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basic-setup/components/u8g2/sys/arm/lpc804/lpc_chip_804/inc/LPC8xx.h Normal file
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// Attention please!
// This is the header file for the LPC80x product family only.
/****************************************************************************
* $Id:: LPC8xx.h 6437 2012-10-31 11:06:06Z dep00694 $
* Project: NXP LPC8xx software example
*
* Description:
* CMSIS Cortex-M0+ Core Peripheral Access Layer Header File for
* NXP LPC800 Device Series
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
****************************************************************************/
#ifndef __LPC8xx_H__
#define __LPC8xx_H__
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup LPC8xx_Definitions LPC8xx Definitions
This file defines all structures and symbols for LPC8xx:
- Registers and bitfields
- peripheral base address
- PIO definitions
@{
*/
/******************************************************************************/
/* Processor and Core Peripherals */
/******************************************************************************/
/** @addtogroup LPC8xx_CMSIS LPC8xx CMSIS Definitions
Configuration of the Cortex-M0+ Processor and Core Peripherals
@{
*/
/*
* ==========================================================================
* ---------- Interrupt Number Definition -----------------------------------
* ==========================================================================
*/
typedef enum IRQn
{
/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset*/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
/****** LPC80x Specific Interrupt Numbers ********************************************************/
SPI0_IRQn = 0, /*!< SPI0 */
DAC0_IRQn = 2, /*!< DAC0 Interrupt */
UART0_IRQn = 3, /*!< USART0 */
UART1_IRQn = 4, /*!< USART1 */
I2C1_IRQn = 7, /*!< I2C1 */
I2C0_IRQn = 8, /*!< I2C0 */
MRT_IRQn = 10, /*!< MRT */
CMP_IRQn = 11, /*!< Analog Comparator /CapTouch */
WDT_IRQn = 12, /*!< WDT */
BOD_IRQn = 13, /*!< BOD */
FLASH_IRQn = 14, /*!< FLASH */
WKT_IRQn = 15, /*!< WKT Interrupt */
ADC_SEQA_IRQn = 16, /*!< ADC Seq. A */
ADC_SEQB_IRQn = 17, /*!< ADC Seq. B */
ADC_THCMP_IRQn = 18, /*!< ADC Thresh Comp */
ADC_OVR_IRQn = 19, /*!< ADC overrun */
CTIMER0_IRQn = 23, /*!< Timer 0 Interrupt */
PININT0_IRQn = 24, /*!< External Interrupt 0 */
PININT1_IRQn = 25, /*!< External Interrupt 1 */
PININT2_IRQn = 26, /*!< External Interrupt 2 */
PININT3_IRQn = 27, /*!< External Interrupt 3 */
PININT4_IRQn = 28, /*!< External Interrupt 4 */
PININT5_IRQn = 29, /*!< External Interrupt 5 */
PININT6_IRQn = 30, /*!< External Interrupt 6 */
PININT7_IRQn = 31, /*!< External Interrupt 7 */
} IRQn_Type;
#define CAPT_IRQn CMP_IRQn
/*
* ==========================================================================
* ----------- Processor and Core Peripheral Section ------------------------
* ==========================================================================
*/
/* Configuration of the Cortex-M0+ Processor and Core Peripherals */
#define __CM0PLUS_REV 0x0001
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
/*@}*/ /* end of group LPC8xx_CMSIS */
#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
#include "system.h" /* System Header */
#if defined ( __CC_ARM )
#pragma anon_unions // This is needed by the Keil compiler
#endif
/******************************************************************************/
/* Device Specific Peripheral Registers structures */
/******************************************************************************/
//------------- System Control (SYSCON) --------------------------------------
typedef struct
{
__IO uint32_t SYSMEMREMAP ; ///< (0x000) System memory remap
__IO uint32_t RESERVED0[8] ; ///< (0x004 - 0x020)
__IO uint32_t LPOSCCTRL ; ///< (0x024) Low power oscillator control
__IO uint32_t FROOSCCTRL ; ///< (0x028) FRO oscillator control
__IO uint32_t RESERVED2[3] ; ///< (0x02C - 0x034)
__IO uint32_t SYSRSTSTAT ; ///< (0x038) System reset status 0
__IO uint32_t RESERVED3[5] ; ///< (0x03C - 0x04C)
__IO uint32_t MAINCLKSEL ; ///< (0x050) Main clock source select
__IO uint32_t MAINCLKUEN ; ///< (0x054) Main clock source update enable
__IO uint32_t SYSAHBCLKDIV ; ///< (0x058) System clock divider
__IO uint32_t RESERVED4[1] ; ///< (0x05C)
__IO uint32_t CAPTCLKSEL ; ///< (0x060) /* Added by Andrew Su 2018-01-18. */
__IO uint32_t ADCCLKSEL ; ///< (0x064) ADC clock source select
__IO uint32_t ADCCLKDIV ; ///< (0x068) ADC clock divider
__IO uint32_t RESERVED5[4] ; ///< (0x06C - 0x078)
__IO uint32_t LPOSCCLKEN ; ///< (0x07C)
union {
__IO uint32_t SYSAHBCLKCTRL[2] ;
struct {
__IO uint32_t SYSAHBCLKCTRL0 ; ///< (0x080) System clock group 0 control
__IO uint32_t SYSAHBCLKCTRL1 ; ///< (0x084) System clock group 1 control
};
};
union {
__IO uint32_t PRESETCTRL[2] ;
struct {
__IO uint32_t PRESETCTRL0 ; ///< (0x088) Peripheral reset group 0 control
__IO uint32_t PRESETCTRL1 ; ///< (0x08C) Peripheral reset group 1 control
};
};
union {
__IO uint32_t FCLKSEL[11] ;
struct {
__IO uint32_t UART0CLKSEL ; ///< (0x090) FCLK0 clock source select
__IO uint32_t UART1CLKSEL ; ///< (0x094) FCLK1 clock source select
__IO uint32_t unimp2CLKSEL ; ///< (0x098) FCLK2 clock source select
__IO uint32_t unimp3CLKSEL ; ///< (0x09C) FCLK3 clock source select
__IO uint32_t unimp4CLKSEL ; ///< (0x0A0) FCLK4 clock source select
__IO uint32_t I2C0CLKSEL ; ///< (0x0A4) FCLK5 clock source select
__IO uint32_t I2C1CLKSEL ; ///< (0x0A8) FCLK6 clock source select
__IO uint32_t unimp7CLKSEL ; ///< (0x0AC) FCLK7 clock source select
__IO uint32_t unimp8CLKSEL ; ///< (0x0B0) FCLK8 clock source select
__IO uint32_t SPI0CLKSEL ; ///< (0x0B4) FCLK9 clock source select
__IO uint32_t unimp10CLKSEL ; ///< (0x0B8) FCLK10 clock source select
};
};
__IO uint32_t RESERVED6[5] ; ///< (0x0BC - 0x0CC)
__IO uint32_t FRG0DIV ; ///< (0x0D0) Fractional generator divider value
__IO uint32_t FRG0MULT ; ///< (0x0D4) Fractional generator multiplier value
__IO uint32_t FRG0CLKSEL ; ///< (0x0D8) FRG0 clock source select
__IO uint32_t RESERVED8[5] ; ///< (0x0DC - 0x0EC)
__IO uint32_t CLKOUTSEL ; ///< (0x0F0) CLKOUT clock source select
__IO uint32_t CLKOUTDIV ; ///< (0x0F4) CLKOUT clock divider
__IO uint32_t RESERVED10[2] ; ///< (0x0F8 - 0x0FC)
__I uint32_t PIOPORCAP0 ; ///< (0x100) POR captured PIO0 status 0
__I uint32_t RESERVED11[19] ; ///< (0x104 - 0x14C)
__IO uint32_t BODCTRL ; ///< (0x150) Brown-Out Detect
__IO uint32_t SYSTCKCAL ; ///< (0x154) System tick counter calibration
__IO uint32_t RESERVED12[6] ; ///< (0x158 - 0x16C)
__IO uint32_t IRQLATENCY ; ///< (0x170) IRQ delay. Allows trade-off between interrupt latency and determinism.
__IO uint32_t NMISRC ; ///< (0x174) NMI Source Control
union {
__IO uint32_t PINTSEL[8] ;
struct {
__IO uint32_t PINTSEL0 ; ///< (0x178) GPIO Pin Interrupt Select 0
__IO uint32_t PINTSEL1 ; ///< (0x17C) GPIO Pin Interrupt Select 1
__IO uint32_t PINTSEL2 ; ///< (0x180) GPIO Pin Interrupt Select 2
__IO uint32_t PINTSEL3 ; ///< (0x184) GPIO Pin Interrupt Select 3
__IO uint32_t PINTSEL4 ; ///< (0x188) GPIO Pin Interrupt Select 4
__IO uint32_t PINTSEL5 ; ///< (0x18C) GPIO Pin Interrupt Select 5
__IO uint32_t PINTSEL6 ; ///< (0x190) GPIO Pin Interrupt Select 6
__IO uint32_t PINTSEL7 ; ///< (0x194) GPIO Pin Interrupt Select 7
};
};
__IO uint32_t RESERVED13[27] ; ///< (0x198 - 0x200)
__IO uint32_t STARTERP0 ; ///< (0x204) Start logic 0 pin wake-up enable
__IO uint32_t RESERVED14[3] ; ///< (0x208 - 0x210)
__IO uint32_t STARTERP1 ; ///< (0x214) Start logic 1 interrupt wake-up enable
__IO uint32_t RESERVED15[6] ; ///< (0x218 - 0x22C)
__IO uint32_t PDSLEEPCFG ; ///< (0x230) Power-down states in deep-sleep mode
__IO uint32_t PDAWAKECFG ; ///< (0x234) Power-down states for wake-up from deep-sleep
__IO uint32_t PDRUNCFG ; ///< (0x238) Power configuration
__IO uint32_t RESERVED16[111] ; ///< (0x23C - 0x3F4)
__I uint32_t DEVICE_ID ; ///< (0x3F8) Device ID
} LPC_SYSCON_TypeDef;
// ---------------- IOCON ----------------
typedef struct {
__IO uint32_t PIO0_17; // 0x00
__IO uint32_t PIO0_13; // 0x04
__IO uint32_t PIO0_12; // 0x08
__IO uint32_t PIO0_5; // 0x0C
__IO uint32_t PIO0_4; // 0x10
__IO uint32_t PIO0_3; // 0x14
__IO uint32_t PIO0_2; // 0x18
__IO uint32_t PIO0_11; // 0x1C
__IO uint32_t PIO0_10; // 0x20
__IO uint32_t PIO0_16; // 0x24
__IO uint32_t PIO0_15; // 0x28
__IO uint32_t PIO0_1; // 0x2C
__IO uint32_t PIO0_21; // 0x30
__IO uint32_t PIO0_9; // 0x34
__IO uint32_t PIO0_8; // 0x38
__IO uint32_t PIO0_7; // 0x3C
__IO uint32_t PIO0_29; // 0x40
__IO uint32_t PIO0_0; // 0x44
__IO uint32_t PIO0_14; // 0x48
__IO uint32_t PIO0_28; // 0x4C
__IO uint32_t PIO0_27; // 0x50
__IO uint32_t PIO0_26; // 0x54
__IO uint32_t PIO0_20; // 0x58
__IO uint32_t PIO0_30; // 0x5C
__IO uint32_t PIO0_19; // 0x60
__IO uint32_t PIO0_25; // 0x64
__IO uint32_t PIO0_24; // 0x68
__IO uint32_t PIO0_23; // 0x6C
__IO uint32_t PIO0_22; // 0x70
__IO uint32_t PIO0_18; // 0x74
} LPC_IOCON_TypeDef;
//------------- Power Management Unit (PMU) --------------------------
typedef struct
{
__IO uint32_t PCON; //!< Offset: 0x000 Power control Register (R/W)
__IO uint32_t GPREG0; //!< Offset: 0x004 General purpose Register 0 (R/W)
__IO uint32_t GPREG1; //!< Offset: 0x008 General purpose Register 1 (R/W)
__IO uint32_t GPREG2; //!< Offset: 0x00C General purpose Register 2 (R/W)
__IO uint32_t GPREG3; //!< Offset: 0x010 General purpose Register 3 (R/W)
__IO uint32_t GPREG4; //!< Offset: 0x014 General purpose Register 4 (R/W)
__I uint32_t RESERVED[2]; // 0x18 - 0x1C
__IO uint32_t WUSRCREG; // 0x20
__IO uint32_t WUENAREG; // 0x24
} LPC_PMU_TypeDef;
//------------- Switch Matrix (SWM) --------------------------
typedef struct
{
union {
__IO uint32_t PINASSIGN[10];
struct {
__IO uint32_t PINASSIGN0; // 0x000
__IO uint32_t PINASSIGN1; // 0x004
__IO uint32_t PINASSIGN2; // 0x008
__IO uint32_t PINASSIGN3; // 0x00C
__IO uint32_t PINASSIGN4; // 0x010
__IO uint32_t PINASSIGN5; // 0x014
__IO uint32_t PINASSIGN6; // 0x018
__IO uint32_t PINASSIGN7; // 0x01C
__IO uint32_t PINASSIGN8; // 0x020
__IO uint32_t PINASSIGN9; // 0x024
};
};
__I uint32_t Reserved0[86]; // 0x028 - 0x17C
__IO uint32_t PINASSIGN_4PIN; // 0x180
__I uint32_t Reserved1[15]; // 0x184 - 0x1BC
__IO uint32_t PINENABLE0; // 0x1C0
__IO uint32_t PINENABLE1; // 0x1C4
} LPC_SWM_TypeDef;
// ------------------------------------------------------------------------------------------------
// ----- General Purpose I/O (GPIO) -----
// ------------------------------------------------------------------------------------------------
typedef struct {
__IO uint8_t B0[32]; // 0x00 - 0x1F Byte pin registers P0.0 - P0.31
__IO uint8_t B1[32]; // 0x20 - 0x3F Byte pin registers P1.0 - P1.31
__I uint8_t Reserved0[4032]; // 0x40 - 0xFFF
__IO uint32_t W0[32]; // 0x1000 - 0x107C Word pin registers P0.0 - P0.31
__IO uint32_t W1[32]; // 0x1080 - 0x10FC Word pin registers P1.0 - P1.31
__I uint32_t Reserved1[960]; // 0x1100 - 0x1FFC (960d = 0x3c0)
union {
__IO uint32_t DIR[2]; // 0x2000 - 0x2004
struct {
__IO uint32_t DIR0; // 0x2000
__IO uint32_t DIR1; // 0x2004
};
};
__I uint32_t Reserved2[30]; // 0x2008 - 0x207C
union {
__IO uint32_t MASK[2]; // 0x2080 - 0x2084
struct {
__IO uint32_t MASK0; // 0x2080
__IO uint32_t MASK1; // 0x2084
};
};
__I uint32_t Reserved3[30]; // 0x2088 - 0x20FC
union {
__IO uint32_t PIN[2]; // 0x2100 - 0x2104
struct {
__IO uint32_t PIN0; // 0x2100
__IO uint32_t PIN1; // 0x2104
};
};
__I uint32_t Reserved4[30]; // 0x2108 - 0x217C
union {
__IO uint32_t MPIN[2]; // 0x22180 - 0x2184
struct {
__IO uint32_t MPIN0; // 0x2180
__IO uint32_t MPIN1; // 0x2184
};
};
__I uint32_t Reserved5[30]; // 0x2188 - 0x21FC
union {
__IO uint32_t SET[2]; // 0x2200 -0x2204
struct {
__IO uint32_t SET0; // 0x2200
__IO uint32_t SET1; // 0x2204
};
};
__I uint32_t Reserved6[30]; // 0x2208 - 0x227C
union {
__O uint32_t CLR[2]; // 0x2280 - 0x2284
struct {
__O uint32_t CLR0; // 0x2280
__O uint32_t CLR1; // 0x2284
};
};
__I uint32_t Reserved7[30]; // 0x2288 - 0x22FC
union {
__O uint32_t NOT[2]; // 0x2300 - 0x2304
struct {
__O uint32_t NOT0; // 0x2300
__O uint32_t NOT1; // 0x2304
};
};
__I uint32_t Reserved8[30]; // 0x2308 - 0x237C
union {
__O uint32_t DIRSET[2]; // 0x2380 - 0x2384
struct {
__O uint32_t DIRSET0; // 0x2380
__O uint32_t DIRSET1; // 0x2384
};
};
__I uint32_t Reserved9[30]; // 0x2388 - 0x23FC
union {
__O uint32_t DIRCLR[2]; // 0x2400 - 0x2404
struct {
__O uint32_t DIRCLR0; // 0x2400
__O uint32_t DIRCLR1; // 0x2404
};
};
__I uint32_t Reserved10[30]; // 0x2408 - 0x247C
union {
__O uint32_t DIRNOT[2]; // 0x2480 - 0x2484
struct {
__O uint32_t DIRNOT0; // 0x2480
__O uint32_t DIRNOT1; // 0x2484
};
};
} LPC_GPIO_PORT_TypeDef;
// ------------------------------------------------------------------------------------------------
// ----- Pin Interrupts and Pattern Match (PIN_INT) -----
// ------------------------------------------------------------------------------------------------
typedef struct { /*!< (@ 0xA0004000) PIN_INT Structure */
__IO uint32_t ISEL; /*!< (@ 0xA0004000) Pin Interrupt Mode register */
__IO uint32_t IENR; /*!< (@ 0xA0004004) Pin Interrupt Enable (Rising) register */
__IO uint32_t SIENR; /*!< (@ 0xA0004008) Set Pin Interrupt Enable (Rising) register */
__IO uint32_t CIENR; /*!< (@ 0xA000400C) Clear Pin Interrupt Enable (Rising) register */
__IO uint32_t IENF; /*!< (@ 0xA0004010) Pin Interrupt Enable Falling Edge / Active Level register */
__IO uint32_t SIENF; /*!< (@ 0xA0004014) Set Pin Interrupt Enable Falling Edge / Active Level register */
__IO uint32_t CIENF; /*!< (@ 0xA0004018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
__IO uint32_t RISE; /*!< (@ 0xA000401C) Pin Interrupt Rising Edge register */
__IO uint32_t FALL; /*!< (@ 0xA0004020) Pin Interrupt Falling Edge register */
__IO uint32_t IST; /*!< (@ 0xA0004024) Pin Interrupt Status register */
__IO uint32_t PMCTRL; /*!< (@ 0xA0004028) GPIO pattern match interrupt control register */
__IO uint32_t PMSRC; /*!< (@ 0xA000402C) GPIO pattern match interrupt bit-slice source register */
__IO uint32_t PMCFG; /*!< (@ 0xA0004030) GPIO pattern match interrupt bit slice configuration register */
} LPC_PIN_INT_TypeDef;
//------------- CRC Engine (CRC) -----------------------------------------
typedef struct
{
__IO uint32_t MODE;
__IO uint32_t SEED;
union {
__I uint32_t SUM;
__O uint32_t WR_DATA;
};
} LPC_CRC_TypeDef;
//------------- Comparator (CMP) --------------------------------------------------
typedef struct { /*!< (@ 0x40024000) CMP Structure */
__IO uint32_t CTRL; /*!< (@ 0x40024000) Comparator control register */
__IO uint32_t LAD; /*!< (@ 0x40024004) Voltage ladder register */
} LPC_CMP_TypeDef;
//------------- Self Wakeup Timer (WKT) --------------------------------------------------
typedef struct { /*!< (@ 0x40028000) WKT Structure */
__IO uint32_t CTRL; /*!< (@ 0x40028000) Alarm/Wakeup Timer Control register */
uint32_t Reserved[2];
__IO uint32_t COUNT; /*!< (@ 0x4002800C) Alarm/Wakeup TImer counter register */
} LPC_WKT_TypeDef;
//------------- Multi-Rate Timer (MRT) --------------------------------------------------
typedef struct {
__IO uint32_t INTVAL;
__IO uint32_t TIMER;
__IO uint32_t CTRL;
__IO uint32_t STAT;
} MRT_Channel_cfg_Type;
typedef struct {
MRT_Channel_cfg_Type Channel[4];
uint32_t Reserved0[45]; // Address offsets = 0x40 - 0xF0
__IO uint32_t IDLE_CH;
__IO uint32_t IRQ_FLAG;
} LPC_MRT_TypeDef;
//------------- USART -----------
typedef struct
{
__IO uint32_t CFG;
__IO uint32_t CTL;
__IO uint32_t STAT;
__IO uint32_t INTENSET;
__O uint32_t INTENCLR;
__I uint32_t RXDAT;
__I uint32_t RXDATSTAT;
__IO uint32_t TXDAT;
__IO uint32_t BRG;
__I uint32_t INTSTAT;
__IO uint32_t OSR;
__IO uint32_t ADDR;
} LPC_USART_TypeDef;
//------------- SPI -----------------------
typedef struct
{
__IO uint32_t CFG; /* 0x00 */
__IO uint32_t DLY;
__IO uint32_t STAT;
__IO uint32_t INTENSET;
__O uint32_t INTENCLR; /* 0x10 */
__I uint32_t RXDAT;
__IO uint32_t TXDATCTL;
__IO uint32_t TXDAT;
__IO uint32_t TXCTL; /* 0x20 */
__IO uint32_t DIV;
__I uint32_t INTSTAT;
} LPC_SPI_TypeDef;
//------------- I2C -------------------------------
typedef struct
{
__IO uint32_t CFG; /* 0x00 */
__IO uint32_t STAT;
__IO uint32_t INTENSET;
__O uint32_t INTENCLR;
__IO uint32_t TIMEOUT; /* 0x10 */
union {
__IO uint32_t CLKDIV;
__IO uint32_t DIV;
};
__IO uint32_t INTSTAT;
uint32_t Reserved0[1];
__IO uint32_t MSTCTL; /* 0x20 */
__IO uint32_t MSTTIME;
__IO uint32_t MSTDAT;
uint32_t Reserved1[5];
__IO uint32_t SLVCTL; /* 0x40 */
__IO uint32_t SLVDAT;
__IO uint32_t SLVADR0;
__IO uint32_t SLVADR1;
__IO uint32_t SLVADR2; /* 0x50 */
__IO uint32_t SLVADR3;
__IO uint32_t SLVQUAL0;
uint32_t Reserved2[9];
__I uint32_t MONRXDAT; /* 0x80 */
} LPC_I2C_TypeDef;
//------------------- Standard Counter/Timer (CTIMER) ---------------------
typedef struct {
__IO uint32_t IR; // 0x00
__IO uint32_t TCR; // 0x04
__IO uint32_t TC; // 0x08
__IO uint32_t PR; // 0x0C
__IO uint32_t PC; // 0x10
__IO uint32_t MCR; // 0x14
__IO uint32_t MR[4]; // 0x18 - 0x24
__IO uint32_t CCR; // 0x28
__IO uint32_t CR[4]; // 0x2C - 0x38
__IO uint32_t EMR; // 0x3C
__I uint32_t RESERVED0[12]; // 0x40 - 0x6C
__IO uint32_t CTCR; // 0x70
__IO uint32_t PWMC; // 0x74
} LPC_TIMER_TypeDef;
//------------- Widowed Watchdog Timer (WWDT) -----------------------------------------
typedef struct
{
__IO uint32_t MOD; /*!< Offset: 0x000 Watchdog mode register (R/W) */
__IO uint32_t TC; /*!< Offset: 0x004 Watchdog timer constant register (R/W) */
__O uint32_t FEED; /*!< Offset: 0x008 Watchdog feed sequence register (W) */
__I uint32_t TV; /*!< Offset: 0x00C Watchdog timer value register (R) */
uint32_t RESERVED; /*!< Offset: 0x010 RESERVED */
__IO uint32_t WARNINT; /*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */
__IO uint32_t WINDOW; /*!< Offset: 0x018 Watchdog timer window value register (R/W) */
} LPC_WWDT_TypeDef;
//------------- ADC -----------------------------------------
typedef struct {
__IO uint32_t CTRL; // 0x0
uint32_t RESERVED0; // 0x4
__IO uint32_t SEQA_CTRL; // 0x8
__IO uint32_t SEQB_CTRL; // 0xC
__IO uint32_t SEQA_GDAT; // 0x10
__IO uint32_t SEQB_GDAT; // 0x14
uint32_t RESERVED1[2]; // 0x18 - 0x1C
__IO uint32_t DAT[12]; // 0x20 - 0x4C
__IO uint32_t THR0_LOW; // 0x50
__IO uint32_t THR1_LOW; // 0x54
__IO uint32_t THR0_HIGH; // 0x58
__IO uint32_t THR1_HIGH; // 0x5C
__IO uint32_t CHAN_THRSEL; // 0x60
__IO uint32_t INTEN; // 0x64
__IO uint32_t FLAGS; // 0x68
__IO uint32_t TRM; // 0x6C
} LPC_ADC_TypeDef;
//------------- DAC ----------------
typedef struct {
__IO uint32_t CR; // 0x00
__IO uint32_t CTRL; // 0x04
__IO uint32_t CNTVAL; // 0x08
} LPC_DAC_TypeDef;
//------------- Capacitive Touch module (CAPT) ----------------
typedef struct {
__IO uint32_t CTRL; // 0x00
__IO uint32_t STATUS; // 0x04
__IO uint32_t POLL_TCNT; // 0x08
__I uint32_t reserved0; // 0x0C
__IO uint32_t INTENSET; // 0x10
__O uint32_t INTENCLR; // 0x14
__I uint32_t INTSTAT; // 0x18
__I uint32_t reserved1; // 0x1C
__I uint32_t TOUCH; // 0x20
__I uint32_t A_hole[1014];// 0x24 - 0xFF8
__I uint32_t ID; // 0xFFC
} LPC_CAPT_TypeDef;
#define LUT_INs 5
#define PLU_INs 6
#define PLU_LUTs 26
#define PLU_FFs 4
#define PLU_OUTs 8
typedef struct {
struct { /* Input select register for LUT & Input... */
union {
__IO uint32_t INP[8]; /* Each LUT has maximum 5 inputs, the remaining are reserved. */
struct {
__IO uint32_t INP0;
__IO uint32_t INP1;
__IO uint32_t INP2;
__IO uint32_t INP3;
__IO uint32_t INP4;
uint32_t RESERVED[3];
};
} LUT_MUX[PLU_LUTs];
};
uint32_t RESERVED0[8*64-8*PLU_LUTs]; /* ...-0x7FC */
__IO uint32_t LUT_TRUTH[PLU_LUTs]; /* Truth-Table ("Look-up Table") programming */
uint32_t RESERVED1[64-PLU_LUTs]; /* ...-0x8FC */
__I uint32_t OUTPUTS; /* PLU Outputs Register (Read-only) */
uint32_t RESERVED2[3*64-1]; /* ...-0xBFC */
__IO uint32_t OUTPUT_MUX[PLU_OUTs]; /* Select register for PLU Ouptut */
} LPC_PLU_TypeDef;
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
/******************************************************************************/
/* Peripheral memory map */
/******************************************************************************/
// Base addresses
#define LPC_FLASH_BASE (0x00000000UL)
#define LPC_RAM_BASE (0x10000000UL)
#define LPC_ROM_BASE (0x1FFF0000UL)
#define LPC_APB0_BASE (0x40000000UL)
#define LPC_AHB_BASE (0x50000000UL)
// APB0 peripherals
#define LPC_WWDT_BASE (LPC_APB0_BASE + 0x00000)
#define LPC_MRT_BASE (LPC_APB0_BASE + 0x04000)
#define LPC_WKT_BASE (LPC_APB0_BASE + 0x08000)
#define LPC_SWM_BASE (LPC_APB0_BASE + 0x0C000)
// (LPC_APB0_BASE + 0x10000)
#define LPC_DAC0_BASE (LPC_APB0_BASE + 0x14000)
// (LPC_APB0_BASE + 0x18000)
#define LPC_ADC_BASE (LPC_APB0_BASE + 0x1C000)
#define LPC_PMU_BASE (LPC_APB0_BASE + 0x20000)
#define LPC_CMP_BASE (LPC_APB0_BASE + 0x24000)
#define LPC_PLU_BASE (LPC_APB0_BASE + 0x28000)
// (LPC_APB0_BASE + 0x2C000)
// (LPC_APB0_BASE + 0x30000)
// (LPC_APB0_BASE + 0x34000)
#define LPC_CTIMER0_BASE (LPC_APB0_BASE + 0x38000)
// (LPC_APB0_BASE + 0x38000)
#define LPC_FLASHCTRL_BASE (LPC_APB0_BASE + 0x40000)
#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000)
#define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000)
#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x50000)
#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x54000)
#define LPC_SPI0_BASE (LPC_APB0_BASE + 0x58000)
// (LPC_APB0_BASE + 0x5C000)
#define LPC_CAPT_BASE (LPC_APB0_BASE + 0x60000)
#define LPC_USART0_BASE (LPC_APB0_BASE + 0x64000)
#define LPC_USART1_BASE (LPC_APB0_BASE + 0x68000)
// (LPC_APB0_BASE + 0x6C000)
// (LPC_APB0_BASE + 0x70000)
// (LPC_APB0_BASE + 0x74000)
// AHB peripherals
#define LPC_CRC_BASE (LPC_AHB_BASE + 0x00000)
// (LPC_AHB_BASE + 0x04000)
// (LPC_AHB_BASE + 0x08000)
// (LPC_AHB_BASE + 0x0C000)
// (LPC_AHB_BASE + 0x10000)
#define LPC_GPIO_PORT_BASE (0xA0000000)
#define LPC_PIN_INT_BASE (LPC_GPIO_PORT_BASE + 0x4000)
/******************************************************************************/
/* Peripheral declarations */
/******************************************************************************/
#define LPC_WWDT ((LPC_WWDT_TypeDef *) LPC_WWDT_BASE )
#define LPC_MRT ((LPC_MRT_TypeDef *) LPC_MRT_BASE )
#define LPC_WKT ((LPC_WKT_TypeDef *) LPC_WKT_BASE )
#define LPC_SWM ((LPC_SWM_TypeDef *) LPC_SWM_BASE )
#define LPC_DAC0 ((LPC_DAC_TypeDef *) LPC_DAC0_BASE )
#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
#define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE )
#define LPC_CMP ((LPC_CMP_TypeDef *) LPC_CMP_BASE )
#define LPC_CTIMER0 ((LPC_TIMER_TypeDef *) LPC_CTIMER0_BASE )
#define LPC_FLASHCTRL ((LPC_FLASHCTRL_TypeDef *) LPC_FLASHCTRL_BASE )
#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
#define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
#define LPC_SPI0 ((LPC_SPI_TypeDef *) LPC_SPI0_BASE )
#define LPC_CAPT ((LPC_CAPT_TypeDef *) LPC_CAPT_BASE )
#define LPC_USART0 ((LPC_USART_TypeDef *) LPC_USART0_BASE )
#define LPC_USART1 ((LPC_USART_TypeDef *) LPC_USART1_BASE )
#define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE )
#define LPC_GPIO_PORT ((LPC_GPIO_PORT_TypeDef *) LPC_GPIO_PORT_BASE )
#define LPC_PIN_INT ((LPC_PIN_INT_TypeDef *) LPC_PIN_INT_BASE )
#define LPC_PLU0 ((LPC_PLU_TypeDef *) LPC_PLU_BASE)
///////////////////////////////////////////////////////////////////////////////
// Other chip-specific macro definitions (a.k.a. the chip.h section)
///////////////////////////////////////////////////////////////////////////////
// ACMP_I-to-IOCON mapping
#define ACMP_I1_PORT PIO0_0
#define ACMP_I2_PORT PIO0_1
#define ACMP_I3_PORT PIO0_14
#define ACMP_I4_PORT PIO0_16
#define ACMP_I5_PORT PIO0_21
// For looping through the pad controls
#define NUM_IOCON_SLOTS 30
#ifdef __cplusplus
}
#endif
#endif /* __LPC8xx_H__ */

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/*
* lpc8xx_acomp.h
*
* Created on: Apr 7, 2016
* Author:
*/
#ifndef LPC8XX_ACOMP_H_
#define LPC8XX_ACOMP_H_
// CTRL register shifters
#define HYS 25
#define INTENA 24
#define COMPEDGE 23
#define COMPSTAT 21
#define EDGECLR 20
#define COMP_VM_SEL 11
#define COMP_VP_SEL 8
#define COMPSA 6
#define EDGESEL 3
// HYS field descriptors
#define _20mV 0x3
#define _10mV 0x2
#define _5mV 0x1
#define NONE 0x0
// COMP_VM_SEL and COMP_VP_SEL field descriptors
#define DAC_OUT_0 0x7
#define V_BANDGAP 0x6
#define ACOMP_IN5 0x5
#define ACOMP_IN4 0x4
#define ACOMP_IN3 0x3
#define ACOMP_IN2 0x2
#define ACOMP_IN1 0x1
#define V_LADDER_OUT 0x0
// EDGESEL field descriptors
#define BOTH 0x3
#define RISING 0x1
#define FALLING 0x0
// LAD register shifters
#define LADREF 6
#define LADSEL 1
#define LADEN 0
// LADREF field descriptors
#define VDDCMP_PIN 1
#define SUPPLY_VDD 0
#endif /* LPC8XX_ACOMP_H_ */

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/*
* lpc8xx_adc.h
*
* Created on: This day, August 18, 2016
* Author: The Creator
*/
#ifndef LPC8XX_ADC_H_
#define LPC8XX_ADC_H_
// CTRL register shifters
#define ADC_CLKDIV 0
#define ADC_LPWRMODE 10
#define ADC_CALMODE 30
// Sequence A and B control register shifters
#define ADC_CHANNELS 0
#define ADC_TRIGGER 12
#define ADC_TRIGPOL 18
#define ADC_SYNCBYPASS 19
#define ADC_START 26
#define ADC_BURST 27
#define ADC_SINGLESTEP 28
#define ADC_LOWPRIO 29
#define ADC_MODE 30
#define ADC_SEQ_ENA 31
// ADC hardware trigger inputs
#define NO_TRIGGER 0
#define PININT0_IRQ 1
#define PININT1_IRQ 2
#define TIM0_MAT3 5
#define CMP0_OUT_ADC 6
#define GPIO_INT_BMATCH 7
#define ARM_TXEV 8
// Threshold compare register shifters
#define THRLOW 15
#define THRHIGH 15
// INTEN register shifters
#define SEQA_INTEN 0
#define SEQB_INTEN 1
#define OVR_INTEN 2
#define ADCMPINTEN0 3
#define ADCMPINTEN1 5
#define ADCMPINTEN2 7
#define ADCMPINTEN3 9
#define ADCMPINTEN4 11
#define ADCMPINTEN5 13
#define ADCMPINTEN6 15
#define ADCMPINTEN7 17
#define ADCMPINTEN8 19
#define ADCMPINTEN9 21
#define ADCMPINTEN10 23
#define ADCMPINTEN11 25
// FLAGS register shifters
#define ADC_THCMP0 0
#define ADC_THCMP1 1
#define ADC_THCMP2 2
#define ADC_THCMP3 3
#define ADC_THCMP4 4
#define ADC_THCMP5 5
#define ADC_THCMP6 6
#define ADC_THCMP7 7
#define ADC_THCMP8 8
#define ADC_THCMP9 9
#define ADC_THCMP10 10
#define ADC_THCMP11 11
#define ADC_OVERRUN0 12
#define ADC_OVERRUN1 13
#define ADC_OVERRUN2 14
#define ADC_OVERRUN3 15
#define ADC_OVERRUN4 16
#define ADC_OVERRUN5 17
#define ADC_OVERRUN6 18
#define ADC_OVERRUN7 19
#define ADC_OVERRUN8 20
#define ADC_OVERRUN9 21
#define ADC_OVERRUN10 22
#define ADC_OVERRUN11 23
#define ADC_SEQA_OVR 24
#define ADC_SEQB_OVR 25
#define ADC_SEQA_INT 28
#define ADC_SEQB_INT 29
#define ADC_THCMP_INT 30
#define ADC_OVR_INT 31
// TRM register shifters
#define ADC_VRANGE 5
#endif /* LPC8XX_ADC_H_ */

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/*
* board.h
*
* Created on:
* Author:
*/
#ifndef BOARD_H_
#define BOARD_H_
//#define XPRESSO_812_BOARD // For the LPC812 Max board
//#define XPRESSO_824_BOARD // For the LPC824 Max board
//#define XPRESSO_845_BOARD // For the LPC845 Max board
//#define XPRESSO_802_BOARD // For the LPC802 Max board
#define XPRESSO_804_BOARD // For the LPC804 Max board
// LPC812 Max board
#ifdef XPRESSO_812_BOARD
#define RED (1<<7)
#define BLUE (1<<16)
#define GREEN (1<<17)
#define red_led_port P0_7
#define blue_led_port P0_16
#define green_led_port P0_17
#define PCF8591_address 0x4F // The on-board ADC/DAC default I2C address
#define PCA9672_address 0x23 // The on-board GPIO Expander default I2C address
#define TARGET_TX P0_6 // For the VCOM serial port
#define TARGET_RX P0_1 // For the VCOM serial port
#define NUM_IOCON_P0_SLOTS 19 // For looping through the pad controls
#endif
// LPC824 Max board
#ifdef XPRESSO_824_BOARD
#define RED (1<<12)
#define BLUE (1<<27)
#define GREEN (1<<16)
#define red_led_port P0_12
#define blue_led_port P0_27
#define green_led_port P0_16
#define TARGET_TX P0_7 // For the VCOM serial port
#define TARGET_RX P0_18 // For the VCOM serial port
#define NUM_IOCON_P0_SLOTS 31 // For looping through the pad controls
#endif
// LPC845 Max board
#ifdef XPRESSO_845_BOARD
#define LED_RED P0_12
#define LED_BLUE P1_15
#define LED_GREEN P0_0
#define TARGET_TX P1_17 // For the VCOM serial port
#define TARGET_RX P1_16 // For the VCOM serial port
#define DACOUT0_PIN PIO0_17
#define DACOUT1_PIN PIO0_29
#define AUDIO_AMP_ENABLE_PORT PORT1
#define AUDIO_AMP_ENABLE_PIN Bit11
#define NUM_IOCON_P0_SLOTS 56 // For looping through the pad controls
#endif
// LPC802 MAX board
#ifdef XPRESSO_802_BOARD
#define LED_BLUE P0_8
#define LED_RED P0_9
#define LED_GREEN P0_12
#define TARGET_TX P0_4 // For the VCOM serial port
#define TARGET_RX P0_0 // For the VCOM serial port
#endif
// LPC804 MAX board
#ifdef XPRESSO_804_BOARD
#define LED_BLUE P0_11
#define LED_RED P0_13
#define LED_GREEN P0_12
#define TARGET_TX P0_4 // For the VCOM serial port
#define TARGET_RX P0_0 // For the VCOM serial port
#define TARTET_I2CSCL P0_14
#define TARTET_I2CSDA P0_7
#define DACOUT_PIN PIO0_19
#endif
#endif /* BOARD_H_ */

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/*
* lpc8xx_capt.h
*
* Created on: This day
* Author: The Creator
*/
#ifndef LPC8XX_CAPT_H_
#define LPC8XX_CAPT_H_
#define CAPT_X_PIN_COUNT 5U
// CTRL register
#define POLLMODE_INACTIVE (0x0<<0)
#define POLLMODE_NOW (0x1<<0)
#define POLLMODE_CONTINUOUS (0x2<<0)
#define POLLMODE_LOWPWR (0x3<<0)
#define POLLMODE 0 // Use this as a shifter for a 2-bit value
#define TYPE_NORMAL (0x0<<2)
#define TYPE_3x3 (0x1<<2)
#define TYPE_5_INTERLEAVE (0x2<<2)
#define TYPE_TRIGGER_YH (0x0<<4)
#define TYPE_TRIGGER_ACMP (0x1<<4)
#define WAIT (0x1<<5)
#define DMA_NONE (0x0<<6)
#define DMA_TOUCH (0x1<<6)
#define DMA_BOTH (0x2<<6)
#define DMA_BOTH_PLUS_TO (0x3<<6)
#define FDIV 8 // Use this as a shifter for a 4-bit value
#define XPINUSE_HIGHZ (0x0<<12)
#define XPINUSE_LOW (0x1<<12)
#define INCHANGE (0x1<<15) // Use as an AND-mask, when reading this bit
#define X0_ACTV 1<<0
#define X1_ACTV 1<<1
#define X2_ACTV 1<<2
#define X3_ACTV 1<<3
#define X4_ACTV 1<<4
#define X5_ACTV 1<<5
#define X6_ACTV 1<<6
#define X7_ACTV 1<<7
#define X8_ACTV 1<<8
#define X9_ACTV 1<<9
#define X10_ACTV 1<<10
#define X11_ACTV 1<<11
#define X12_ACTV 1<<12
#define X13_ACTV 1<<13
#define X14_ACTV 1<<14
#define X15_ACTV 1<<15
#define XPINSEL 16 // Use this as a shifter for a 16-bit value
// STATUS, INTENSET, INTENCLR, INTSTAT registers
#define YESTOUCH (1<<0)
#define NOTOUCH (1<<1)
#define POLLDONE (1<<2)
#define TIMEOUT (1<<3)
#define OVERRUN (1<<4)
#define BUSY (1<<8)
#define XMAX (0xFF<<16) // Use as an AND-mask, when reading this field
// POLL_TCNT register
#define TCNT 0 // Use this as a shifter for a 12-bit value
#define TOUT 12 // Use this as a shifter for a 4-bit value
#define POLL 16 // Use this as a shifter for an 8-bit value
#define MDELAY 24 // Use this as a shifter for a 2-bit value
#define RDELAY 26 // Use this as a shifter for a 2-bit value
#define TCHLOWER 31 // Use this as a shifter for a 1-bit value
// TOUCH register
#define TOUCH_COUNT (0xFFF<<0) // Use as an AND-mask, when reading this field
#define TOUCH_XVAL (0xF<<12) // Use as an AND-mask, when reading this field
#define TOUCH_ISTOUCH (0x1<<16) // Use as an AND-mask, when reading this field
#define TOUCH_ISTO (0x1<<17) // Use as an AND-mask, when reading this field
#define TOUCH_SEQ (0xF<<20) // Use as an AND-mask, when reading this field
#define TOUCH_CHANGE (0x1<<31) // Use as an AND-mask, when reading this field
#endif /* LPC8XX_CAPT_H_ */

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#include "board.h"
//
// The following parameters need to be defined for each project's inital clock setup (used in system.c))
//
#define FRO_FREQ_VAL 2 // 0 = 18 MHz
// 1 = 24 MHz (reset value)
// 2 = 30 MHz
#define MAINCLKSEL_VAL 0 // 00 = fro (reset value)
// 01 = external_clk
// 10 = lposc_clk
// 11 = fro_div
#define SYSAHBCLKDIV_VAL 1 // 0x00 = system_ahb_clk disabled (use with caution)
// 0x01 = divide_by_1 (reset value)
// 0x02 = divide_by_2
// 0xFF = divide_by_255
#define CLKIN_CLK_VAL 12000000 // External Clock (CLKIN) frequency [Hz] must be in the range of 1 MHz to 25 MHz
#define EXT_CLOCK_FORCE_ENABLE 0 // Force config. and enable of external_clk for use by other than main_clk
// 0 = external_clk will be configured and enabled only if needed by main_clk or sys_pll0_clk.
// 1 = external_clk will be configured and enabled (available for other, e.g. clock out).
// End of clocks configuration section
//
// The following parameters need to be defined for projects that use the debug UART (used in serial.c)
//
#define DBGUART 0 // Choose the index for the debug UART (0 for UART0, 1 for UART1, etc.)
#define DBGBAUDRATE 9600 // Choose the baud rate for the debug UART
#define USE_VCOM_PORT 1 // '1' to use VCOM serial port, '0' to use user-defined port pins for debug UART
#if (USE_VCOM_PORT == 1)
#define DBGTXPIN TARGET_TX // For VCOM serial port (see board.h)
#define DBGRXPIN TARGET_RX // For VCOM serial port (see board.h)
#else
#define DBGTXPIN P0_15 // Use with USB-to-RS232 break-out cable (choose your own favorite TxD pin)
#define DBGRXPIN P0_14 // Use with USB-to-RS232 break-out cable (choose your own favorite RxD pin)
#endif
//
// The following are so the debug UART is selectable from any UART on the device (used in Serial.c)
//
#define __CONCAT(x,y,z) x##y##z
#define __XCONCAT(x,y,z) __CONCAT(x,y,z)
#define INDEX DBGUART
#define pDBGU __XCONCAT(LPC_USART,INDEX,)
#define DBGU __XCONCAT(UART,INDEX,)
#define DBGUTXD __XCONCAT(U,INDEX,_TXD)
#define DBGURXD __XCONCAT(U,INDEX,_RXD)
#define DBGURST __XCONCAT(UART,INDEX,_RST_N)
#define DBGUIRQ __XCONCAT(UART,INDEX,_IRQn)

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/**************************************************************************//**
* @file core_cm0plus.h
* @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
* @version V3.01
* @date 22. March 2012
*
* @note
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
#ifdef __cplusplus
extern "C" {
#endif
#ifndef __CORE_CM0PLUS_H_GENERIC
#define __CORE_CM0PLUS_H_GENERIC
/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/** \ingroup Cortex-M0+
@{
*/
/* CMSIS CM0P definitions */
#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
#define __CM0PLUS_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
__CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00) /*!< Cortex-M Core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#endif
/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
*/
#define __FPU_USED 0
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include <stdint.h> /* standard types definitions */
#include <core_cmInstr.h> /* Core Instruction Access */
#include <core_cmFunc.h> /* Core Function Access */
#endif /* __CORE_CM0PLUS_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0PLUS_H_DEPENDANT
#define __CORE_CM0PLUS_H_DEPENDANT
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0PLUS_REV
#define __CM0PLUS_REV 0x0000
#warning "__CM0PLUS_REV not defined in device header file; using default!"
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __VTOR_PRESENT
#define __VTOR_PRESENT 0
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/*@} end of group Cortex-M0+ */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core MPU Register
******************************************************************************/
/** \defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/** \brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
#else
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
#endif
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
#else
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
#endif
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/** \brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/*@} end of group CMSIS_CORE */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31];
__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31];
__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31];
__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31];
uint32_t RESERVED4[64];
__IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/** \brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
#if (__VTOR_PRESENT == 1)
__IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
#else
uint32_t RESERVED0;
#endif
__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
#if (__VTOR_PRESENT == 1)
/* SCB Interrupt Control State Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
#endif
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/** \brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
#if (__MPU_PRESENT == 1)
/** \ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/** \brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
__IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
} MPU_Type;
/* MPU Type Register */
#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register */
#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register */
#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register */
#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register */
#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
are only accessible over DAP and not via processor. Therefore
they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Cortex-M0+ Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#if (__MPU_PRESENT == 1)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
/** \brief Enable External Interrupt
The function enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Disable External Interrupt
The function disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Get Pending Interrupt
The function reads the pending register in the NVIC and returns the pending bit
for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
/** \brief Set Pending Interrupt
The function sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Clear Pending Interrupt
The function clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
}
/** \brief Set Interrupt Priority
The function sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if(IRQn < 0) {
SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
else {
NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
}
/** \brief Get Interrupt Priority
The function reads the priority of an interrupt. The interrupt
number can be positive to specify an external (device specific)
interrupt, or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority. Value is aligned automatically to the implemented
priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if(IRQn < 0) {
return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0+ system interrupts */
else {
return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
}
/** \brief System Reset
The function initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
while(1); /* wait until reset */
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if (__Vendor_SysTickConfig == 0)
/** \brief System Tick Configuration
The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#endif /* __CORE_CM0PLUS_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V3.01
* @date 06. March 2012
*
* @note
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) );
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
return(result);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

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/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V3.01
* @date 06. March 2012
*
* @note
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
#define __WFI __wfi
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
{
__ASM volatile ("isb");
}
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
{
__ASM volatile ("dsb");
}
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
{
__ASM volatile ("dmb");
}
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
{
uint32_t result;
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
__ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
return(op1);
}
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint8_t result;
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint16_t result;
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
{
__ASM volatile ("clrex");
}
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
{
uint8_t result;
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

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#ifndef LPC8XX_CTIMER_H_
#define LPC8XX_CTIMER_H_
// Interrupt Register (IR) shifters
#define MR0INT 0
#define MR1INT 1
#define MR2INT 2
#define MR3INT 3
#define CR0INT 4
#define CR1INT 5
#define CR2INT 6
#define CR3INT 7
// Timer Control Register (TCR) shifters
#define CEN 0
#define CRST 1
// Match Control Register (MCR) shifters
#define MR0I 0
#define MR0R 1
#define MR0S 2
#define MR1I 3
#define MR1R 4
#define MR1S 5
#define MR2I 6
#define MR2R 7
#define MR2S 8
#define MR3I 9
#define MR3R 10
#define MR3S 11
// Capture Control Register (CCR) shifters
#define CAP0RE 0
#define CAP0FE 1
#define CAP0I 2
#define CAP1RE 3
#define CAP1FE 4
#define CAP1I 5
#define CAP2RE 6
#define CAP2FE 7
#define CAP2I 8
#define CAP3RE 9
#define CAP3FE 10
#define CAP3I 11
// External Match Register (EMR) shifters
#define EM0 0
#define EM1 1
#define EM2 2
#define EM3 3
#define EMC0 4
#define EMC1 6
#define EMC2 8
#define EMC3 10
// EMR bit fields
#define DO_NOTHING_ON_MATCH 0x0
#define CLEAR_ON_MATCH 0x1
#define SET_ON_MATCH 0x2
#define TOGGLE_ON_MATCH 0x3
// Count Control Register (CTCR) shifters
#define CTMODE 0
#define CINSEL 2
#define ENCC 4
#define SELCC 5
// CTCR bit fields
#define TIMER_MODE 0x0
#define COUNTER_MODE_RISING 0x1
#define COUNTER_MODE_FALLING 0x2
#define COUNTER_MODE_BOTH 0x3
#define CLEAR_ON_CAP0_RISING 0x0
#define CLEAR_ON_CAP0_FALLING 0x1
#define CLEAR_ON_CAP1_RISING 0x2
#define CLEAR_ON_CAP1_FALLING 0x3
#define CLEAR_ON_CAP2_RISING 0x4
#define CLEAR_ON_CAP2_FALLING 0x5
#define CLEAR_ON_CAP3_RISING 0x6
#define CLEAR_ON_CAP3_FALLING 0x7
// PWM Control Register (PWMC) shifters
#define PWMEN0 0
#define PWMEN1 1
#define PWMEN2 2
#define PWMEN3 3
#endif // LPC8XX_CTIMER_H_

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/*
* dac.h
* Author: Arthur
*/
#ifndef LPC8XX_DAC_H_
#define LPC8XX_DAC_H_
// D/A Converter Register (VAL) shifters
#define DAC_VALUE 6
#define DAC_BIAS 16
// CTRL register shifters
#define DAC_INT_DMA_REQ 0
#define DAC_DBLBUF_ENA 1
#define DAC_CNT_ENA 2
#define DAC_DMA_ENA 3
#endif /* LPC8XX_DAC_H_ */

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#ifndef __FRO_H__
#define __FRO_H__
// FROOSCTRL register shifters
#define FRO_FREQ_SEL 0
#define FRO_TRIM 11
#define FRO_TEMP_TRIM 12
#define FRO_DIRECT 17
#define FRO_DEBUG_ENABLE 18
// FROOSCTRL register values
#define FRO_18MHZ 0
#define FRO_24MHZ 1
#define FRO_30MHZ 2
#define FRO_FREQSEL_MASK 3
#define FRO_DIVIDERS_OUT 0
#define FRO_OSCOUT 1
#endif // __FRO_H

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/****************************************************************************
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
****************************************************************************/
#ifndef __LPC8XX_GPIO_H
#define __LPC8XX_GPIO_H
#define INPUT 0
#define OUTPUT 1
#define PORT0 0
#define PORT1 1
#define Bit0 0
#define Bit1 1
#define Bit2 2
#define Bit3 3
#define Bit4 4
#define Bit5 5
#define Bit6 6
#define Bit7 7
#define Bit8 8
#define Bit9 9
#define Bit10 10
#define Bit11 11
#define Bit12 12
#define Bit13 13
#define Bit14 14
#define Bit15 15
#define Bit16 16
#define Bit17 17
#define Bit18 18
#define Bit19 19
#define Bit20 20
#define Bit21 21
#define Bit22 22
#define Bit23 23
#define Bit24 24
#define Bit25 25
#define Bit26 26
#define Bit27 27
#define Bit28 28
#define Bit29 29
#define Bit30 30
#define Bit31 31
void PININT_Handler ( uint32_t irq_num );
void PININT0_IRQHandler(void);
void PININT1_IRQHandler(void);
void PININT2_IRQHandler(void);
void PININT3_IRQHandler(void);
void PININT4_IRQHandler(void);
void PININT5_IRQHandler(void);
void PININT6_IRQHandler(void);
void PININT7_IRQHandler(void);
void GPIOInit( void );
uint32_t GPIOGetPinValue( uint32_t portNum, uint32_t bitPosi );
void GPIOSetBitValue( uint32_t portNum, uint32_t bitPosi, uint32_t bitVal );
void GPIOSetDir( uint32_t portNum, uint32_t bitPosi, uint32_t dir );
#endif /* end __LPC8XX_GPIO_H */
/*****************************************************************************
** End Of File
******************************************************************************/

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/**********************************************************************
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors<72>
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
#ifndef lpc8xx_I2C_H_
#define lpc8xx_I2C_H_
#include "LPC8xx.h"
#define RD_BIT 0x01
#define CFG_MSTENA (1 << 0)
#define CFG_SLVENA (1 << 1)
#define CFG_MONENA (1 << 2)
#define CFG_TIMEOUTENA (1 << 3)
#define CFG_MONCLKSTR (1 << 4)
#define CTL_MSTCONTINUE (1 << 0)
#define CTL_MSTSTART (1 << 1)
#define CTL_MSTSTOP (1 << 2)
#define CTL_SLVCONTINUE (1 << 0)
#define CTL_SLVNACK (1 << 1)
// Below matches the Niobe2 user manual
#define I2C_STAT_MSTSTATE (0x7<<1)
#define I2C_STAT_MSTST_IDLE (0x0<<1)
#define I2C_STAT_MSTST_RX (0x1<<1)
#define I2C_STAT_MSTST_TX (0x2<<1)
#define STAT_MSTPEND (1 << 0)
#define MASTER_STATE_MASK (0x7<<1)
#define STAT_MSTIDLE (0x0 << 1)
#define STAT_MSTRX (0x1 << 1)
#define STAT_MSTTX (0x2 << 1)
#define STAT_MSTNACKADDR (0x3 << 1)
#define STAT_MSTNACKTX (0x4 << 1)
#define STAT_MSTARBLOSS (1 << 4)
#define STAT_MSTSSERR (1 << 6)
#define STAT_SLVPEND (1 << 8)
#define SLAVE_STATE_MASK (0x3<<9)
#define STAT_SLVADDR (0x0 << 9)
#define STAT_SLVRX (0x1 << 9)
#define STAT_SLVTX (0x2 << 9)
#define STAT_SLVNOTSTR (1 << 11)
#define STAT_SLVSEL (1 << 14)
#define STAT_SLVDESEL (1 << 15)
#define STAT_MONOVERRUN (1 << 17)
#define STAT_MONACTIVE (1 << 18)
#define STAT_MONIDLE (1 << 19)
#define STAT_EVTIMEOUT (1 << 24)
#define STAT_SCLTIMEOUT (1 << 25)
void WaitI2CMasterState(LPC_I2C_TypeDef * ptr_LPC_I2C, uint32_t state);
void WaitI2CSlaveState(LPC_I2C_TypeDef * ptr_LPC_I2C, uint32_t state);
void I2CmasterWrite( uint8_t *WrBuf, uint8_t WrLen );
void I2CmasterWriteRead( uint8_t *WrBuf, uint8_t *RdBuf, uint8_t WrLen, uint8_t RdLen );
#endif /* lpc8xx_I2C_H_ */

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#ifndef __IAP_H__
#define __IAP_H__
#include <stdint.h> // standard types definitions
enum eIAP_COMMANDS
{
IAP_PREPARE = 50, // Prepare sector(s) for write operation
IAP_COPY_RAM2FLASH, // Copy RAM to Flash
IAP_ERASE, // Erase sector(s)
IAP_BLANK_CHECK, // Blank check sector(s)
IAP_READ_PART_ID, // Read chip part ID
IAP_READ_BOOT_VER, // Read chip boot code version
IAP_COMPARE, // Compare memory areas
IAP_REINVOKE_ISP, // Reinvoke ISP
IAP_READ_UID, // Read unique ID
IAP_ERASE_PAGE, // Erase page(s)
IAP_READ_MISR=70,
IAP_READ_MISR_EX=73,
};
struct sIAP
{
uint32_t cmd; // Command
uint32_t par[4]; // Parameters
uint32_t stat; // Status
uint32_t res[4]; // Result
};
#define REINVOKE_AUTO 0
#define REINVOKE_UART 1
// Pointer to ROM IAP entry functions
#define IAP_ENTRY_LOCATION 0x0F001FF1
// IAP Call
typedef void (*IAP_Entry) (uint32_t *cmd, uint32_t *stat);
#define IAP_Call ((IAP_Entry) IAP_ENTRY_LOCATION)
#endif // __IAP_H__

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#ifndef IOCON_H_
#define IOCON_H_
#define IOCON_MODE_MASK (0xFFFFFFe7)
#define IOCON_DACEN_MASK (0xFFFeFFFF)
#define MODE_INACTIVE (0<<3)
#define MODE_PULLDOWN (1<<3)
#define MODE_PULLUP (2<<3)
#define MODE_REPEATER (3<<3)
// DAC pin shifters
#define IOCON_MODE 3
#define IOCON_HYS 5
#define IOCON_INV 6
#define IOCON_RESERVED789 (0x1<<7)
#define IOCON_OD 10
#define IOCON_S_MODE 11
#define IOCON_CLK_DIV 13
#define IOCON_DAC_ENABLE 16
#endif // IOCON_H_

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/*
* @brief Common types used in LPC functions
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __LPC_TYPES_H_
#define __LPC_TYPES_H_
#include <stdint.h>
#include <stdbool.h>
/** @defgroup LPC_Types CHIP: LPC Common Types
* @ingroup CHIP_Common
* @{
*/
/** @defgroup LPC_Types_Public_Types LPC Public Types
* @{
*/
/**
* @brief Boolean Type definition
*/
typedef enum {FALSE = 0, TRUE = !FALSE} Bool;
/**
* @brief Boolean Type definition
*/
#if !defined(__cplusplus)
// typedef enum {false = 0, true = !false} bool;
#endif
/**
* @brief Flag Status and Interrupt Flag Status type definition
*/
typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState;
#define PARAM_SETSTATE(State) ((State == RESET) || (State == SET))
/**
* @brief Functional State Definition
*/
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
#define PARAM_FUNCTIONALSTATE(State) ((State == DISABLE) || (State == ENABLE))
/**
* @ Status type definition
*/
typedef enum {ERROR = 0, SUCCESS = !ERROR} Status;
/**
* Read/Write transfer type mode (Block or non-block)
*/
typedef enum {
NONE_BLOCKING = 0, /**< None Blocking type */
BLOCKING, /**< Blocking type */
} TRANSFER_BLOCK_T;
/** Pointer to Function returning Void (any number of parameters) */
typedef void (*PFV)();
/** Pointer to Function returning int32_t (any number of parameters) */
typedef int32_t (*PFI)();
/**
* @}
*/
/** @defgroup LPC_Types_Public_Macros LPC Public Macros
* @{
*/
/* _BIT(n) sets the bit at position "n"
* _BIT(n) is intended to be used in "OR" and "AND" expressions:
* e.g., "(_BIT(3) | _BIT(7))".
*/
#undef _BIT
/* Set bit macro */
#define _BIT(n) (1 << (n))
/* _SBF(f,v) sets the bit field starting at position "f" to value "v".
* _SBF(f,v) is intended to be used in "OR" and "AND" expressions:
* e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)"
*/
#undef _SBF
/* Set bit field macro */
#define _SBF(f, v) ((v) << (f))
/* _BITMASK constructs a symbol with 'field_width' least significant
* bits set.
* e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF
* The symbol is intended to be used to limit the bit field width
* thusly:
* <a_register> = (any_expression) & _BITMASK(x), where 0 < x <= 32.
* If "any_expression" results in a value that is larger than can be
* contained in 'x' bits, the bits above 'x - 1' are masked off. When
* used with the _SBF example above, the example would be written:
* a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16))
* This ensures that the value written to a_reg is no wider than
* 16 bits, and makes the code easier to read and understand.
*/
#undef _BITMASK
/* Bitmask creation macro */
#define _BITMASK(field_width) ( _BIT(field_width) - 1)
/* NULL pointer */
#ifndef NULL
#define NULL ((void *) 0)
#endif
/* Number of elements in an array */
#define NELEMENTS(array) (sizeof(array) / sizeof(array[0]))
/* Static data/function define */
#define STATIC static
/* External data/function define */
#define EXTERN extern
#if !defined(MAX)
#define MAX(a, b) (((a) > (b)) ? (a) : (b))
#endif
#if !defined(MIN)
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
#endif
/**
* @}
*/
/* Old Type Definition compatibility */
/** @addtogroup LPC_Types_Public_Types
* @{
*/
/** LPC type for character type */
typedef char CHAR;
/** LPC type for 8 bit unsigned value */
typedef uint8_t UNS_8;
/** LPC type for 8 bit signed value */
typedef int8_t INT_8;
/** LPC type for 16 bit unsigned value */
typedef uint16_t UNS_16;
/** LPC type for 16 bit signed value */
typedef int16_t INT_16;
/** LPC type for 32 bit unsigned value */
typedef uint32_t UNS_32;
/** LPC type for 32 bit signed value */
typedef int32_t INT_32;
/** LPC type for 64 bit signed value */
typedef int64_t INT_64;
/** LPC type for 64 bit unsigned value */
typedef uint64_t UNS_64;
#ifdef __CODE_RED
#define BOOL_32 bool
#define BOOL_16 bool
#define BOOL_8 bool
#else
/** 32 bit boolean type */
typedef bool BOOL_32;
/** 16 bit boolean type */
typedef bool BOOL_16;
/** 8 bit boolean type */
typedef bool BOOL_8;
#endif
#ifdef __CC_ARM
#define INLINE __inline
#else
#define INLINE inline
#endif
#ifdef __ICCARM__
#define ALIGNSTR(x) # x
#define ALIGN(x) _Pragma(ALIGNSTR(data_alignment = x))
#else /* __CC_ARM || __GNUC__ */
#define ALIGN(x) __attribute__ ((aligned(x)))
#endif
/**
* @}
*/
/**
* @}
*/
#endif /* __LPC_TYPES_H_ */

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/*
* lpc8xx_mrt.h
*
* Created on: Apr 11, 2016
* Author:
*/
#ifndef LPC8XX_MRT_H_
#define LPC8XX_MRT_H_
// INTVAL register values
#define NoForceLoad 0<<31
#define ForceLoad (uint32_t)1<<31
// INTVAL register bit field shifters
#define MRT_LOAD 31
// Control register bit field shifters
#define MRT_INTEN 0
#define MRT_MODE 1
// Control register values
#define MRT_Repeat 0
#define MRT_OneShot 1
#define MRT_OneShotBusStall 2
// Status register
#define MRT_INTFLAG 0
#define MRT_RUN 1
// Idle channel register
#define IDLE_CHAN 4
// IRQ_FLAG register
#define GFLAG0 0
#define GFLAG1 1
#define GFLAG2 2
#define GFLAG3 3
#endif /* LPC8XX_MRT_H_ */

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#ifndef __LPCPLU_H__
#define __LPCPLU_H__
#ifdef __cplusplus
extern "C" {
#endif
//#define CONFIG_PLU_nLUT_IN (5)
//#define CONFIG_PLU_nIN (6) /* Number of inputs */
//#define CONFIG_PLU_nLU (26) /* Number of LUTs */
//#define CONFIG_PLU_nFF (4) /* Number of FFs */
//#define CONFIG_PLU_nOU (8) /* Number of outputs */
#define LUT_INs 5
#define PLU_INs 6
#define PLU_LUTs 26
#define PLU_FFs 4
#define PLU_OUTs 8
#pragma anon_unions
typedef struct
{
struct { /* Input select register for LUT & Input... */
union {
__IO uint32_t INP[8]; /* Each LUT has maximum 5 inputs, the remaining are reserved. */
struct {
__IO uint32_t INP0;
__IO uint32_t INP1;
__IO uint32_t INP2;
__IO uint32_t INP3;
__IO uint32_t INP4;
uint32_t RESERVED[3];
};
} LUT_MUX[PLU_LUTs];
};
uint32_t RESERVED0[8*64-8*PLU_LUTs]; /* ...-0x7FC */
__IO uint32_t LUT_TRUTH[PLU_LUTs]; /* Truth-Table ("Look-up Table") programming */
uint32_t RESERVED1[64-PLU_LUTs]; /* ...-0x8FC */
__I uint32_t OUTPUTS; /* PLU Outputs Register (Read-only) */
uint32_t RESERVED2[3*64-1]; /* ...-0xBFC */
__IO uint32_t OUTPUT_MUX[PLU_OUTs]; /* Select register for PLU Ouptut */
} LPC_PLU_T;
/* PLU driver error code */
#define PLU_OK 0
#define PLU_INPUT_OUT_OF_RANGE 1
#define PLU_LUT_OUT_OF_RANGE 2
#define PLU_FF_OUT_OF_RANGE 3
#define PLU_OUTPUT_OUT_OF_RANGE 4
#define PLU_LUT_IN_DEFAULT 999
#define PLU_ROUTINE_FAILED 9999
#define PLU_STDL_OUT_OF_RANGE 0xDEAD
/* PLU masks, and micros if PLU tool is not used. */
#define LUT_OUT_MASK (1<<7)
#define FF_OUT_MASK (1<<6)
#define PLU_INPUT_MASK (0<<6)
#define LUT_OUT(x) (LUT_OUT_MASK | (x & 0x7F))
#define FF_OUT(x) (FF_OUT_MASK | (x & 0x3F))
#define PLU_INPUT(x) (PLU_INPUT_MASK | (x & 0x3F))
#define LUT_IN_OFFSET_INPUT 0
#define LUT_IN_OFFSET_LUT_OUT (PLU_INs)
#define LUT_IN_OFFSET_FF (PLU_INs+PLU_LUTs)
#define LUT_IN_PLU_INPUT(x) (LUT_IN_OFFSET_INPUT+x)
#define LUT_IN_LUT_OUT(x) (LUT_IN_OFFSET_LUT_OUT+x)
#define LUT_IN_FF(x) (LUT_IN_OFFSET_FF+x)
#define PLU_OUT_OFFSET_LUT_OUT 0
#define PLU_OUT_OFFSET_FF (PLU_LUTs)
#define PLU_OUT_LUT(x) (PLU_OUT_OFFSET_LUT_OUT+x)
#define PLU_OUT_FF(x) (PLU_OUT_OFFSET_FF+x)
extern uint32_t generate_plu_tt(uint32_t (* pnt_tt_function)(uint32_t, uint32_t, uint32_t, uint32_t, uint32_t), uint32_t * pnt_tt);
#define INMUX_IN(x) (x)
#define INMUX_LUT(x) (PLU_INs+x)
#define INMUX_FF(x) (PLU_INs+PLU_LUTs+x)
#define INMUXDEF(x) INMUX_LUT(x)
#define PLU_LUT_5IN_CUSTOM(lut,in0,in1,in2,in3,in4,tt) LPC_PLU0->LUT_MUX[lut].INP[0]=in0; \
LPC_PLU0->LUT_MUX[lut].INP[1]=in1; \
LPC_PLU0->LUT_MUX[lut].INP[2]=in2; \
LPC_PLU0->LUT_MUX[lut].INP[3]=in3; \
LPC_PLU0->LUT_MUX[lut].INP[4]=in4; \
LPC_PLU0->LUT_TRUTH[lut]=tt
#define PLU_LUT_4IN_CUSTOM(lut,in0,in1,in2,in3,tt) PLU_LUT_5IN_CUSTOM(lut,in0,in1,in2,in3,INMUXDEF(lut),tt)
#define PLU_LUT_3IN_CUSTOM(lut,in0,in1,in2,tt) PLU_LUT_5IN_CUSTOM(lut,in0,in1,in2,INMUXDEF(lut),INMUXDEF(lut),tt)
#define PLU_LUT_2IN_CUSTOM(lut,in0,in1,tt) PLU_LUT_5IN_CUSTOM(lut,in0,in1,INMUXDEF(lut),INMUXDEF(lut),INMUXDEF(lut),tt)
#define PLU_LUT_2IN_AND(lut,in0,in1) PLU_LUT_2IN_CUSTOM(lut,in0,in1,0x88888888)
#define PLU_LUT_3IN_AND(lut,in0,in1,in2) PLU_LUT_3IN_CUSTOM(lut,in0,in1,in2,0x80808080)
#define PLU_LUT_4IN_AND(lut,in0,in1,in2,in3) PLU_LUT_4IN_CUSTOM(lut,in0,in1,in2,in3,0x80008000)
#define PLU_LUT_5IN_AND(lut,in0,in1,in2,in3,in4) PLU_LUT_5IN_CUSTOM(lut,in0,in1,in2,in3,in4,0x80000000)
#define PLU_LUT_2IN_NAND(lut,in0,in1) PLU_LUT_2IN_CUSTOM(lut,in0,in1,0x77777777)
#define PLU_LUT_3IN_NAND(lut,in0,in1,in2) PLU_LUT_3IN_CUSTOM(lut,in0,in1,in2,0x7F7F7F7F)
#define PLU_LUT_4IN_NAND(lut,in0,in1,in2,in3) PLU_LUT_4IN_CUSTOM(lut,in0,in1,in2,in3,0x7FFF7FFF)
#define PLU_LUT_5IN_NAND(lut,in0,in1,in2,in3,in4) PLU_LUT_5IN_CUSTOM(lut,in0,in1,in2,in3,in4,0x7FFFFFFF)
#define PLU_LUT_2IN_OR(lut,in0,in1) PLU_LUT_2IN_CUSTOM(lut,in0,in1,0xEEEEEEEE)
#define PLU_LUT_3IN_OR(lut,in0,in1,in2) PLU_LUT_3IN_CUSTOM(lut,in0,in1,in2,0xFEFEFEFE)
#define PLU_LUT_4IN_OR(lut,in0,in1,in2,in3) PLU_LUT_4IN_CUSTOM(lut,in0,in1,in2,in3,0xFFFEFFFE)
#define PLU_LUT_5IN_OR(lut,in0,in1,in2,in3,in4) PLU_LUT_5IN_CUSTOM(lut,in0,in1,in2,in3,in4,0xFFFFFFFE)
#define PLU_LUT_2IN_NOR(lut,in0,in1) PLU_LUT_2IN_CUSTOM(lut,in0,in1,0x11111111)
#define PLU_LUT_3IN_NOR(lut,in0,in1,in2) PLU_LUT_3IN_CUSTOM(lut,in0,in1,in2,0x01010101)
#define PLU_LUT_4IN_NOR(lut,in0,in1,in2,in3) PLU_LUT_4IN_CUSTOM(lut,in0,in1,in2,in3,0x00010001)
#define PLU_LUT_5IN_NOR(lut,in0,in1,in2,in3,in4) PLU_LUT_5IN_CUSTOM(lut,in0,in1,in2,in3,in4,0x00000001)
#define PLU_LUT_2IN_XOR(lut,in0,in1) PLU_LUT_2IN_CUSTOM(lut,in0,in1,0x66666666)
#define PLU_LUT_3IN_XOR(lut,in0,in1,in2) PLU_LUT_3IN_CUSTOM(lut,in0,in1,in2,0x96969696)
#define PLU_LUT_4IN_XOR(lut,in0,in1,in2,in3) PLU_LUT_4IN_CUSTOM(lut,in0,in1,in2,in3,0x69966996)
#define PLU_LUT_5IN_XOR(lut,in0,in1,in2,in3,in4) PLU_LUT_5IN_CUSTOM(lut,in0,in1,in2,in3,in4,0x96696996)
#define PLU_LUT_2IN_XNOR(lut,in0,in1) PLU_LUT_2IN_CUSTOM(lut,in0,in1,0x99999999)
#define PLU_LUT_3IN_XNOR(lut,in0,in1,in2) PLU_LUT_3IN_CUSTOM(lut,in0,in1,in2,0x69696969)
#define PLU_LUT_4IN_XNOR(lut,in0,in1,in2,in3) PLU_LUT_4IN_CUSTOM(lut,in0,in1,in2,in3,0x96699669)
#define PLU_LUT_5IN_XNOR(lut,in0,in1,in2,in3,in4) PLU_LUT_5IN_CUSTOM(lut,in0,in1,in2,in3,in4,0x69969669)
#define PLU_LUT_2IN1SEL_MUX(lut,in0,in1,in2) PLU_LUT_3IN_CUSTOM(lut,in0,in1,in2,0xCACACACA)
#define PLU_LUT_BUFFER(lut,in0) PLU_LUT_2IN_CUSTOM(lut,in0,INMUXDEF(lut),0xAAAAAAAA)
#define PLU_LUT_INVERTER(lut,in0) PLU_LUT_2IN_CUSTOM(lut,in0,INMUXDEF(lut),0x55555555)
#define OUTMUX_LUT(x) (x)
#define OUTMUX_FF(x) (PLU_LUTs+x)
#define PLU_OUT(out,src) LPC_PLU0->OUTPUT_MUX[out]=src
#ifdef __cplusplus
}
#endif
#endif /* __LPCPLU_H__ */

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#ifndef LPC8XX_PMU_H_
#define LPC8XX_PMU_H_
// PCON register shifters
#define PM 0
#define NODPD 3
#define SLEEPFLAG 8
#define DPDFLAG 11
// WUSRCREG and WUENAREG
#define PIO_15_WU (1<<0)
#define PIO_9_WU (1<<1)
#define PIO_8_WU (1<<2)
#define PIO_17_WU (1<<3)
#define PIO_13_WU (1<<4)
#define PIO_5_WU (1<<5)
#define PIO_11_WU (1<<6)
#define PIO_10_WU (1<<7)
#endif // LPC8XX_PMU_H_

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/*
* rom_api_.h
*
* Created on:
* By Arthur:
*/
#ifndef __ROM_API_H_
#define __ROM_API_H_
// FRO API
typedef struct _PWRD {
const unsigned int reserved[2];
void (*set_fro_frequency)(unsigned frequency);
} PWRD_API_T;
// Integer divide API routines
typedef struct {
int quot; // Quotient
int rem; // Remainder
} IDIV_RETURN_T;
typedef struct {
unsigned quot; // Quotient
unsigned rem; // Reminder
} UIDIV_RETURN_T;
typedef struct {
int (*sidiv)(int numerator, int denominator); // Signed integer division
unsigned (*uidiv)(unsigned numerator, unsigned denominator); // Unsigned integer division
IDIV_RETURN_T (*sidivmod)(int numerator, int denominator); // Signed integer division with remainder
UIDIV_RETURN_T (*uidivmod)(unsigned numerator, unsigned denominator); // Unsigned integer division with remainder
} ROM_DIV_API_T;
// The master structure that defines the table of all ROM APIs on the device (a.k.a ROM Driver table)
typedef struct _ROM_API {
const unsigned int reserved3[3]; // Offsets 0, 4, 8
const PWRD_API_T *pPWRD; // Offset 0xC. Power APIs function table base address
const ROM_DIV_API_T *divApiBase; // Offset 0x10. Integer division routines function table base address
const unsigned int reserved7[7]; // Offsets 0x14 - 0x2C
} LPC_ROM_API_T;
#define ROM_DRIVER_BASE (0x0F001FF8UL)
// Define a pointer to the master table
#define LPC_ROM_API (*(LPC_ROM_API_T * *)ROM_DRIVER_BASE)
// Use like this:
// ROM_DIV_API_T const *pROMDiv = LPC_ROM_API->divApiBase; // Create and initialize a pointer to the DIVIDE functions table
// int32_t result; // Declare an int variable
// result = pROMDiv->sidiv(-99, 6); // Call the sidiv routine, result now contains -99/6 = -16
// ROM_DIV_API_T const *pPwr = LPC_ROM_API->pPWRD; // Create and initialize a pointer to the power API functions table
// pPwr->set_power((uint32_t *)&cmd_table, (uint32_t *)&result_table); // Call the set_power routine
// Alternate form
#define LPC_PWRD_API ((PWRD_API_T * ) ((*(LPC_ROM_API_T * *) (ROM_DRIVER_BASE))->pPWRD))
#define LPC_DIVD_API ((ROM_DIV_API_T *) ((*(LPC_ROM_API_T * *) (ROM_DRIVER_BASE))->divApiBase))
// Use like this:
// LPC_PWRD_API->set_power((uint32_t *)&cmd_table, (uint32_t *)&result_table); // Call the set_power routine
#endif // rom_api.h

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/**********************************************************************
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors<72>
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
#ifndef lpc8xx_SPI_H_
#define lpc8xx_SPI_H_
#include "LPC8xx.h"
#include "swm.h"
#define SPI_FLASH_CS1() (LPC_GPIO_PORT->SET[0] = 1<<P0_16) /* Use for LPC804 */
#define SPI_FLASH_CS0() (LPC_GPIO_PORT->CLR[0] = 1<<P0_16) /* Use for LPC804 */
#define DATA_WIDTH 8
#define DUMMY_BYTE 0x55
#define BUFFER_SIZE 64
#define LPC_SPI0BAUDRate 500000
#define SPI_CFG_ENABLE (1 << 0)
#define SPI_CFG_MASTER (1 << 2)
#define SPI_CFG_SLAVE (0 << 2)
#define SPI_CFG_LSBF (1 << 3)
#define SPI_CFG_CPHA (1 << 4)
#define SPI_CFG_CPOL (1 << 5)
#define SPI_CFG_MOSIDRV (1 << 6)
#define SPI_CFG_LOOPBACK (1 << 7)
#define SPI_CFG_SPOL (1<<8)
//#define SPI_CFG_SPOL(s) (1 << (8 + s))
#define SPI_DLY_PREDELAY(d) ((d) << 0)
#define SPI_DLY_POSTDELAY(d) ((d) << 4)
#define SPI_DLY_FRAMEDELAY(d) ((d) << 8)
#define SPI_DLY_INTERDELAY(d) ((d) << 12)
#define SPI_STAT_RXRDY (1 << 0)
#define SPI_STAT_TXRDY (1 << 1)
#define SPI_STAT_RXOVERRUN (1 << 2)
#define SPI_STAT_TXUNDERRUN (1 << 3)
#define SPI_STAT_SELNASSERT (1 << 4)
#define SPI_STAT_SELNDEASSERT (1 << 5)
#define SPI_STAT_CLKSTALL (1 << 6)
#define SPI_STAT_ET (1 << 7)
#define SPI_STAT_MSTIDLE (1<<8)
#define SPI_STAT_ERROR_MASK (SPI_STAT_RXOVERRUN|SPI_STAT_TXUNDERRUN|SPI_STAT_SELNASSERT|SPI_STAT_SELNDEASSERT|SPI_STAT_CLKSTALL)
#define SPI_RXRDYEN (1<<0)
#define SPI_TXRDYEN (1<<1)
#define SPI_RXOVEN (1<<2)
#define SPI_TXUREN (1<<3)
#define SPI_SSAEN (1<<4)
#define SPI_SSDEN (1<<5)
#define SPI_RXRDY (1<<0)
#define SPI_TXRDY (1<<1)
#define SPI_RXOV (1<<2)
#define SPI_TXUR (1<<3)
#define SPI_SSA (1<<4)
#define SPI_SSD (1<<5)
#define SPI_CTL_TXSSELN (1<<16)
#define SPI_CTL_EOT (1<<20)
#define SPI_CTL_EOF (1<<21)
#define SPI_CTL_RXIGNORE (1<<22)
#define SPI_CTL_LEN(b) (((b)-1)<<24)
#define SPI_TXDATCTL_SSELN(s) (s << 16)
#define SPI_TXDATCTL_EOT (1 << 20)
#define SPI_TXDATCTL_EOF (1 << 21)
#define SPI_TXDATCTL_RX_IGNORE (1 << 22)
#define SPI_TXDATCTL_FSIZE(s) ((s) << 24)
#define SPI_RXDAT_SOT (1 << 20)
void SPI0_IRQHandler(void);
void SPImasterWriteOnly( uint8_t *WrBuf, uint32_t WrLen );
void SPImasterWriteRead( uint8_t *WrBuf, uint8_t *RdBuf, uint32_t WrLen );
void SPImasterReadOnly( uint8_t *RdBuf, uint32_t RdLen );
#endif /* lpc8xx_SPI_H_ */

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/*
* lpc8xx_swm.h
*
* Created on: March 28, 2017
*
*/
#ifndef LPC8XX_SWM_H_
#define LPC8XX_SWM_H_
#include "LPC8xx.h"
// Port pin number equates
#define P0_0 0
#define P0_1 1
#define P0_2 2
#define P0_3 3
#define P0_4 4
#define P0_5 5
#define P0_6 6
#define P0_7 7
#define P0_8 8
#define P0_9 9
#define P0_10 10
#define P0_11 11
#define P0_12 12
#define P0_13 13
#define P0_14 14
#define P0_15 15
#define P0_16 16
#define P0_17 17
#define P0_18 18
#define P0_19 19
#define P0_20 20
#define P0_21 21
#define P0_22 22
#define P0_23 23
#define P0_24 24
#define P0_25 25
#define P0_26 26
#define P0_27 27
#define P0_28 28
#define P0_29 29
#define P0_30 30
#define P0_31 31
#define P1_0 32
#define P1_1 33
#define P1_2 34
#define P1_3 35
#define P1_4 36
#define P1_5 37
#define P1_6 38
#define P1_7 39
#define P1_8 40
#define P1_9 41
#define P1_10 42
#define P1_11 43
#define P1_12 44
#define P1_13 45
#define P1_14 46
#define P1_15 47
#define P1_16 48
#define P1_17 49
#define P1_18 50
#define P1_19 51
#define P1_20 52
#define P1_21 53
#define P1_22 54
#define P1_23 55
#define P1_24 56
#define P1_25 57
#define P1_26 58
#define P1_27 59
#define P1_28 60
#define P1_29 61
#define P1_30 62
#define P1_31 63
#define NO_PIN 0xFF
// Function name equates (for normal people)
#define U0_TXD 0
#define U0_RXD 1
#define U0_RTS 2
#define U0_CTS 3
#define U0_SCLK 4
#define U1_TXD 5
#define U1_RXD 6
#define U1_SCLK 7
#define SPI0_SCK 8
#define SPI0_MOSI 9
#define SPI0_MISO 10
#define SPI0_SSEL0 11
#define SPI0_SSEL1 12
#define T0_CAP0 13
#define T0_CAP1 14
#define T0_CAP2 15
#define T0_MAT0 16
#define T0_MAT1 17
#define T0_MAT2 18
#define T0_MAT3 19
#define I2C0_SDA 20
#define I2C0_SCL 21
#define COMP0_OUT 22
#define ACOMP 22
#define CLKOUT 23
#define GPIO_INT_BMAT 24
#define LVLSHFT_IN0 25
#define LVLSHFT_IN1 26
#define LVLSHFT_OUT0 27
#define LVLSHFT_OUT1 28
#define I2C1_SDA 29
#define I2C1_SCL 30
#define PLU_CLKIN 31
#define CAPT_X0 32
#define CAPT_X1 33
#define CAPT_X2 34
#define CAPT_X3 35
#define CAPT_X4 36
#define CAPT_YL 37
#define CAPT_YH 38
#define num_funcs 39
// Function name equates for the PINASSIGN_4PIN register
#define min_4pin_func 100
#define PLU_IN0 100
#define PLU_IN1 101
#define PLU_IN2 102
#define PLU_IN3 103
#define PLU_IN4 104
#define PLU_IN5 105
#define PLU_OUT0 106
#define PLU_OUT1 107
#define PLU_OUT2 108
#define PLU_OUT3 109
#define PLU_OUT4 110
#define PLU_OUT5 111
#define PLU_OUT6 112
#define PLU_OUT7 113
#define max_4pin_func 113
// PINENABLE0 register defines
#define ACMP_I1 (1<<0)
#define ACMP_I2 (1<<1)
#define ACMP_I3 (1<<2)
#define ACMP_I4 (1<<3)
#define SWCLK (1<<4)
#define SWDIO (1<<5)
#define RESETN (1<<6)
#define CLKIN (1<<7)
#define WKTCLKIN (1<<8)
#define VDDCMP (1<<9)
#define ADC_0 (1<<10)
#define ADC_1 (1<<11)
#define ADC_2 (1<<12)
#define ADC_3 (1<<13)
#define ADC_4 (1<<14)
#define ADC_5 (1<<15)
#define ADC_6 (1<<16)
#define ADC_7 (1<<17)
#define ADC_8 (1<<18)
#define ADC_9 (1<<19)
#define ADC_10 (1<<20)
#define ADC_11 (1<<21)
#define ACMP_I5 (1<<22)
#define DACOUT0 (1<<23)
/**
* @brief LPC8XX Switch Matrix PLU Movable pins (works for LPC804 with PLU)
*/
typedef enum CHIP_SWM_PLU_MOVABLE {
PLU_INPUT0_PIO0_0 = 0x00 << 0, /*!< PLU_INPUT0 - PIO0_0 */
PLU_INPUT0_PIO0_8 = 0x01 << 0, /*!< PLU_INPUT0 - PIO0_8 */
PLU_INPUT0_PIO0_17 = 0x02 << 0, /*!< PLU_INPUT0 - PIO0_17 */
PLU_INPUT0_NONE = 0x03 << 0, /*!< PLU_INPUT0 - NONE */
PLU_INPUT1_PIO0_1 = 0x00 << 2, /*!< PLU_INPUT1 - PIO0_1 */
PLU_INPUT1_PIO0_9 = 0x01 << 2, /*!< PLU_INPUT1 - PIO0_9 */
PLU_INPUT1_PIO0_18 = 0x02 << 2, /*!< PLU_INPUT1 - PIO0_18 */
PLU_INPUT1_NONE = 0x03 << 2, /*!< PLU_INPUT1 - NONE */
PLU_INPUT2_PIO0_2 = 0x00 << 4, /*!< PLU_INPUT2 - PIO0_2 */
PLU_INPUT2_PIO0_10 = 0x01 << 4, /*!< PLU_INPUT2 - PIO0_10 */
PLU_INPUT2_PIO0_19 = 0x02 << 4, /*!< PLU_INPUT2 - PIO0_19 */
PLU_INPUT2_NONE = 0x03 << 4, /*!< PLU_INPUT2 - NONE */
PLU_INPUT3_PIO0_3 = 0x00 << 6, /*!< PLU_INPUT3 - PIO0_3 */
PLU_INPUT3_PIO0_11 = 0x01 << 6, /*!< PLU_INPUT3 - PIO0_11 */
PLU_INPUT3_PIO0_20 = 0x02 << 6, /*!< PLU_INPUT3 - PIO0_20 */
PLU_INPUT3_NONE = 0x03 << 6, /*!< PLU_INPUT3 - NONE */
PLU_INPUT4_PIO0_4 = 0x00 << 8, /*!< PLU_INPUT4 - PIO0_4 */
PLU_INPUT4_PIO0_12 = 0x01 << 8, /*!< PLU_INPUT4 - PIO0_12 */
PLU_INPUT4_PIO0_21 = 0x02 << 8, /*!< PLU_INPUT4 - PIO0_21 */
PLU_INPUT4_NONE = 0x03 << 8, /*!< PLU_INPUT4 - NONE */
PLU_INPUT5_PIO0_5 = 0x00 << 10, /*!< PLU_INPUT5 - PIO0_5 */
PLU_INPUT5_PIO0_13 = 0x01 << 10, /*!< PLU_INPUT5 - PIO0_13 */
PLU_INPUT5_PIO0_22 = 0x02 << 10, /*!< PLU_INPUT5 - PIO0_22 */
PLU_INPUT5_NONE = 0x03 << 10, /*!< PLU_INPUT5 - NONE */
PLU_OUTPUT0_PIO0_7 = 0x00 << 12, /*!< PLU_OUTPUT0 - PIO0_7 */
PLU_OUTPUT0_PIO0_14 = 0x01 << 12, /*!< PLU_OUTPUT0 - PIO0_14 */
PLU_OUTPUT0_PIO0_23 = 0x02 << 12, /*!< PLU_OUTPUT0 - PIO0_23 */
PLU_OUTPUT0_NONE = 0x03 << 12, /*!< PLU_OUTPUT0 - NONE */
PLU_OUTPUT1_PIO0_8 = 0x00 << 14, /*!< PLU_OUTPUT1 - PIO0_8 */
PLU_OUTPUT1_PIO0_15 = 0x01 << 14, /*!< PLU_OUTPUT1 - PIO0_15 */
PLU_OUTPUT1_PIO0_24 = 0x02 << 14, /*!< PLU_OUTPUT1 - PIO0_24 */
PLU_OUTPUT1_NONE = 0x03 << 14, /*!< PLU_OUTPUT1 - NONE */
PLU_OUTPUT2_PIO0_9 = 0x00 << 16, /*!< PLU_OUTPUT2 - PIO0_9 */
PLU_OUTPUT2_PIO0_16 = 0x01 << 16, /*!< PLU_OUTPUT2 - PIO0_16 */
PLU_OUTPUT2_PIO0_25 = 0x02 << 16, /*!< PLU_OUTPUT2 - PIO0_25 */
PLU_OUTPUT2_NONE = 0x03 << 16, /*!< PLU_OUTPUT2 - NONE */
PLU_OUTPUT3_PIO0_10 = 0x00 << 18, /*!< PLU_OUTPUT3 - PIO0_10 */
PLU_OUTPUT3_PIO0_17 = 0x01 << 18, /*!< PLU_OUTPUT3 - PIO0_17 */
PLU_OUTPUT3_PIO0_26 = 0x02 << 18, /*!< PLU_OUTPUT3 - PIO0_26 */
PLU_OUTPUT3_NONE = 0x03 << 18, /*!< PLU_OUTPUT3 - NONE */
PLU_OUTPUT4_PIO0_11 = 0x00 << 20, /*!< PLU_OUTPUT4 - PIO0_11 */
PLU_OUTPUT4_PIO0_18 = 0x01 << 20, /*!< PLU_OUTPUT4 - PIO0_18 */
PLU_OUTPUT4_PIO0_27 = 0x02 << 20, /*!< PLU_OUTPUT4 - PIO0_27 */
PLU_OUTPUT4_NONE = 0x03 << 20, /*!< PLU_OUTPUT4 - NONE */
PLU_OUTPUT5_PIO0_12 = 0x00 << 22, /*!< PLU_OUTPUT5 - PIO0_12 */
PLU_OUTPUT5_PIO0_19 = 0x01 << 22, /*!< PLU_OUTPUT5 - PIO0_19 */
PLU_OUTPUT5_PIO0_28 = 0x02 << 22, /*!< PLU_OUTPUT5 - PIO0_28 */
PLU_OUTPUT5_NONE = 0x03 << 22, /*!< PLU_OUTPUT5 - NONE */
PLU_OUTPUT6_PIO0_13 = 0x00 << 24, /*!< PLU_OUTPUT6 - PIO0_13 */
PLU_OUTPUT6_PIO0_20 = 0x01 << 24, /*!< PLU_OUTPUT6 - PIO0_20 */
PLU_OUTPUT6_PIO0_29 = 0x02 << 24, /*!< PLU_OUTPUT6 - PIO0_29 */
PLU_OUTPUT6_NONE = 0x03 << 24, /*!< PLU_OUTPUT6 - NONE */
PLU_OUTPUT7_PIO0_14 = 0x00 << 26, /*!< PLU_OUTPUT7 - PIO0_14 */
PLU_OUTPUT7_PIO0_21 = 0x01 << 26, /*!< PLU_OUTPUT7 - PIO0_21 */
PLU_OUTPUT7_PIO0_30 = 0x02 << 26, /*!< PLU_OUTPUT7 - PIO0_30 */
PLU_OUTPUT7_NONE = 0x03 << 26, /*!< PLU_OUTPUT7 - NONE */
} CHIP_SWM_PLU_MOVABLE_T;
// Function prototypes
void ConfigSWM(uint32_t func, uint32_t port_pin);
void EnableFixedPinFunc(uint32_t func);
void DisableFixedPinFunc(uint32_t func);
#endif /* LPC8XX_SWM_H_ */

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/*
* lpc8xx_syscon.h
*
* Created on:
* Author:
*/
#include <stdint.h>
#ifndef LPC8XX_SYSCON_H_
#define LPC8XX_SYSCON_H_
// SYSAHBCLKCTRL0 register bits
#define ROM (1<<1)
#define RAM0_1 (1<<2)
#define FLASH (1<<4)
#define I2C0 (1<<5)
#define GPIO (1<<6)
#define GPIO0 (1<<6)
#define SWM (1<<7)
#define WKT (1<<9)
#define MRT (1<<10)
#define SPI0 (1<<11)
#define CRC (1<<13)
#define UART0 (1<<14)
#define UART1 (1<<15)
#define WWDT (1<<17)
#define IOCON (1<<18)
#define ACMP (1<<19)
#define GPIO1 (1<<20)
#define I2C1 (1<<21)
#define ADC (1<<24)
#define CTIMER0 (1<<25)
#define DAC0 (1<<27)
#define GPIO_INT (1<<28)
// SYSAHBCLKCTRL1 register bits
#define CAPT (1<<0)
#define PLU (1<<5)
// SYSAHBCLKCTRL[] register bits (alternate form)
typedef enum {
CLK_ROM = 1 ,
CLK_RAM0_1 ,
CLK_FLASH = 4 ,
CLK_I2C0 ,
CLK_GPIO0 ,
CLK_SWM ,
CLK_WKT = 9 ,
CLK_MRT ,
CLK_SPI0 ,
CLK_CRC = 13 ,
CLK_UART0 ,
CLK_UART1 ,
CLK_WWDT = 17 ,
CLK_IOCON ,
CLK_ACMP ,
CLK_I2C1 = 21 ,
CLK_ADC = 24 ,
CLK_CTIMER0 ,
CLK_DAC0 = 27 ,
CLK_GPIO_INT ,
CLK_CAPT = 32,
CLK_PLU = 37
} CHIP_SYSCON_CLOCK_CTRL_T;
// PRESETCTRL0 register bits
#define FLASH_RST_N ~(1<<4)
#define I2C0_RST_N ~(1<<5)
#define GPIO0_RST_N ~(1<<6)
#define SWM_RST_N ~(1<<7)
#define WKT_RST_N ~(1<<9)
#define MRT_RST_N ~(1<<10)
#define SPI0_RST_N ~(1<<11)
#define CRC_RST_N ~(1<<13)
#define UART0_RST_N ~(1<<14)
#define UART1_RST_N ~(1<<15)
#define IOCON_RST_N ~(1<<18)
#define ACMP_RST_N ~(1<<19)
#define GPIO1_RST_N ~(1<<20)
#define I2C1_RST_N ~(1<<21)
#define ADC_RST_N ~(1<<24)
#define CTIMER0_RST_N ~(1<<25)
#define DAC0_RST_N ~(1<<27)
#define GPIOINT_RST_N ~(1<<28)
// PRESETCTRL1 register bits
#define CAPT_RST_N ~(1<<0)
#define FRG0_RST_N ~(1<<3)
#define PLU_RST_N ~(1<<5)
// PRESETCTRL[] register bits (alternate form)
typedef enum {
RESET_FLASH = 4 ,
RESET_I2C0 ,
RESET_GPIO0 ,
RESET_SWM ,
RESET_WKT = 9 ,
RESET_MRT ,
RESET_SPI0 ,
RESET_CRC = 13 ,
RESET_UART0 ,
RESET_UART1 ,
RESET_IOCON = 18,
RESET_ACMP ,
RESET_I2C1 = 21 ,
RESET_ADC = 24 ,
RESET_CTIMER0 ,
RESET_DAC0 = 27 ,
RESET_GPIO_INT ,
RESET_CAPT = 32 ,
RESET_FRG0 = 35 ,
RESET_PLU = 37
} CHIP_SYSCON_PERIPH_RESET_T;
// STARTERP0 register bits
#define PINT0_WAKEUP (1<<0)
#define PINT1_WAKEUP (1<<1)
#define PINT2_WAKEUP (1<<2)
#define PINT3_WAKEUP (1<<3)
#define PINT4_WAKEUP (1<<4)
#define PINT5_WAKEUP (1<<5)
#define PINT6_WAKEUP (1<<6)
#define PINT7_WAKEUP (1<<7)
// STARTERP1 register bits
#define SPI0_INT_WAKEUP (1<<0)
#define USART0_INT_WAKEUP (1<<3)
#define USART1_INT_WAKEUP (1<<4)
#define I2C1_INT_WAKEUP (1<<7)
#define I2C0_INT_WAKEUP (1<<8)
#define WWDT_INT_WAKE (1<<12)
#define BOD_INT_WAKE (1<<13)
#define WKT_INT_WAKEUP (1<<15)
// PDAWAKECFG and PDRUNCFG register bits
#define FROOUT_PD (1<<0)
#define FRO_PD (1<<1)
#define FLASH_PD (1<<2)
#define BOD_PD (1<<3) // Also for PDSLEEPCFG
#define ADC_PD (1<<4)
#define LPOSC_PD (1<<6) // Also for PDSLEEPCFG
#define DAC0_PD (1<<13)
#define ACMP_PD (1<<15)
// LPOSCCLKEN register bit field shifters
#define WWDT_CLK_EN 0
#define WKT_CLK_EN 1
// BODCTRL register bit field shifters
#define BODRSTLEV 0
#define BODINTVAL 2
#define BODRSTENA 4
// Below entries are for clock select mux functions
typedef enum {
FCLKSEL_FRO_CLK = 0,
FCLKSEL_MAIN_CLK = 1,
FCLKSEL_FRG0CLK = 2,
FCLKSEL_FRO_DIV_CLK = 4,
FCLKSEL_OFF = 7
} SYSCON_FCLKSEL_CLK_T;
typedef enum {
FCLK_TO_UART0 = 0,
FCLK_TO_UART1 = 1,
FCLK_TO_I2C0 = 5,
FCLK_TO_I2C1 = 6,
FCLK_TO_SPI0 = 9
} SYSCON_FCLKSEL_T;
typedef enum {
FRGCLKSEL_FRO_CLK = 0,
FRGCLKSEL_MAIN_CLK = 1,
FRGCLKSEL_OFF = 3
} SYSCON_FRGCLKSEL_T;
typedef enum {
CLKOUTSEL_FRO_CLK = 0,
CLKOUTSEL_MAIN_CLK = 1,
CLKOUTSEL_EXTERNAL_CLK = 3,
CLKOUTSEL_LPOSC_CLK = 4,
CLKOUTSEL_OFF = 7
} SYSCON_CLKOUTSEL_T;
typedef enum {
ADCCLKSEL_FRO_CLK = 0,
ADCCLKSEL_EXTERNAL_CLK = 1,
ADCCLKSEL_OFF = 3
} SYSCON_ADCCLKSEL_T;
void Enable_Periph_Clock(uint32_t slot);
void Disable_Periph_Clock(uint32_t slot);
void Do_Periph_Reset(uint32_t slot);
//void Config_Syspll(unsigned int which_clock, unsigned int pll_ctrl_value);
void Config_Fclksel_Mux(uint32_t to_which_periph, uint32_t which_clock);
#endif /* LPC8XX_SYSCON_H_ */

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/**************************************************************************//**
* @file system_LPC8xx.h
* @brief CMSIS Device System Header File for
* NXP LPC845
* @version V1.10
* @date 19. August 2014
*
* @note
* Copyright (C) 2014 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __SYSTEM_LPC8xx_H
#define __SYSTEM_LPC8xx_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t main_clk;
extern uint32_t wdt_osc_clk;
extern uint32_t sys_pll0_clk;
extern uint32_t fro_clk;
extern uint32_t fro_div_clk;
extern uint32_t system_ahb_clk;
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_LPC8xx_H */

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/**********************************************************************
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors<72>
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
**********************************************************************/
#ifndef __lpc8xx_UART_H
#define __lpc8xx_UART_H
#define UART_EN (0x01<<0)
#define DATA_LENG_7 (0x00<<2)
#define DATA_LENG_8 (0x01<<2)
#define DATA_LENG_9 (0x02<<2)
#define PARITY_NONE (0x00<<4)
#define PARITY_NC (0x01<<4)
#define PARITY_EVEN (0x02<<4)
#define PARITY_ODD (0x03<<4)
#define STOP_BIT_1 (0x00<<6)
#define STOP_BIT_2 (0x01<<6)
#define MODE_32K (0x01<<7)
#define EXT_CTS_EN (0x01<<9)
#define INT_CTS_EN (0x01<<10)
#define SYNC_EN (0x01<<11)
#define CLK_POL (0x01<<12)
#define SYNC_MS (0x01<<14)
#define LOOPBACK (0x01<<15)
// UART Control register
#define TXBRK_EN (0x01<<1)
#define ADDR_DET (0x01<<2)
#define TXDIS (0x01<<6)
#define CC (0x01<<8)
#define CCCLR (0x01<<9)
// UART status register
#define RXRDY (0x01<<0)
#define RXIDLE (0x01<<1)
#define TXRDY (0x01<<2)
#define TXIDLE (0x01<<3)
#define CTS (0x01<<4)
#define CTS_DELTA (0x01<<5)
#define TXINT_DIS (0x01<<6)
#define OVRN_ERR (0x01<<8)
#define RXBRK (0x01<<10)
#define DELTA_RXBRK (0x01<<11)
#define START_DETECT (0x01<<12)
#define FRM_ERR (0x01<<13)
#define PAR_ERR (0x01<<14)
#define RXNOISE (0x01<<15)
#endif /* __lpc8xx_UART_H */

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/*
* lpc8xx_wkt.h
*
* Created on: Apr 11, 2016
* Author:
*/
#ifndef LPC8XX_WKT_H_
#define LPC8XX_WKT_H_
// Control register shifters
#define WKT_CLKSEL 0
#define WKT_ALARMFLAG 1
#define WKT_CLEARCTR 2
// Control register fields
#define DIVIDED_IRC 0
#define LOW_POWER_OSC 1
#endif /* LPC8XX_WKT_H_ */

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/*
* lpc8xx_wwdt.h
*
* Created on: Apr 12, 2016
* Author:
*/
#ifndef LPC8XX_WWDT_H_
#define LPC8XX_WWDT_H_
// MOD register
#define WDEN 0
#define WDRESET 1
#define WDTOF 2
#define WDINT 3
#define WDPROTECT 4
#define LOCK 5
#endif /* LPC8XX_WWDT_H_ */

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There seems to be no LPCOpen library for the LPC804:
https://www.nxp.com/design/microcontrollers-developer-resources/lpcopen-libraries-and-examples/lpcopen-software-development-platform-lpc8xx:LPCOPEN-SOFTWARE-FOR-LPC8XX
Source: LPC804-EX-CODE-MCUXPRESSO.zip from nxp.com
available from here:
https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc800-cortex-m0-plus-/low-cost-microcontrollers-mcus-based-on-arm-cortex-m0-plus-core:LPC80X?tab=Design_Tools_Tab#t749
"LPC804 Example Code Bundle MCUXpresso"
Toplevel include should be "LPC8xx.h".
The name "LPC8xx.h" might be misleading: This file is specific to the LPC804, but
I decided not to change the name, but keep the orginal file name from the above zip
folder. In fact plan is not to modify any of the files in lpc_chip_804 so that they can
be overwritten at any time with the original files (maybe chip_setup.h is an exception).
For some reason the variable "SystemCoreClock" is renamed to "main_clk".
While working in the code, I saw, that there are some issues in "lpc_chip_804":
- Removed includes of "utilities.h" because the funcionality is not called
- added inclusion of "swm.h" from "spi.h", because "spi.h" makes use of
some definitions from "swm.h"
- Removed "Config_Syspll" declaration from "syscon.h" because it is removed in the src.
- Alligned "unsigned int" with "uint32_t" declarations in syscon.h and .c
- Change the inclusion of "lpc8xx.h" to "LPC8xx.h" in i2c.h
As a conclusion, I had to change the following files compared to the original zip content:
i2c.h syscon.h syscon.c i2c.c spi.c spi.h plu.c

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/****************************************************************************
*
****************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors'
* relevant copyright in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
****************************************************************************/
#include "LPC8xx.h" /* LPC8xx Peripheral Registers */
#include "gpio.h"
#include "syscon.h"
/*****************************************************************************
** Function name: GPIOInit
**
** Description: Enable clock, then reset the GPIO module.
** See syscon.h for register bit definitions.
**
** Parameters: None
**
** Returned value: None
*****************************************************************************/
void GPIOInit( void )
{
/* Enable AHB clock to the GPIO domain. */
LPC_SYSCON->SYSAHBCLKCTRL[0] |= (GPIO0 | GPIO1);
/* Peripheral reset to the GPIO module. '0' asserts, '1' deasserts reset. */
LPC_SYSCON->PRESETCTRL[0] &= (GPIO0_RST_N & GPIO1_RST_N);
LPC_SYSCON->PRESETCTRL[0] |= ~(GPIO0_RST_N & GPIO1_RST_N);
return;
}
/*****************************************************************************
** Function name: GPIOGetPinValue
**
** Description: Read Current state of port pin, PIN register value
**
** parameters: port number, bit position
** Returned value: The value, obviously
**
*****************************************************************************/
uint32_t GPIOGetPinValue( uint32_t portNum, uint32_t bitPosi )
{
return (LPC_GPIO_PORT->PIN[portNum] & (1<<bitPosi));
}
/*****************************************************************************
** Function name: GPIOSetBitValue
**
** Descriptions: Set/clear a bit in a specific position
**
** parameters: port num, bit position, bit value
**
** Returned value: None
**
*****************************************************************************/
void GPIOSetBitValue( uint32_t portNum, uint32_t bitPosi, uint32_t bitVal )
{
if ( bitVal )
{
LPC_GPIO_PORT->SET[portNum] = 1<<bitPosi;
}
else
{
LPC_GPIO_PORT->CLR[portNum] = 1<<bitPosi;
}
return;
}
/*****************************************************************************
** Function name: GPIOSetDir
**
** Descriptions: Set the direction in GPIO port
**
** parameters: portNum, bit position, direction (1 out, 0 input)
**
** Returned value: None
**
*****************************************************************************/
void GPIOSetDir( uint32_t portNum, uint32_t bitPosi, uint32_t dir )
{
if( dir )
{
LPC_GPIO_PORT->DIRSET[portNum] = 1<<bitPosi;
}
else
{
LPC_GPIO_PORT->DIRCLR[portNum] = 1<<bitPosi;
}
return;
}
/******************************************************************************
** End Of File
******************************************************************************/

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/*
* i2c.c
*
* Created on: Apr 5, 2016
*
*/
#include "LPC8xx.h"
//#include "utilities.h"
#include "i2c.h"
/*****************************************************************************
** Function name: I2CmasterWrite
**
** Description: Write a block of data to the I2C slave using polling.
**
** parameters: pointer to the write buffer starting with the I2C slave address.
** Length of the write data block
** Returned value: None
**
*****************************************************************************/
void I2CmasterWrite( uint8_t *WrBuf, uint8_t WrLen )
{
uint32_t i;
WaitI2CMasterState(LPC_I2C0, I2C_STAT_MSTST_IDLE); // Wait for the master state to be idle
LPC_I2C0->MSTDAT = *WrBuf | 0; // Address with 0 for RWn bit (WRITE)
LPC_I2C0->MSTCTL = CTL_MSTSTART; // Start the transaction by setting the MSTSTART bit to 1 in the Master control register.
WaitI2CMasterState(LPC_I2C0, I2C_STAT_MSTST_TX); // Wait for the address to be ACK'd
for ( i = 0; i < WrLen; i++ ) {
LPC_I2C0->MSTDAT = *(WrBuf + i + 1); // Send the data to the slave
LPC_I2C0->MSTCTL = CTL_MSTCONTINUE; // Continue the transaction
WaitI2CMasterState(LPC_I2C0, I2C_STAT_MSTST_TX); // Wait for the data to be ACK'd
}
LPC_I2C0->MSTCTL = CTL_MSTSTOP; // Send a stop to end the transaction
return;
}
/*****************************************************************************
** Function name: I2CmasterWriteRead
**
** Description: Write the command to the i2C slave and followed by using repeated start
to read a block of data from the I2C slave.
**
** parameters: pointer to the write buffer
pointer to the read buffer
length of the write data buffer
length of the read data buffer
e.g. WR_Addr, Write data (0~WrLen-1), RD_addr, Read data (0~RdLen-1)
** Returned value: None
**
*****************************************************************************/
void I2CmasterWriteRead( uint8_t *WrBuf, uint8_t *RdBuf, uint8_t WrLen, uint8_t RdLen )
{
uint32_t i, i2c_addr;
i2c_addr = *WrBuf;
WaitI2CMasterState(LPC_I2C0, I2C_STAT_MSTST_IDLE); // Wait for the master state to be idle
LPC_I2C0->MSTDAT = i2c_addr; // Address with 0 for RWn bit (WRITE)
LPC_I2C0->MSTCTL = CTL_MSTSTART; // Start the transaction by setting the MSTSTART bit to 1 in the Master control register.
WaitI2CMasterState(LPC_I2C0, I2C_STAT_MSTST_TX); // Wait for the address to be ACK'd
for ( i = 0; i < WrLen; i++ ) {
LPC_I2C0->MSTDAT = *(WrBuf + i + 1); // Send the data to the slave
LPC_I2C0->MSTCTL = CTL_MSTCONTINUE; // Continue the transaction
WaitI2CMasterState(LPC_I2C0, I2C_STAT_MSTST_TX); // Wait for the data to be ACK'd
}
LPC_I2C0->MSTDAT = i2c_addr | RD_BIT; // Address with 1 for RWn bit (READ)
LPC_I2C0->MSTCTL = CTL_MSTSTART; // Start the transaction by setting the MSTSTART bit to 1 in the Master control register.
for ( i = 0; i < RdLen; i++ ) {
WaitI2CMasterState(LPC_I2C0, I2C_STAT_MSTST_RX); // Wait for the data to be ACK'd
*(RdBuf + i) = LPC_I2C0->MSTDAT; // Send the data to the slave
LPC_I2C0->MSTCTL = CTL_MSTCONTINUE; // Continue the transaction
}
LPC_I2C0->MSTCTL = CTL_MSTSTOP; // Send a stop to end the transaction
return;
}
/*****************************************************************************
** Function name: WaitI2CMasterState
**
** Description: Waits for I2C master pending, then compares the master
** state to the state parameter. If compare fails, enter
** a while(1) loop. If compare passes, return.
**
** parameters:
** ptr_LPC_I2C: A pointer to an I2C instance
** state: One of the 3-bit Master function state codes of the I2C
** Returned value: None
**
*****************************************************************************/
void WaitI2CMasterState(LPC_I2C_TypeDef * ptr_LPC_I2C, uint32_t state) {
while(!(ptr_LPC_I2C->STAT & STAT_MSTPEND)); // Wait for MSTPENDING bit set in STAT register
if((ptr_LPC_I2C->STAT & MASTER_STATE_MASK) != state) { // If master state mismatch ...
while(1); // die here and debug the problem
}
return; // If no mismatch, return
}
/*****************************************************************************
** Function name: WaitI2CSlaveState
**
** Description: Waits for I2C slave pending, then compares the slave
** state to the state parameter. If compare fails, enter
** a while(1) loop. If compare passes, return.
**
** parameters:
** ptr_LPC_I2C: A pointer to an I2C instance
** state: One of the 2-bit slave function state codes of the I2C
** Returned value: None
**
*****************************************************************************/
void WaitI2CSlaveState(LPC_I2C_TypeDef * ptr_LPC_I2C, uint32_t state) {
while(!(ptr_LPC_I2C->STAT & STAT_SLVPEND)); // Wait for SLVPENDING bit in STAT register
if((ptr_LPC_I2C->STAT & SLAVE_STATE_MASK) != state) // If state mismatches
while(1); // Die here, and debug the problem
return; // Otherwise, return
}

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/*
* @brief LPC80X Analog comparator driver
*
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "LPC8xx.h"
#include "core_cm0plus.h"
#include "syscon.h"
#include "plu.h"
#include <stdarg.h>
typedef struct {
uint16_t id;
uint16_t inputs;
uint32_t tt;
} _stdl_id_ins_tt;
uint32_t generate_plu_tt(uint32_t (* pnt_tt_function)(uint32_t, uint32_t, uint32_t, uint32_t, uint32_t), uint32_t * pnt_tt)
{
uint32_t result;
uint32_t fin, fin4, fin3, fin2, fin1, fin0;
uint32_t tt_loc;
result = PLU_ROUTINE_FAILED;
tt_loc = 0;
for (fin = 0; fin != 32; fin++)
{
fin0 = (fin >> 0) & 1;
fin1 = (fin >> 1) & 1;
fin2 = (fin >> 2) & 1;
fin3 = (fin >> 3) & 1;
fin4 = (fin >> 4) & 1;
tt_loc |= (*pnt_tt_function)(fin0, fin1, fin2, fin3, fin4)<<fin;
}
*pnt_tt = tt_loc;
result = PLU_OK;
return result;
}

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/*
* spi.c
*
* Created on: Apr 5, 2016
*
*/
#include "LPC8xx.h"
//#include "utilities.h"
#include "spi.h"
uint32_t SPI_RXCount, SPI_TXCount;
void SPI0_IRQHandler(void)
{
uint32_t active = LPC_SPI0->STAT & LPC_SPI0->INTENSET;
if(active & SPI_STAT_RXRDY) {
SPI_RXCount++;
LPC_SPI0->INTENCLR = SPI_STAT_RXRDY;
}
if(active & SPI_STAT_TXRDY) {
SPI_TXCount++;
LPC_SPI0->INTENCLR = SPI_STAT_TXRDY;
}
return;
}
/*****************************************************************************
** Function name: SPImasterWriteOnly
**
** Description: Write a block of data to the SPI slave using polling.
** In this example, data width is limited to 8 bits only.
**
** parameters: pointer to the write buffer.
** Length of the write data block
** Returned value: None
**
*****************************************************************************/
void SPImasterWriteOnly( uint8_t *WrBuf, uint32_t WrLen )
{
uint32_t i = 0;
volatile uint32_t temp;
LPC_SPI0->TXCTL &= ~(SPI_CTL_EOT); // Start a new transfer, clear the EOT bit
SPI_FLASH_CS0(); /* Drive SPI CS low. */
if ( WrLen == 1 ) {
while ( (LPC_SPI0->STAT & SPI_STAT_TXRDY) == 0 );
LPC_SPI0->TXDATCTL = SPI_CTL_LEN(DATA_WIDTH) | SPI_CTL_EOT | *WrBuf;
}
else {
while ( i < WrLen ) {
/* Move only if TXRDY is ready */
while ( (LPC_SPI0->STAT & SPI_STAT_TXRDY) == 0 );
if ( i == 0 ) {
LPC_SPI0->TXDATCTL = SPI_CTL_LEN(DATA_WIDTH) | SPI_TXDATCTL_RX_IGNORE | *WrBuf++;
}
else if ( i == WrLen-1 ) {
LPC_SPI0->TXDATCTL = SPI_CTL_LEN(DATA_WIDTH) | SPI_CTL_EOT | *WrBuf++;
}
else {
LPC_SPI0->TXDAT = *WrBuf++;
}
i++;
}
}
while ( (LPC_SPI0->STAT & SPI_STAT_RXRDY) == 0 ); /* For last frame to be sent, wait until RX on MISO arrives before raising CS. */
temp = LPC_SPI0->RXDAT;
SPI_FLASH_CS1(); /* Drive SPI CS high */
return;
}
/*****************************************************************************
** Function name: SPImasterWriteRead
**
** Description: Write data on the SPI MOSI line while reading data from MISO.
** In this example, data width is limited to 8 bits only.
**
** parameters: pointer to the write buffer
pointer to the read buffer
length of the write/read data buffer
** Returned value: None
**
*****************************************************************************/
void SPImasterWriteRead( uint8_t *WrBuf, uint8_t *RdBuf, uint32_t WrLen )
{
uint32_t i = 0;
LPC_SPI0->TXCTL &= ~(SPI_CTL_EOT); // Start a new transfer, clear the EOT bit
SPI_FLASH_CS0(); /* Drive SPI CS low. */
if ( WrLen == 1 ) {
while ( (LPC_SPI0->STAT & SPI_STAT_TXRDY) == 0 );
LPC_SPI0->TXDATCTL = SPI_CTL_LEN(DATA_WIDTH) | SPI_CTL_EOT | *WrBuf;
while ( (LPC_SPI0->STAT & SPI_STAT_RXRDY) == 0 );
*RdBuf = LPC_SPI0->RXDAT;
}
else {
while ( i < WrLen ) {
/* Move only if TXRDY is ready */
while ( (LPC_SPI0->STAT & SPI_STAT_TXRDY) == 0 );
if ( i == 0 ) {
LPC_SPI0->TXDATCTL = SPI_CTL_LEN(DATA_WIDTH) | *WrBuf++;
}
else if ( i == WrLen-1 ) {
LPC_SPI0->TXDATCTL = SPI_CTL_LEN(DATA_WIDTH) | SPI_CTL_EOT | *WrBuf++;
}
else {
LPC_SPI0->TXDAT = *WrBuf++;
}
while ( (LPC_SPI0->STAT & SPI_STAT_RXRDY) == 0 );
*RdBuf++ = LPC_SPI0->RXDAT;
i++;
}
}
SPI_FLASH_CS1(); /* Drive SPI CS high */
return;
}
/*****************************************************************************
** Function name: SPImasterReadOnly
**
** Description: Read a block of data to the SPI slave using polling. It's almost
** the same as SPImasterWriteRead() except that SPI master writes
** dummy data the MOSI.
** In this example, data width is limited to 8 bits only.
**
** parameters: pointer to the read buffer.
** Length of the write data block
** Returned value: None
**
*****************************************************************************/
void SPImasterReadOnly( uint8_t *RdBuf, uint32_t RdLen )
{
uint32_t i = 0;
LPC_SPI0->TXCTL &= ~(SPI_CTL_EOT); // Start a new transfer, clear the EOT bit
SPI_FLASH_CS0(); /* Drive SPI CS low. */
if ( RdLen == 1 ) {
while ( (LPC_SPI0->STAT & SPI_STAT_TXRDY) == 0 );
LPC_SPI0->TXDATCTL = SPI_CTL_LEN(DATA_WIDTH) | SPI_CTL_EOT | DUMMY_BYTE;
while ( (LPC_SPI0->STAT & SPI_STAT_RXRDY) == 0 );
*RdBuf = LPC_SPI0->RXDAT;
}
else {
while ( i < RdLen ) {
/* Move only if TXRDY is ready */
while ( (LPC_SPI0->STAT & SPI_STAT_TXRDY) == 0 );
if ( i == 0 ) {
LPC_SPI0->TXDATCTL = SPI_CTL_LEN(DATA_WIDTH) | DUMMY_BYTE;
}
else if ( i == RdLen-1 ) {
LPC_SPI0->TXDATCTL = SPI_CTL_LEN(DATA_WIDTH) | SPI_CTL_EOT | DUMMY_BYTE;
}
else {
LPC_SPI0->TXDAT = DUMMY_BYTE;
}
while ( (LPC_SPI0->STAT & SPI_STAT_RXRDY) == 0 );
*RdBuf++ = LPC_SPI0->RXDAT;
i++;
}
}
SPI_FLASH_CS1(); /* Drive SPI CS high */
return;
}

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#include "swm.h"
#include "LPC8xx.h"
/*****************************************************************************
** Function name: ConfigSWM
** Description: Attaches a pin (designated by its GPIO port and bit numbers)
** to a function.
** parameters: func: Any function name that is movable.
** port_pin: Any pin which has a GPIO port number and bit number.
** Returned value: None
*****************************************************************************/
void ConfigSWM(uint32_t func, uint32_t port_pin) {
uint32_t temp, i;
uint32_t pinassign = 0;
uint32_t shifter = 0;
for (i=0; i<num_funcs; i++) {
if (func != i)
continue;
else {
pinassign = i/4;
shifter = (i%4)*8;
break;
}
}
temp = LPC_SWM->PINASSIGN[pinassign];
temp &= ~(0xFF<<(shifter));
temp |= (port_pin << shifter);
LPC_SWM->PINASSIGN[pinassign] = temp;
return;
}
/*****************************************************************************
** Function name: EnableFixedPinFunc
** Description: Enables a fixed-pin function in PINENABLE0 or PINENABLE1.
** parameters: func: Any function name that is a fixed-pin function.
** Returned value: None
*****************************************************************************/
void EnableFixedPinFunc(uint32_t func) {
if (func <= 0x80000000) {
LPC_SWM->PINENABLE0 &= ~(func);
}
else {
LPC_SWM->PINENABLE1 &= ~(func);
}
}
/*****************************************************************************
** Function name: DisableFixedPinFunc
** Description: Disables a fixed-pin function in PINENABLE0 or PINENABLE1.
** parameters: func: Any function name that is a fixed-pin function.
** Returned value: None
*****************************************************************************/
void DisableFixedPinFunc(uint32_t func) {
if (func <= 0x80000000) {
LPC_SWM->PINENABLE0 |= (func);
}
else {
LPC_SWM->PINENABLE1 |= (func);
}
}

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//
// syscon.c
//
#include "syscon.h"
#include "LPC8xx.h"
// Function: Enable_Periph_Clock
// Use like this: Enable_Periph_Clock(CLK_SPI0);
//
void Enable_Periph_Clock(uint32_t slot) {
if (slot < 32) {
LPC_SYSCON->SYSAHBCLKCTRL[0] |= 1<<slot;
}
else if (slot < 64) {
LPC_SYSCON->SYSAHBCLKCTRL[1] |= 1<<(slot-32);
}
}
// Function: Disable_Periph_Clock
// Use like this: Disable_Periph_Clock(CLK_SPI0);
//
void Disable_Periph_Clock(uint32_t slot) {
if (slot < 32) {
LPC_SYSCON->SYSAHBCLKCTRL[0] &= ~(1<<slot);
}
else if (slot < 64) {
LPC_SYSCON->SYSAHBCLKCTRL[1] &= ~(1<<(slot-32));
}
}
// Function: Do_Periph_Reset
// Use like this: Do_Periph_Reset(RESET_SPI0);
//
void Do_Periph_Reset(uint32_t slot) {
if (slot < 32) {
LPC_SYSCON->PRESETCTRL[0] &= ~(1<<slot);
LPC_SYSCON->PRESETCTRL[0] |= (1<<slot);
}
else if (slot < 64) {
LPC_SYSCON->PRESETCTRL[1] &= ~(1<<(slot-32));
LPC_SYSCON->PRESETCTRL[1] |= (1<<(slot-32));
}
}
// Function: Config_Syspll
// Use like this: Config_Syspll(SYSPLL_CLKSEL_EXTERNAL_CLK, 0x42);
//
//void Config_Syspll(unsigned int which_clock, unsigned int pll_ctrl_value) {
// LPC_SYSCON->SYSPLLCLKSEL = which_clock; // Select the input to the system PLL (sys_pll0_clk_src_i)
// LPC_SYSCON->SYSPLLCLKUEN = 0; // Toggle update register
// LPC_SYSCON->SYSPLLCLKUEN = 1;
// while (!(LPC_SYSCON->SYSPLLCLKUEN & 1)) __NOP(); // Wait until updated
// LPC_SYSCON->SYSPLLCTRL = pll_ctrl_value; // Update the SYSPLLCTRL register
// LPC_SYSCON->PDRUNCFG &= ~(SYSPLL_PD); // Power up system PLL
// while (!(LPC_SYSCON->SYSPLLSTAT & 1)) __NOP(); // Wait until PLL locked
//}
// Function: Config_Fclksel_Mux
// Use like this: Config_Fclksel_Mux(FCLK_TO_UART0, FCLKSEL_MAIN_CLK);
//
void Config_Fclksel_Mux(uint32_t to_which_periph, uint32_t which_clock) {
LPC_SYSCON->FCLKSEL[to_which_periph] = which_clock;
}

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/**************************************************************************//**
* @file system.c
* @brief CMSIS Device System Source File for
* NXP LPC80xm Device Series
* @version V1.0
* @date 01. April 2017
*
******************************************************************************/
//----------------------------------------------------------------------------
// Important!
// Please configure the desired initial clock setup for your project in:
// $proj_name/inc/chip_setup.h
//----------------------------------------------------------------------------
#include <stdint.h>
#include "LPC8xx.h"
#include "swm.h"
#include "syscon.h"
#include "iocon.h"
#include "fro.h"
#include "rom_api.h"
#include "chip_setup.h"
//----------------------------------------------------------------------------
// Validate the the user's selctions
//----------------------------------------------------------------------------
#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
#define CHECK_RSVD(val, mask) (val & mask)
#if (CHECK_RANGE((FRO_FREQ_VAL), 0, 2))
#error "FRO_FREQ_VAL: Value out of range."
#endif
#if (CHECK_RSVD((MAINCLKSEL_VAL), ~0x00000003))
#error "MAINCLKSEL: Invalid values of reserved bits!"
#endif
#if (CHECK_RANGE((SYSAHBCLKDIV_VAL), 0, 255))
#error "SYSAHBCLKDIV: Value out of range!"
#endif
#if (CHECK_RANGE(CLKIN_CLK_VAL, 1000000, 25000000))
#error "CLKIN frequency is out of bounds"
#endif
//----------------------------------------------------------------------------
// Calculate internal clock node frequency initial values
//----------------------------------------------------------------------------
#define __LPOSC_CLK (1000000)
// determine output of the FRO_CLKDIV subsystem
#if FRO_FREQ_VAL == 0
#define __FRO_OSCOUT (18000000)
#elif FRO_FREQ_VAL == 2
#define __FRO_OSCOUT (30000000)
#else
#define __FRO_OSCOUT (24000000)
#endif
#define __FRO_DIVIDERS_OUT (__FRO_OSCOUT / 2)
#define __FRO_CLK __FRO_DIVIDERS_OUT
#define __FRO_DIV_CLK (__FRO_CLK / 2)
// determine external_clk
#define __SYS_OSC_CLK (0)
#define __CLKIN_CLK (CLKIN_CLK_VAL)
#define __EXTERNAL_CLK __CLKIN_CLK
// determine main_clk
#if MAINCLKSEL_VAL == 0
#define __MAIN_CLK __FRO_CLK
#elif MAINCLKSEL_VAL == 1
#define __MAIN_CLK __EXTERNAL_CLK
#elif MAINCLKSEL_VAL == 2
#define __MAIN_CLK __LPOSC_CLK
#else
#define __MAIN_CLK __FRO_DIV_CLK
#endif
// determine system_ahb_clk
#define __SYSTEM_AHB_CLK (__MAIN_CLK / SYSAHBCLKDIV_VAL)
//----------------------------------------------------------------------------
// Function name: SystemInit
// Sets up the initial chip clocking based on MACROs defined in chip_setup.h.
//----------------------------------------------------------------------------
void SystemInit (void) {
uint32_t i;
for (i = 1; i < 1; i++) __NOP(); // To avoid a warning if variable i is unused
// Enable clocks to IOCON and SWM upon entry, disable them upon exit
LPC_SYSCON->SYSAHBCLKCTRL[0] |= (SWM | IOCON);
// Step 0. Configure the FRO subsystem (choose the source for clocks fro and fro_div)
#if (FRO_FREQ_VAL == 0)
//temp |= (FRO_18MHZ << FRO_FREQ_SEL);
LPC_PWRD_API->set_fro_frequency(18000);
#elif (FRO_FREQ_VAL == 2)
//temp |= (FRO_30MHZ << FRO_FREQ_SEL);
LPC_PWRD_API->set_fro_frequency(30000);
#else
//temp |= (FRO_24MHZ << FRO_FREQ_SEL);
LPC_PWRD_API->set_fro_frequency(24000);
#endif
//temp = LPC_SYSCON->FROOSCCTRL; // Get the current register contents
//temp &= ~(FRO_FREQSEL_MASK); // Preserve all but the bits of interest [1:0]
///PC_SYSCON->FROOSCCTRL = temp; // Update the actual register
//LPC_SYSCON->FRODIRECTCLKUEN = 0; // Toggle the update register for the output mux
//LPC_SYSCON->FRODIRECTCLKUEN = 1;
//while (!(LPC_SYSCON->FRODIRECTCLKUEN & 1)) __NOP(); // Wait for update to take effect
// Configure clk_in, if needed for main_clk or other (e.g. clock out, ADC clk.)
#if ((MAINCLKSEL_VAL == 1) || (EXT_CLOCK_FORCE_ENABLE == 1))
LPC_IOCON->PIO0_1 &= (IOCON_MODE_MASK | MODE_INACTIVE); // Disable pull-up and pull-down
LPC_SWM->PINENABLE0 &= ~(CLKIN); // Enable CLKIN func.
#endif
// Step 2. Power up the LP OSC if it's needed for main_clk
#if (MAINCLKSEL_VAL == 2)
LPC_SYSCON->PDRUNCFG &= ~(LPOSC_PD); // Power up the LP OSC
for (i = 0; i < 200; i++) __NOP(); // Wait for osc to stabilize
#endif
// Step 4. Choose source for main_clk
LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_VAL; // Update the actual register
LPC_SYSCON->MAINCLKUEN = 0; // Toggle update register
LPC_SYSCON->MAINCLKUEN = 1;
while (!(LPC_SYSCON->MAINCLKUEN & 1)) __NOP(); // Wait until updated
// Step 6. Configure the main_clock divider
LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_VAL; // Update the actual register
LPC_SYSCON->SYSAHBCLKCTRL[0] &= ~(SWM | IOCON); // Turn off peripheral clocks before leaving
} // end of SystemInit
//----------------------------------------------------------------------------
// Global clock variable declarations and initial value assignments
//----------------------------------------------------------------------------
uint32_t main_clk = __MAIN_CLK;
uint32_t lposc_clk = __LPOSC_CLK;
uint32_t fro_clk = __FRO_CLK;
uint32_t fro_div_clk = __FRO_DIV_CLK;
uint32_t system_ahb_clk = __SYSTEM_AHB_CLK;
//----------------------------------------------------------------------------
// Function name: SystemCoreClockUpdate
// Determines the actual system_ahb_clk (core clock), main_clock,
// fro_clk, and fro_div_clk frequencies
// based on the current state of the device, and updates the associated
// global clock variables.
//----------------------------------------------------------------------------
void SystemCoreClockUpdate (void)
{
uint32_t external_clk;
uint32_t fro_oscout, fro_clock;
uint32_t temp;
// Set the fro_clk and fro_div_clk variables according to current register settings
temp = LPC_SYSCON->FROOSCCTRL;
switch (temp & FRO_FREQSEL_MASK) {
case 0: fro_oscout = 18000000; break;
case 1: fro_oscout = 24000000; break;
default:fro_oscout = 30000000; break;
}
fro_clock = 0;
if ((LPC_SYSCON->PDRUNCFG & (FROOUT_PD | FRO_PD)) == 0x0) {
fro_clock = fro_oscout;
}
fro_clk = fro_clock / 2;
fro_div_clk = fro_clk / 2;
// Set the external_clk variable according to current register values
//if (LPC_SYSCON->EXTCLKSEL == 0)
// external_clk = __SYS_OSC_CLK;
//else
external_clk = __CLKIN_CLK;
// Set the lposc_clk variable
if (!(LPC_SYSCON->PDRUNCFG & LPOSC_PD)) {
lposc_clk = __LPOSC_CLK;
}
else {
lposc_clk = 0;
}
// Set the main_clk variable according to current register values
switch (LPC_SYSCON->MAINCLKSEL & 0x3) {
case 0: main_clk = fro_clk; break;
case 1: main_clk = external_clk; break;
case 2: main_clk = lposc_clk; break;
case 3: main_clk = fro_div_clk; break;
}
// Set the system_ahb_clk (a.k.a SystemCoreClock) variable according to current register values
system_ahb_clk = main_clk / LPC_SYSCON->SYSAHBCLKDIV;
} // end of SystemCoreClockUpdate