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7
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Web:
http://www.nxp.com/products/software-and-tools/hardware-development-tools/lpcxpresso-boards/lpcopen-software-development-platform-lpc11xx:LPCOPEN-SOFTWARE-FOR-LPC11XX
Source:
http://cache.nxp.com/files/microcontrollers/software/LPCWare/lpcopen_v2_03_lpcxpresso_nxp_lpcxpresso_11u37h.zip

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basic-setup/components/u8g2/sys/arm/plain/lpc_chip_11uxx_lib/inc/adc_11xx.h Normal file
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/*
* @brief LPC11xx A/D conversion driver (except LPC1125)
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __ADC_11XX_H_
#define __ADC_11XX_H_
#if !defined(CHIP_LPC1125)
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup ADC_11XX CHIP: LPC11xx A/D conversion driver
* @ingroup CHIP_11XX_Drivers
* This ADC driver is for LPC11xx variants except for LPC1125.
* @{
*/
#define ADC_MAX_SAMPLE_RATE 400000
/**
* @brief 10 or 12-bit ADC register block structure
*/
typedef struct { /*!< ADCn Structure */
__IO uint32_t CR; /*!< A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. */
__I uint32_t GDR; /*!< A/D Global Data Register. Contains the result of the most recent A/D conversion. */
__I uint32_t RESERVED0;
__IO uint32_t INTEN; /*!< A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
__I uint32_t DR[8]; /*!< A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n. */
__I uint32_t STAT; /*!< A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
} LPC_ADC_T;
/**
* @brief ADC register support bitfields and mask
*/
#define ADC_DR_RESULT(n) ((((n) >> 6) & 0x3FF)) /*!< Mask for getting the 10 bits ADC data read value */
#define ADC_CR_BITACC(n) ((((n) & 0x7) << 17)) /*!< Number of ADC accuracy bits */
#define ADC_DR_DONE(n) (((n) >> 31)) /*!< Mask for reading the ADC done status */
#define ADC_DR_OVERRUN(n) ((((n) >> 30) & (1UL))) /*!< Mask for reading the ADC overrun status */
#define ADC_CR_CH_SEL(n) ((1UL << (n))) /*!< Selects which of the AD0.0:7 pins is (are) to be sampled and converted */
#define ADC_CR_CLKDIV(n) ((((n) & 0xFF) << 8)) /*!< The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D */
#define ADC_CR_BURST ((1UL << 16)) /*!< Repeated conversions A/D enable bit */
#define ADC_CR_PDN ((1UL << 21)) /*!< ADC convert is operational */
#define ADC_CR_START_MASK ((7UL << 24)) /*!< ADC start mask bits */
#define ADC_CR_START_MODE_SEL(SEL) ((SEL << 24)) /*!< Select Start Mode */
#define ADC_CR_START_NOW ((1UL << 24)) /*!< Start conversion now */
#define ADC_CR_START_CTOUT15 ((2UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
#define ADC_CR_START_CTOUT8 ((3UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
#define ADC_CR_START_ADCTRIG0 ((4UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
#define ADC_CR_START_ADCTRIG1 ((5UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
#define ADC_CR_START_MCOA2 ((6UL << 24)) /*!< Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
#define ADC_CR_EDGE ((1UL << 27)) /*!< Start conversion on a falling edge on the selected CAP/MAT signal */
#define ADC_SAMPLE_RATE_CONFIG_MASK (ADC_CR_CLKDIV(0xFF) | ADC_CR_BITACC(0x07))
/**
* @brief ADC status register used for IP drivers
*/
typedef enum IP_ADC_STATUS {
ADC_DR_DONE_STAT, /*!< ADC data register staus */
ADC_DR_OVERRUN_STAT,/*!< ADC data overrun staus */
ADC_DR_ADINT_STAT /*!< ADC interrupt status */
} ADC_STATUS_T;
/** The channels on one ADC peripheral*/
typedef enum CHIP_ADC_CHANNEL {
ADC_CH0 = 0, /**< ADC channel 0 */
ADC_CH1, /**< ADC channel 1 */
ADC_CH2, /**< ADC channel 2 */
ADC_CH3, /**< ADC channel 3 */
ADC_CH4, /**< ADC channel 4 */
ADC_CH5, /**< ADC channel 5 */
ADC_CH6, /**< ADC channel 6 */
ADC_CH7, /**< ADC channel 7 */
} ADC_CHANNEL_T;
/** The number of bits of accuracy of the result in the LS bits of ADDR*/
typedef enum CHIP_ADC_RESOLUTION {
ADC_10BITS = 0, /**< ADC 10 bits */
ADC_9BITS, /**< ADC 9 bits */
ADC_8BITS, /**< ADC 8 bits */
ADC_7BITS, /**< ADC 7 bits */
ADC_6BITS, /**< ADC 6 bits */
ADC_5BITS, /**< ADC 5 bits */
ADC_4BITS, /**< ADC 4 bits */
ADC_3BITS, /**< ADC 3 bits */
} ADC_RESOLUTION_T;
/** Edge configuration, which controls rising or falling edge on the selected signal for the start of a conversion */
typedef enum CHIP_ADC_EDGE_CFG {
ADC_TRIGGERMODE_RISING = 0, /**< Trigger event: rising edge */
ADC_TRIGGERMODE_FALLING, /**< Trigger event: falling edge */
} ADC_EDGE_CFG_T;
/** Start mode, which controls the start of an A/D conversion when the BURST bit is 0. */
typedef enum CHIP_ADC_START_MODE {
ADC_NO_START = 0,
ADC_START_NOW, /*!< Start conversion now */
ADC_START_ON_CTOUT15, /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_15 */
ADC_START_ON_CTOUT8, /*!< Start conversion when the edge selected by bit 27 occurs on CTOUT_8 */
ADC_START_ON_ADCTRIG0, /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG0 */
ADC_START_ON_ADCTRIG1, /*!< Start conversion when the edge selected by bit 27 occurs on ADCTRIG1 */
ADC_START_ON_MCOA2 /*!< Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2 */
} ADC_START_MODE_T;
/** Clock setup structure for ADC controller passed to the initialize function */
typedef struct {
uint32_t adcRate; /*!< ADC rate */
uint8_t bitsAccuracy; /*!< ADC bit accuracy */
bool burstMode; /*!< ADC Burt Mode */
} ADC_CLOCK_SETUP_T;
/**
* @brief Initialize the ADC peripheral and the ADC setup structure to default value
* @param pADC : The base of ADC peripheral on the chip
* @param ADCSetup : ADC setup structure to be set
* @return Nothing
* @note Default setting for ADC is 400kHz - 10bits
*/
void Chip_ADC_Init(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup);
/**
* @brief Shutdown ADC
* @param pADC : The base of ADC peripheral on the chip
* @return Nothing
*/
void Chip_ADC_DeInit(LPC_ADC_T *pADC);
/**
* @brief Read the ADC value from a channel
* @param pADC : The base of ADC peripheral on the chip
* @param channel : ADC channel to read
* @param data : Pointer to where to put data
* @return SUCCESS or ERROR if no conversion is ready
*/
Status Chip_ADC_ReadValue(LPC_ADC_T *pADC, uint8_t channel, uint16_t *data);
/**
* @brief Read the ADC value and convert it to 8bits value
* @param pADC : The base of ADC peripheral on the chip
* @param channel: selected channel
* @param data : Storage for data
* @return Status : ERROR or SUCCESS
*/
Status Chip_ADC_ReadByte(LPC_ADC_T *pADC, ADC_CHANNEL_T channel, uint8_t *data);
/**
* @brief Read the ADC channel status
* @param pADC : The base of ADC peripheral on the chip
* @param channel : ADC channel to read
* @param StatusType : Status type of ADC_DR_*
* @return SET or RESET
*/
FlagStatus Chip_ADC_ReadStatus(LPC_ADC_T *pADC, uint8_t channel, uint32_t StatusType);
/**
* @brief Enable/Disable interrupt for ADC channel
* @param pADC : The base of ADC peripheral on the chip
* @param channel : ADC channel to read
* @param NewState : New state, ENABLE or DISABLE
* @return SET or RESET
*/
void Chip_ADC_Int_SetChannelCmd(LPC_ADC_T *pADC, uint8_t channel, FunctionalState NewState);
/**
* @brief Enable/Disable global interrupt for ADC channel
* @param pADC : The base of ADC peripheral on the chip
* @param NewState : New state, ENABLE or DISABLE
* @return Nothing
*/
STATIC INLINE void Chip_ADC_Int_SetGlobalCmd(LPC_ADC_T *pADC, FunctionalState NewState)
{
Chip_ADC_Int_SetChannelCmd(pADC, 8, NewState);
}
/**
* @brief Select the mode starting the AD conversion
* @param pADC : The base of ADC peripheral on the chip
* @param mode : Stating mode, should be :
* - ADC_NO_START : Must be set for Burst mode
* - ADC_START_NOW : Start conversion now
* - ADC_START_ON_CTOUT15 : Start conversion when the edge selected by bit 27 occurs on CTOUT_15
* - ADC_START_ON_CTOUT8 : Start conversion when the edge selected by bit 27 occurs on CTOUT_8
* - ADC_START_ON_ADCTRIG0 : Start conversion when the edge selected by bit 27 occurs on ADCTRIG0
* - ADC_START_ON_ADCTRIG1 : Start conversion when the edge selected by bit 27 occurs on ADCTRIG1
* - ADC_START_ON_MCOA2 : Start conversion when the edge selected by bit 27 occurs on Motocon PWM output MCOA2
* @param EdgeOption : Stating Edge Condition, should be :
* - ADC_TRIGGERMODE_RISING : Trigger event on rising edge
* - ADC_TRIGGERMODE_FALLING : Trigger event on falling edge
* @return Nothing
*/
void Chip_ADC_SetStartMode(LPC_ADC_T *pADC, ADC_START_MODE_T mode, ADC_EDGE_CFG_T EdgeOption);
/**
* @brief Set the ADC Sample rate
* @param pADC : The base of ADC peripheral on the chip
* @param ADCSetup : ADC setup structure to be modified
* @param rate : Sample rate, should be set so the clock for A/D converter is less than or equal to 4.5MHz.
* @return Nothing
*/
void Chip_ADC_SetSampleRate(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup, uint32_t rate);
/**
* @brief Set the ADC accuracy bits
* @param pADC : The base of ADC peripheral on the chip
* @param ADCSetup : ADC setup structure to be modified
* @param resolution : The resolution, should be ADC_10BITS -> ADC_3BITS
* @return Nothing
*/
void Chip_ADC_SetResolution(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup, ADC_RESOLUTION_T resolution);
/**
* @brief Enable or disable the ADC channel on ADC peripheral
* @param pADC : The base of ADC peripheral on the chip
* @param channel : Channel to be enable or disable
* @param NewState : New state, should be:
* - ENABLE
* - DISABLE
* @return Nothing
*/
void Chip_ADC_EnableChannel(LPC_ADC_T *pADC, ADC_CHANNEL_T channel, FunctionalState NewState);
/**
* @brief Enable burst mode
* @param pADC : The base of ADC peripheral on the chip
* @param NewState : New state, should be:
* - ENABLE
* - DISABLE
* @return Nothing
*/
void Chip_ADC_SetBurstCmd(LPC_ADC_T *pADC, FunctionalState NewState);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* !defined(CHIP_LPC1125) */
#endif /* __ADC_11XX_H_ */

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/*
* @brief LPC11xx basic chip inclusion file
*
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __CHIP_H_
#define __CHIP_H_
#include "lpc_types.h"
#include "sys_config.h"
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifndef CORE_M0
#error CORE_M0 is not defined for the LPC11xx architecture
#error CORE_M0 should be defined as part of your compiler define list
#endif
#if !defined(ENABLE_UNTESTED_CODE)
#if defined(CHIP_LPC110X)
#warning The LCP110X code has not been tested with a platform. This code should \
build without errors but may not work correctly for the device. To disable this \
#warning message, define ENABLE_UNTESTED_CODE.
#endif
#if defined(CHIP_LPC11XXLV)
#warning The LPC11XXLV code has not been tested with a platform. This code should \
build without errors but may not work correctly for the device. To disable this \
#warning message, define ENABLE_UNTESTED_CODE.
#endif
#if defined(CHIP_LPC11AXX)
#warning The LPC11AXX code has not been tested with a platform. This code should \
build without errors but may not work correctly for the device. To disable this \
#warning message, define ENABLE_UNTESTED_CODE.
#endif
#if defined(CHIP_LPC11EXX)
#warning The LPC11EXX code has not been tested with a platform. This code should \
build without errors but may not work correctly for the device. To disable this \
warning message, define ENABLE_UNTESTED_CODE.
#endif
#endif
#if !defined(CHIP_LPC110X) && !defined(CHIP_LPC11XXLV) && !defined(CHIP_LPC11AXX) && \
!defined(CHIP_LPC11CXX) && !defined(CHIP_LPC11EXX) && !defined(CHIP_LPC11UXX) && \
!defined(CHIP_LPC1125)
#error CHIP_LPC110x/CHIP_LPC11XXLV/CHIP_LPC11AXX/CHIP_LPC11CXX/CHIP_LPC11EXX/CHIP_LPC11UXX/CHIP_LPC1125 is not defined!
#endif
/* Peripheral mapping per device
Peripheral Device(s)
---------------------------- -------------------------------------------------------------------------------------------------------------
I2C(40000000) CHIP_LPC11XXLV/ CHIP_LPC11CXX/ CHIP_LPC11UXX/ CHIP_LPC11EXX/ CHIP_LPC11AXX CHIP_LPC1125
WDT(40004000) CHIP_LPC110x/ CHIP_LPC11XXLV/ CHIP_LPC11CXX/ CHIP_LPC11UXX/ CHIP_LPC11EXX/ CHIP_LPC11AXX CHIP_LPC1125
UART0(40008000) CHIP_LPC110x/ CHIP_LPC11XXLV/ CHIP_LPC11CXX CHIP_LPC1125
UART1(40020000) CHIP_LPC1125
UART2(40024000) CHIP_LPC1125
USART/SMARTCARD(40008000) CHIP_LPC11UXX/ CHIP_LPC11EXX/ CHIP_LPC11AXX
TIMER0_16(4000C000) CHIP_LPC110x/ CHIP_LPC11XXLV/ CHIP_LPC11CXX/ CHIP_LPC11UXX/ CHIP_LPC11EXX/ CHIP_LPC11AXX CHIP_LPC1125
TIMER1_16(40010000) CHIP_LPC110x/ CHIP_LPC11XXLV/ CHIP_LPC11CXX/ CHIP_LPC11UXX/ CHIP_LPC11EXX/ CHIP_LPC11AXX CHIP_LPC1125
TIMER0_32(40014000) CHIP_LPC110x/ CHIP_LPC11XXLV/ CHIP_LPC11CXX/ CHIP_LPC11UXX/ CHIP_LPC11EXX/ CHIP_LPC11AXX CHIP_LPC1125
TIMER1_32(40018000) CHIP_LPC110x/ CHIP_LPC11XXLV/ CHIP_LPC11CXX/ CHIP_LPC11UXX/ CHIP_LPC11EXX/ CHIP_LPC11AXX CHIP_LPC1125
ADC(4001C000) CHIP_LPC110x/ CHIP_LPC11XXLV/ CHIP_LPC11CXX/ CHIP_LPC11UXX/ CHIP_LPC11EXX/ CHIP_LPC11AXX CHIP_LPC1125
DAC(40024000) CHIP_LPC11AXX
ACMP(40028000) CHIP_LPC11AXX
PMU(40038000) CHIP_LPC110x/ CHIP_LPC11CXX/ CHIP_LPC11UXX/ CHIP_LPC11EXX CHIP_LPC1125
FLASH_CTRL(4003C000) CHIP_LPC110x/ CHIP_LPC11XXLV/ CHIP_LPC11CXX/ CHIP_LPC11UXX CHIP_LPC1125
FLASH_EEPROM(4003C000) CHIP_LPC11EXX/ CHIP_LPC11AXX
SPI0(40040000) CHIP_LPC110x/ CHIP_LPC11XXLV/ CHIP_LPC11CXX
SSP0(40040000) CHIP_LPC11UXX/ CHIP_LPC11EXX/ CHIP_LPC11AXX CHIP_LPC1125
IOCONF(40044000) CHIP_LPC110x/ CHIP_LPC11XXLV/ CHIP_LPC11CXX/ CHIP_LPC11UXX/ CHIP_LPC11EXX/ CHIP_LPC11AXX CHIP_LPC1125
SYSCON(40048000) CHIP_LPC110x/ CHIP_LPC11XXLV/ CHIP_LPC11CXX/ CHIP_LPC11UXX/ CHIP_LPC11EXX/ CHIP_LPC11AXX CHIP_LPC1125
GPIOINTS(4004C000) CHIP_LPC11UXX/ CHIP_LPC11EXX/ CHIP_LPC11AXX
USB(40080000) CHIP_LPC11UXX
CCAN(40050000) CHIP_LPC11CXX
SPI1(40058000) CHIP_LPC11CXX
SSP1(40058000) CHIP_LPC11UXX/ CHIP_LPC11EXX/ CHIP_LPC11AXX CHIP_LPC1125
GPIO_GRP0_INT(4005C000) CHIP_LPC11UXX/ CHIP_LPC11EXX/ CHIP_LPC11AXX
GPIO_GRP1_INT(40060000) CHIP_LPC11UXX/ CHIP_LPC11EXX/ CHIP_LPC11AXX
GPIO_PORT(50000000) CHIP_LPC11UXX/ CHIP_LPC11EXX/ CHIP_LPC11AXX
GPIO_PIO0(50000000) CHIP_LPC110x/ CHIP_LPC11XXLV/ CHIP_LPC11CXX CHIP_LPC1125
GPIO_PIO1(50010000) CHIP_LPC110x/ CHIP_LPC11XXLV/ CHIP_LPC11CXX CHIP_LPC1125
GPIO_PIO2(50020000) CHIP_LPC11XXLV/ CHIP_LPC11CXX CHIP_LPC1125
GPIO_PIO3(50030000) CHIP_LPC11XXLV/ CHIP_LPC11CXX CHIP_LPC1125
*/
/** @defgroup PERIPH_11XX_BASE CHIP: LPC11xx Peripheral addresses and register set declarations
* @ingroup CHIP_11XX_Drivers
* @{
*/
#define LPC_I2C_BASE 0x40000000
#define LPC_WWDT_BASE 0x40004000
#define LPC_USART_BASE 0x40008000
#define LPC_TIMER16_0_BASE 0x4000C000
#define LPC_TIMER16_1_BASE 0x40010000
#define LPC_TIMER32_0_BASE 0x40014000
#define LPC_TIMER32_1_BASE 0x40018000
#define LPC_ADC_BASE 0x4001C000
#define LPC_DAC_BASE 0x40024000
#define LPC_ACMP_BASE 0x40028000
#define LPC_PMU_BASE 0x40038000
#define LPC_FLASH_BASE 0x4003C000
#define LPC_SSP0_BASE 0x40040000
#define LPC_IOCON_BASE 0x40044000
#define LPC_SYSCTL_BASE 0x40048000
#define LPC_USB0_BASE 0x40080000
#define LPC_CAN0_BASE 0x40050000
#define LPC_SSP1_BASE 0x40058000
#if defined(CHIP_LPC1125)
#define LPC_USART1_BASE 0x40020000
#define LPC_USART2_BASE 0x40024000
#endif
#if defined(CHIP_LPC11UXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11AXX)
#define LPC_GPIO_PIN_INT_BASE 0x4004C000
#define LPC_GPIO_GROUP_INT0_BASE 0x4005C000
#define LPC_GPIO_GROUP_INT1_BASE 0x40060000
#define LPC_GPIO_PORT_BASE 0x50000000
#else
#define LPC_GPIO_PORT0_BASE 0x50000000
#define LPC_GPIO_PORT1_BASE 0x50010000
#if defined(CHIP_LPC11XXLV) || defined(CHIP_LPC11CXX) || defined(CHIP_LPC1125)
#define LPC_GPIO_PORT2_BASE 0x50020000
#define LPC_GPIO_PORT3_BASE 0x50030000
#endif /* defined(CHIP_LPC11XXLV) || defined(CHIP_LPC11CXX) || defined(CHIP_LPC1125) */
#endif /* defined(CHIP_LPC11UXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11AXX) */
#define IAP_ENTRY_LOCATION 0X1FFF1FF1
#define LPC_ROM_API_BASE_LOC 0x1FFF1FF8
#if !defined(CHIP_LPC110x)
#define LPC_I2C ((LPC_I2C_T *) LPC_I2C_BASE)
#endif
#define LPC_WWDT ((LPC_WWDT_T *) LPC_WWDT_BASE)
#define LPC_USART ((LPC_USART_T *) LPC_USART_BASE)
#define LPC_TIMER16_0 ((LPC_TIMER_T *) LPC_TIMER16_0_BASE)
#define LPC_TIMER16_1 ((LPC_TIMER_T *) LPC_TIMER16_1_BASE)
#define LPC_TIMER32_0 ((LPC_TIMER_T *) LPC_TIMER32_0_BASE)
#define LPC_TIMER32_1 ((LPC_TIMER_T *) LPC_TIMER32_1_BASE)
#define LPC_ADC ((LPC_ADC_T *) LPC_ADC_BASE)
#if defined(CHIP_LPC1125)
#define LPC_USART0 LPC_USART
#define LPC_USART1 ((LPC_USART_T *) LPC_USART1_BASE)
#define LPC_USART2 ((LPC_USART_T *) LPC_USART2_BASE)
#endif
#if defined(CHIP_LPC11AXX)
#define LPC_DAC ((LPC_DAC_T *) LPC_DAC_BASE)
#define LPC_CMP ((LPC_CMP_T *) LPC_ACMP_BASE)
#endif
#define LPC_PMU ((LPC_PMU_T *) LPC_PMU_BASE)
#define LPC_FMC ((LPC_FMC_T *) LPC_FLASH_BASE)
#define LPC_SSP0 ((LPC_SSP_T *) LPC_SSP0_BASE)
#define LPC_IOCON ((LPC_IOCON_T *) LPC_IOCON_BASE)
#define LPC_SYSCTL ((LPC_SYSCTL_T *) LPC_SYSCTL_BASE)
#if defined(CHIP_LPC11CXX) || defined(CHIP_LPC11UXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11AXX) || \
defined(CHIP_LPC1125)
#define LPC_SSP1 ((LPC_SSP_T *) LPC_SSP1_BASE)
#endif
#define LPC_USB ((LPC_USB_T *) LPC_USB0_BASE)
#if defined(CHIP_LPC11UXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11AXX)
#define LPC_PININT ((LPC_PIN_INT_T *) LPC_GPIO_PIN_INT_BASE)
#define LPC_GPIOGROUP ((LPC_GPIOGROUPINT_T *) LPC_GPIO_GROUP_INT0_BASE)
#define LPC_GPIO ((LPC_GPIO_T *) LPC_GPIO_PORT_BASE)
#else
#define LPC_GPIO ((LPC_GPIO_T *) LPC_GPIO_PORT0_BASE)
#endif
#define LPC_ROM_API (*((LPC_ROM_API_T * *) LPC_ROM_API_BASE_LOC))
/**
* @}
*/
/** @ingroup CHIP_11XX_DRIVER_OPTIONS
* @{
*/
/**
* @brief System oscillator rate
* This value is defined externally to the chip layer and contains
* the value in Hz for the external oscillator for the board. If using the
* internal oscillator, this rate can be 0.
*/
extern const uint32_t OscRateIn;
/**
* @brief Clock rate on the CLKIN pin
* This value is defined externally to the chip layer and contains
* the value in Hz for the CLKIN pin for the board. If this pin isn't used,
* this rate can be 0.
*/
extern const uint32_t ExtRateIn;
/**
* @}
*/
#include "pmu_11xx.h"
#include "fmc_11xx.h"
#include "sysctl_11xx.h"
#include "clock_11xx.h"
#include "iocon_11xx.h"
#include "timer_11xx.h"
#include "uart_11xx.h"
#include "wwdt_11xx.h"
#include "ssp_11xx.h"
#include "romapi_11xx.h"
#if !defined(CHIP_LPC1125)
/* All LPC1xx devices except the LPC1125 */
#include "adc_11xx.h"
#else
/* LPC1125 has different IP than other LPC11xx devices */
#include "adc_1125.h"
#endif
/* Different GPIO/GPIOGROUP/PININT blocks for parts with similar numbers */
#if defined(CHIP_LPC11CXX) || defined(CHIP_LPC110X) || defined(CHIP_LPC11XXLV) || defined(CHIP_LPC1125)
#include "gpio_11xx_2.h"
#else
#include "gpio_11xx_1.h"
#include "gpiogroup_11xx.h"
#include "pinint_11xx.h"
#endif
/* Family specific drivers */
#if defined(CHIP_LPC11AXX)
#include "acmp_11xx.h"
#include "dac_11xx.h"
#endif
#if !defined(CHIP_LPC110X)
#include "i2c_11xx.h"
#include "i2cm_11xx.h"
#endif
#if defined(CHIP_LPC11CXX)
#include "ccand_11xx.h"
#endif
#if defined(CHIP_LPC11UXX)
#include "usbd_11xx.h"
#endif
/* Family specific IRQ handler alias list */
#if (defined(CHIP_LPC11AXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX))
#define UART_IRQHandler USART_IRQHandler
#define USART0_IRQHandler USART_IRQHandler
#endif
/* Common IRQ Handler Alias list */
#define UART0_IRQHanlder UART_IRQHandler
#define I2C0_IRQHandler I2C_IRQHandler
#define CMP_IRQHandler ACMP_IRQHandler
#define WWDT_IRQHandler WDT_IRQHandler
/** @defgroup SUPPORT_11XX_FUNC CHIP: LPC11xx support functions
* @ingroup CHIP_11XX_Drivers
* @{
*/
/**
* @brief Current system clock rate, mainly used for sysTick
*/
extern uint32_t SystemCoreClock;
/**
* @brief Update system core clock rate, should be called if the
* system has a clock rate change
* @return None
*/
void SystemCoreClockUpdate(void);
/**
* @brief Set up and initialize hardware prior to call to main()
* @return None
* @note Chip_SystemInit() is called prior to the application and sets up
* system clocking prior to the application starting.
*/
void Chip_SystemInit(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __CHIP_H_ */

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/*
* @brief LPC11XX Clock control functions
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __CLOCK_11XX_H_
#define __CLOCK_11XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup CLOCK_11XX CHIP: LPC11xx Clock Control block driver
* @ingroup CHIP_11XX_Drivers
* @{
*/
/** Internal oscillator frequency */
#define SYSCTL_IRC_FREQ (12000000)
/**
* @brief Set System PLL divider values
* @param msel : PLL feedback divider value. M = msel + 1.
* @param psel : PLL post divider value. P = (1<<psel).
* @return Nothing
* @note See the user manual for how to setup the PLL.
*/
STATIC INLINE void Chip_Clock_SetupSystemPLL(uint8_t msel, uint8_t psel)
{
LPC_SYSCTL->SYSPLLCTRL = (msel & 0x1F) | ((psel & 0x3) << 5);
}
/**
* @brief Read System PLL lock status
* @return true of the PLL is locked. false if not locked
*/
STATIC INLINE bool Chip_Clock_IsSystemPLLLocked(void)
{
return (bool) ((LPC_SYSCTL->SYSPLLSTAT & 1) != 0);
}
/**
* Clock sources for system and USB PLLs
*/
typedef enum CHIP_SYSCTL_PLLCLKSRC {
SYSCTL_PLLCLKSRC_IRC = 0, /*!< Internal oscillator in */
SYSCTL_PLLCLKSRC_MAINOSC, /*!< Crystal (main) oscillator in */
#if defined(CHIP_LPC11AXX)
SYSCTL_PLLCLKSRC_EXT_CLKIN, /*!< External clock in (11Axx only) */
#else
SYSCTL_PLLCLKSRC_RESERVED1, /*!< Reserved */
#endif
SYSCTL_PLLCLKSRC_RESERVED2, /*!< Reserved */
} CHIP_SYSCTL_PLLCLKSRC_T;
/**
* @brief Set System PLL clock source
* @param src : Clock source for system PLL
* @return Nothing
* @note This function will also toggle the clock source update register
* to update the clock source.
*/
void Chip_Clock_SetSystemPLLSource(CHIP_SYSCTL_PLLCLKSRC_T src);
#if defined(CHIP_LPC11UXX)
/**
* @brief Set USB PLL divider values
* @param msel : PLL feedback divider value. M = msel + 1.
* @param psel : PLL post divider value. P = (1<<psel).
* @return Nothing
* @note See the user manual for how to setup the PLL.
*/
STATIC INLINE void Chip_Clock_SetupUSBPLL(uint8_t msel, uint8_t psel)
{
LPC_SYSCTL->USBPLLCTRL = (msel & 0x1F) | ((psel & 0x3) << 5);
}
/**
* @brief Read USB PLL lock status
* @return true of the PLL is locked. false if not locked
*/
STATIC INLINE bool Chip_Clock_IsUSBPLLLocked(void)
{
return (bool) ((LPC_SYSCTL->USBPLLSTAT & 1) != 0);
}
/**
* @brief Set USB PLL clock source
* @param src : Clock source for USB PLL
* @return Nothing
* @note This function will also toggle the clock source update register
* to update the clock source.
*/
void Chip_Clock_SetUSBPLLSource(CHIP_SYSCTL_PLLCLKSRC_T src);
#endif /*defined(CHIP_LPC11UXX)*/
/**
* @brief Bypass System Oscillator and set oscillator frequency range
* @param bypass : Flag to bypass oscillator
* @param highfr : Flag to set oscillator range from 15-25 MHz
* @return Nothing
* @note Sets the PLL input to bypass the oscillator. This would be
* used if an external clock that is not an oscillator is attached
* to the XTALIN pin.
*/
void Chip_Clock_SetPLLBypass(bool bypass, bool highfr);
/**
* Watchdog and low frequency oscillator frequencies plus or minus 40%
*/
typedef enum CHIP_WDTLFO_OSC {
WDTLFO_OSC_ILLEGAL,
WDTLFO_OSC_0_60, /*!< 0.6 MHz watchdog/LFO rate */
WDTLFO_OSC_1_05, /*!< 1.05 MHz watchdog/LFO rate */
WDTLFO_OSC_1_40, /*!< 1.4 MHz watchdog/LFO rate */
WDTLFO_OSC_1_75, /*!< 1.75 MHz watchdog/LFO rate */
WDTLFO_OSC_2_10, /*!< 2.1 MHz watchdog/LFO rate */
WDTLFO_OSC_2_40, /*!< 2.4 MHz watchdog/LFO rate */
WDTLFO_OSC_2_70, /*!< 2.7 MHz watchdog/LFO rate */
WDTLFO_OSC_3_00, /*!< 3.0 MHz watchdog/LFO rate */
WDTLFO_OSC_3_25, /*!< 3.25 MHz watchdog/LFO rate */
WDTLFO_OSC_3_50, /*!< 3.5 MHz watchdog/LFO rate */
WDTLFO_OSC_3_75, /*!< 3.75 MHz watchdog/LFO rate */
WDTLFO_OSC_4_00, /*!< 4.0 MHz watchdog/LFO rate */
WDTLFO_OSC_4_20, /*!< 4.2 MHz watchdog/LFO rate */
WDTLFO_OSC_4_40, /*!< 4.4 MHz watchdog/LFO rate */
WDTLFO_OSC_4_60 /*!< 4.6 MHz watchdog/LFO rate */
} CHIP_WDTLFO_OSC_T;
/**
* @brief Setup Watchdog oscillator rate and divider
* @param wdtclk : Selected watchdog clock rate
* @param div : Watchdog divider value, even value between 2 and 64
* @return Nothing
* @note Watchdog rate = selected rate divided by divider rate
*/
STATIC INLINE void Chip_Clock_SetWDTOSC(CHIP_WDTLFO_OSC_T wdtclk, uint8_t div)
{
LPC_SYSCTL->WDTOSCCTRL = (((uint32_t) wdtclk) << 5) | ((div >> 1) - 1);
}
#if defined(CHIP_LPC11AXX)
/**
* @brief Setup low frequency oscillator rate and divider
* @param lfoclk : Selected low frequency clock rate
* @param div : Low frequency divider value, even value between 2 and 64
* @return Nothing
* @note Low frequency oscillator rate = selected rate divided by divider rate
*/
STATIC INLINE void Chip_Clock_SetLFOSC(CHIP_WDTLFO_OSC_T lfoclk, uint8_t div)
{
LPC_SYSCTL->LFOSCCTRL = (((uint32_t) lfoclk) << 5) | ((div >> 1) - 1);
}
#endif /*CHIP_LPC11AXX*/
/**
* Clock sources for main system clock
*/
typedef enum CHIP_SYSCTL_MAINCLKSRC {
SYSCTL_MAINCLKSRC_IRC = 0, /*!< Internal oscillator */
SYSCTL_MAINCLKSRC_PLLIN, /*!< System PLL input */
SYSCTL_MAINCLKSRC_LFOSC, /*!< LF oscillator rate (11Axx only) */
SYSCTL_MAINCLKSRC_WDTOSC = SYSCTL_MAINCLKSRC_LFOSC, /*!< Watchdog oscillator rate */
SYSCTL_MAINCLKSRC_PLLOUT, /*!< System PLL output */
} CHIP_SYSCTL_MAINCLKSRC_T;
/**
* @brief Set main system clock source
* @param src : Clock source for main system
* @return Nothing
* @note This function will also toggle the clock source update register
* to update the clock source.
*/
void Chip_Clock_SetMainClockSource(CHIP_SYSCTL_MAINCLKSRC_T src);
/**
* @brief Returns the main clock source
* @return Which clock is used for the core clock source?
*/
STATIC INLINE CHIP_SYSCTL_MAINCLKSRC_T Chip_Clock_GetMainClockSource(void)
{
return (CHIP_SYSCTL_MAINCLKSRC_T) (LPC_SYSCTL->MAINCLKSEL);
}
/**
* @brief Set system clock divider
* @param div : divider for system clock
* @return Nothing
* @note Use 0 to disable, or a divider value of 1 to 255. The system clock
* rate is the main system clock divided by this value.
*/
STATIC INLINE void Chip_Clock_SetSysClockDiv(uint32_t div)
{
LPC_SYSCTL->SYSAHBCLKDIV = div;
}
/**
* System and peripheral clocks
*/
typedef enum CHIP_SYSCTL_CLOCK {
SYSCTL_CLOCK_SYS = 0, /*!< 0: System clock */
SYSCTL_CLOCK_ROM, /*!<1: ROM clock */
SYSCTL_CLOCK_RAM, /*!< 2: RAM clock */
SYSCTL_CLOCK_FLASHREG, /*!< 3: FLASH register interface clock */
SYSCTL_CLOCK_FLASHARRAY, /*!< 4: FLASH array access clock */
#if defined(CHIP_LPC110X)
SYSCTL_CLOCK_RESERVED5, /*!< 5: Reserved */
#else
SYSCTL_CLOCK_I2C, /*!< 5: I2C clock, not on LPC110x */
#endif
SYSCTL_CLOCK_GPIO, /*!< 6: GPIO clock */
SYSCTL_CLOCK_CT16B0, /*!< 7: 16-bit Counter/timer 0 clock */
SYSCTL_CLOCK_CT16B1, /*!< 8: 16-bit Counter/timer 1 clock */
SYSCTL_CLOCK_CT32B0, /*!< 9: 32-bit Counter/timer 0 clock */
SYSCTL_CLOCK_CT32B1, /*!< 10: 32-bit Counter/timer 1 clock */
SYSCTL_CLOCK_SSP0, /*!< 11: SSP0 clock */
SYSCTL_CLOCK_UART0, /*!< 12: UART0 clock */
SYSCTL_CLOCK_ADC, /*!< 13: ADC clock */
#if defined(CHIP_LPC11UXX)
SYSCTL_CLOCK_USB, /*!< 14: USB clock, LPC11Uxx only */
#else
SYSCTL_CLOCK_RESERVED14, /*!< 14: Reserved */
#endif
SYSCTL_CLOCK_WDT, /*!< 15: Watchdog timer clock */
SYSCTL_CLOCK_IOCON, /*!< 16: IOCON block clock */
#if defined(CHIP_LPC11CXX)
SYSCTL_CLOCK_CAN, /*!< 17: CAN clock, LPC11Cxx only */
#else
SYSCTL_CLOCK_RESERVED17, /*!< 17: Reserved */
#endif
#if !(defined(CHIP_LPC110X) || defined(CHIP_LPC11XXLV))
SYSCTL_CLOCK_SSP1, /*!< 18: SSP1 clock, LPC11A/C/E/Uxx//1125 only */
#if !defined(CHIP_LPC11CXX)
SYSCTL_CLOCK_PINT, /*!< 19: GPIO Pin int register interface clock, LPC11A/E/Uxx only */
#if defined(CHIP_LPC11AXX)
SYSCTL_CLOCK_ACOMP, /*!< 20: Analog comparator clock, LPC11Axx only */
SYSCTL_CLOCK_DAC, /*!< 21: DAC clock, LPC11Axx only */
#else
SYSCTL_CLOCK_RESERVED20, /*!< 20: Reserved */
SYSCTL_CLOCK_RESERVED21, /*!< 21: Reserved */
#endif
SYSCTL_CLOCK_RESERVED22, /*!< 22: Reserved */
SYSCTL_CLOCK_P0INT, /*!< 23: GPIO GROUP1 interrupt register clock, LPC11Axx only */
SYSCTL_CLOCK_GROUP0INT = SYSCTL_CLOCK_P0INT,/*!< 23: GPIO GROUP0 interrupt register interface clock, LPC11E/Uxx only */
SYSCTL_CLOCK_P1INT, /*!< 24: GPIO GROUP1 interrupt register clock, LPC11Axx only */
SYSCTL_CLOCK_GROUP1INT = SYSCTL_CLOCK_P1INT,/*!< 24: GPIO GROUP1 interrupt register interface clock, LPC11E/Uxx only */
SYSCTL_CLOCK_RESERVED25, /*!< 25: Reserved */
#if defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX)
SYSCTL_CLOCK_RAM1, /*!< 26: SRAM block (0x20000000) clock, LPC11E/Uxx only */
#else
SYSCTL_CLOCK_RESERVED26, /*!< 26: Reserved */
#endif
#if defined(CHIP_LPC11UXX)
SYSCTL_CLOCK_USBRAM, /*!< 27: USB SRAM block clock, LPC11Uxx only */
#else
SYSCTL_CLOCK_RESERVED27, /*!< 27: Reserved */
#endif
#endif /* !defined(CHIP_LPC11CXX) */
#endif /* !(defined(CHIP_LPC110X) || defined(CHIP_LPC11XXLV)) */
} CHIP_SYSCTL_CLOCK_T;
/**
* @brief Enable a system or peripheral clock
* @param clk : Clock to enable
* @return Nothing
*/
STATIC INLINE void Chip_Clock_EnablePeriphClock(CHIP_SYSCTL_CLOCK_T clk)
{
LPC_SYSCTL->SYSAHBCLKCTRL |= (1 << clk);
}
/**
* @brief Disable a system or peripheral clock
* @param clk : Clock to disable
* @return Nothing
*/
STATIC INLINE void Chip_Clock_DisablePeriphClock(CHIP_SYSCTL_CLOCK_T clk)
{
LPC_SYSCTL->SYSAHBCLKCTRL &= ~(1 << clk);
}
/**
* @brief Set SSP0 divider
* @param div : divider for SSP0 clock
* @return Nothing
* @note Use 0 to disable, or a divider value of 1 to 255. The SSP0 clock
* rate is the main system clock divided by this value.
*/
STATIC INLINE void Chip_Clock_SetSSP0ClockDiv(uint32_t div)
{
LPC_SYSCTL->SSP0CLKDIV = div;
}
/**
* @brief Return SSP0 divider
* @return divider for SSP0 clock
* @note A value of 0 means the clock is disabled.
*/
STATIC INLINE uint32_t Chip_Clock_GetSSP0ClockDiv(void)
{
return LPC_SYSCTL->SSP0CLKDIV;
}
/**
* @brief Set UART divider clock
* @param div : divider for UART clock
* @return Nothing
* @note Use 0 to disable, or a divider value of 1 to 255. The UART clock
* rate is the main system clock divided by this value.
*/
STATIC INLINE void Chip_Clock_SetUARTClockDiv(uint32_t div)
{
LPC_SYSCTL->USARTCLKDIV = div;
}
/**
* @brief Return UART divider
* @return divider for UART clock
* @note A value of 0 means the clock is disabled.
*/
STATIC INLINE uint32_t Chip_Clock_GetUARTClockDiv(void)
{
return LPC_SYSCTL->USARTCLKDIV;
}
#if defined(CHIP_LPC11CXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11AXX) || defined(CHIP_LPC11UXX) || \
defined(CHIP_LPC1125)
/**
* @brief Set SSP1 divider clock
* @param div : divider for SSP1 clock
* @return Nothing
* @note Use 0 to disable, or a divider value of 1 to 255. The SSP1 clock
* rate is the main system clock divided by this value.
*/
STATIC INLINE void Chip_Clock_SetSSP1ClockDiv(uint32_t div)
{
LPC_SYSCTL->SSP1CLKDIV = div;
}
/**
* @brief Return SSP1 divider
* @return divider for SSP1 clock
* @note A value of 0 means the clock is disabled.
*/
STATIC INLINE uint32_t Chip_Clock_GetSSP1ClockDiv(void)
{
return LPC_SYSCTL->SSP1CLKDIV;
}
#endif /*defined(CHIP_LPC11CXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11AXX) || defined(CHIP_LPC11UXX)*/
#if defined(CHIP_LPC11UXX)
/**
* Clock sources for USB
*/
typedef enum CHIP_SYSCTL_USBCLKSRC {
SYSCTL_USBCLKSRC_PLLOUT = 0, /*!< USB PLL out */
SYSCTL_USBCLKSRC_MAINSYSCLK, /*!< Main system clock */
} CHIP_SYSCTL_USBCLKSRC_T;
/**
* @brief Set USB clock source and divider
* @param src : Clock source for USB
* @param div : divider for USB clock
* @return Nothing
* @note Use 0 to disable, or a divider value of 1 to 255. The USB clock
* rate is either the main system clock or USB PLL output clock divided
* by this value. This function will also toggle the clock source
* update register to update the clock source.
*/
void Chip_Clock_SetUSBClockSource(CHIP_SYSCTL_USBCLKSRC_T src, uint32_t div);
#endif /*CHIP_LPC11UXX*/
#if defined(CHIP_LPC110X) || defined(CHIP_LPC11XXLV) || defined(CHIP_LPC11CXX) || defined(CHIP_LPC11EXX) || \
defined(CHIP_LPC1125)
/**
* Clock sources for WDT
*/
typedef enum CHIP_SYSCTL_WDTCLKSRC {
SYSCTL_WDTCLKSRC_IRC = 0, /*!< Internal oscillator for watchdog clock */
SYSCTL_WDTCLKSRC_MAINSYSCLK, /*!< Main system clock for watchdog clock */
SYSCTL_WDTCLKSRC_WDTOSC, /*!< Watchdog oscillator for watchdog clock */
} CHIP_SYSCTL_WDTCLKSRC_T;
/**
* @brief Set WDT clock source and divider
* @param src : Clock source for WDT
* @param div : divider for WDT clock
* @return Nothing
* @note Use 0 to disable, or a divider value of 1 to 255. The WDT clock
* rate is the clock source divided by the divider. This function will
* also toggle the clock source update register to update the clock
* source.
*/
void Chip_Clock_SetWDTClockSource(CHIP_SYSCTL_WDTCLKSRC_T src, uint32_t div);
#endif
#if !defined(CHIP_LPC110X)
/**
* Clock sources for CLKOUT
*/
typedef enum CHIP_SYSCTL_CLKOUTSRC {
SYSCTL_CLKOUTSRC_IRC = 0, /*!< Internal oscillator for CLKOUT */
SYSCTL_CLKOUTSRC_MAINOSC, /*!< Main oscillator for CLKOUT */
SYSCTL_CLKOUTSRC_WDTOSC, /*!< Watchdog oscillator for CLKOUT */
SYSCTL_CLKOUTSRC_LFOSC = SYSCTL_CLKOUTSRC_WDTOSC, /*!< LF oscillator rate (LPC11A/Exx only) for CLKOUT */
SYSCTL_CLKOUTSRC_MAINSYSCLK, /*!< Main system clock for CLKOUT */
} CHIP_SYSCTL_CLKOUTSRC_T;
/**
* @brief Set CLKOUT clock source and divider
* @param src : Clock source for CLKOUT
* @param div : divider for CLKOUT clock
* @return Nothing
* @note Use 0 to disable, or a divider value of 1 to 255. The CLKOUT clock
* rate is the clock source divided by the divider. This function will
* also toggle the clock source update register to update the clock
* source.
*/
void Chip_Clock_SetCLKOUTSource(CHIP_SYSCTL_CLKOUTSRC_T src, uint32_t div);
#endif
/**
* @brief Returns the main oscillator clock rate
* @return main oscillator clock rate
*/
STATIC INLINE uint32_t Chip_Clock_GetMainOscRate(void)
{
return OscRateIn;
}
/**
* @brief Returns the internal oscillator (IRC) clock rate
* @return internal oscillator (IRC) clock rate
*/
STATIC INLINE uint32_t Chip_Clock_GetIntOscRate(void)
{
return SYSCTL_IRC_FREQ;
}
#if defined(CHIP_LPC11AXX)
/**
* @brief Returns the external clock input rate
* @return internal external clock input rate
* @note LPC11Axx devices only
*/
STATIC INLINE uint32_t Chip_Clock_GetExtClockInRate(void)
{
return ExtRateIn;
}
#endif
/**
* @brief Return estimated watchdog oscillator rate
* @return Estimated watchdog oscillator rate
* @note This rate is accurate to plus or minus 40%.
*/
uint32_t Chip_Clock_GetWDTOSCRate(void);
#if defined(CHIP_LPC11AXX)
/**
* @brief Return estimated low frequency oscillator rate
* @return Estimated low frequency oscillator rate
* @note This rate is accurate to plus or minus 40%.
*/
uint32_t Chip_Clock_GetLFOOSCRate(void);
#endif
/**
* @brief Return System PLL input clock rate
* @return System PLL input clock rate
*/
uint32_t Chip_Clock_GetSystemPLLInClockRate(void);
/**
* @brief Return System PLL output clock rate
* @return System PLL output clock rate
*/
uint32_t Chip_Clock_GetSystemPLLOutClockRate(void);
#if defined(CHIP_LPC11UXX)
/**
* @brief Return USB PLL input clock rate
* @return USB PLL input clock rate
*/
uint32_t Chip_Clock_GetUSBPLLInClockRate(void);
/**
* @brief Return USB PLL output clock rate
* @return USB PLL output clock rate
*/
uint32_t Chip_Clock_GetUSBPLLOutClockRate(void);
#endif
/**
* @brief Return main clock rate
* @return main clock rate
*/
uint32_t Chip_Clock_GetMainClockRate(void);
/**
* @brief Return system clock rate
* @return system clock rate
*/
uint32_t Chip_Clock_GetSystemClockRate(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __CLOCK_11XX_H_ */

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/*
* @brief LPC11xx selective CMSIS inclusion file
*
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __CMSIS_H_
#define __CMSIS_H_
#include "lpc_types.h"
#include "sys_config.h"
/* Select correct CMSIS include file based on CHIP_* definition */
#if defined(CHIP_LPC110X)
#include "cmsis_110x.h"
typedef LPC110X_IRQn_Type IRQn_Type;
#elif defined(CHIP_LPC1125)
#include "cmsis_1125.h"
typedef LPC1125_IRQn_Type IRQn_Type;
#elif defined(CHIP_LPC11AXX)
#include "cmsis_11axx.h"
typedef LPC11AXX_IRQn_Type IRQn_Type;
#elif defined(CHIP_LPC11CXX)
#include "cmsis_11cxx.h"
typedef LPC11CXX_IRQn_Type IRQn_Type;
#elif defined(CHIP_LPC11EXX)
#include "cmsis_11exx.h"
typedef LPC11EXX_IRQn_Type IRQn_Type;
#elif defined(CHIP_LPC11UXX)
#include "cmsis_11uxx.h"
typedef LPC11UXX_IRQn_Type IRQn_Type;
#elif defined(CHIP_LPC11XXLV)
#include "cmsis_11lvxx.h"
typedef LPC11XXLV_IRQn_Type IRQn_Type;
#else
#error "No CHIP_* definition is defined"
#endif
/* Cortex-M0 processor and core peripherals */
#include "core_cm0.h"
#endif /* __CMSIS_H_ */

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/*
* @brief Basic CMSIS include file for LPC11UXX
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __CMSIS_11UXX_H_
#define __CMSIS_11UXX_H_
#include "lpc_types.h"
#include "sys_config.h"
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup CMSIS_11UXX CHIP: LPC11UXX CMSIS include file
* @ingroup CHIP_11XX_CMSIS_Drivers
* Applies to LPC11U12, LPC11U13, LPC11U14, LPC11U23, LPC11U24,
* LPC11U34, LPC11U35, LPC11U36, and LPC11U37 devices.
* @{
*/
#if defined(__ARMCC_VERSION)
// Kill warning "#pragma push with no matching #pragma pop"
#pragma diag_suppress 2525
#pragma push
#pragma anon_unions
#elif defined(__CWCC__)
#pragma push
#pragma cpp_extensions on
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__IAR_SYSTEMS_ICC__)
// #pragma push // FIXME not usable for IAR
#pragma language=extended
#else
#error Not supported compiler type
#endif
/*
* ==========================================================================
* ---------- Interrupt Number Definition -----------------------------------
* ==========================================================================
*/
#if !defined(CHIP_LPC11UXX)
#error Incorrect or missing device variant (CHIP_LPC11UXX)
#endif
/** @defgroup CMSIS_11UXX_IRQ CHIP_LPC11UXX: LPC11UXX peripheral interrupt numbers
* @{
*/
typedef enum LPC11UXX_IRQn {
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
PIN_INT0_IRQn = 0, /*!< Pin Interrupt 0 */
PIN_INT1_IRQn = 1, /*!< Pin Interrupt 1 */
PIN_INT2_IRQn = 2, /*!< Pin Interrupt 2 */
PIN_INT3_IRQn = 3, /*!< Pin Interrupt 3 */
PIN_INT4_IRQn = 4, /*!< Pin Interrupt 4 */
PIN_INT5_IRQn = 5, /*!< Pin Interrupt 5 */
PIN_INT6_IRQn = 6, /*!< Pin Interrupt 6 */
PIN_INT7_IRQn = 7, /*!< Pin Interrupt 7 */
GINT0_IRQn = 8, /*!< GPIO GROUP 0 interrupt */
GINT1_IRQn = 9, /*!< GPIO GROUP 1 interrupt */
Reserved10_IRQn = 10, /*!< Reserved Interrupt */
Reserved11_IRQn = 11,
Reserved12_IRQn = 12,
Reserved13_IRQn = 13,
SSP1_IRQn = 14, /*!< SSP1 Interrupt */
I2C0_IRQn = 15, /*!< I2C Interrupt */
TIMER_16_0_IRQn = 16, /*!< 16-bit Timer0 Interrupt */
TIMER_16_1_IRQn = 17, /*!< 16-bit Timer1 Interrupt */
TIMER_32_0_IRQn = 18, /*!< 32-bit Timer0 Interrupt */
TIMER_32_1_IRQn = 19, /*!< 32-bit Timer1 Interrupt */
SSP0_IRQn = 20, /*!< SSP0 Interrupt */
UART0_IRQn = 21, /*!< UART Interrupt */
USB0_IRQn = 22, /*!< USB IRQ interrupt */
USB0_FIQ_IRQn = 23, /*!< USB FIQ interrupt */
ADC_IRQn = 24, /*!< A/D Converter Interrupt */
WDT_IRQn = 25, /*!< Watchdog timer Interrupt */
BOD_IRQn = 26, /*!< Brown Out Detect(BOD) Interrupt */
FMC_IRQn = 27, /*!< Flash Memory Controller Interrupt */
RESERVED28_IRQn = 28,
RESERVED29_IRQn = 29,
USB_WAKEUP_IRQn = 30, /*!< USB wake-up interrupt Interrupt */
IOH_IRQn = 31, /*!< I/O Handler IRQ (Only for LPC11U37) */
} LPC11UXX_IRQn_Type;
/**
* @}
*/
/*
* ==========================================================================
* ----------- Processor and Core Peripheral Section ------------------------
* ==========================================================================
*/
/** @defgroup CMSIS_11UXX_COMMON CHIP: LPC11uxx Cortex CMSIS definitions
* @{
*/
/* Configuration of the Cortex-M0 Processor and Core Peripherals */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __CMSIS_11UXX_H_ */

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/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V3.20
* @date 25. February 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
#ifdef __cplusplus
extern "C" {
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/** \ingroup Cortex_M0
@{
*/
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
__CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00) /*!< Cortex-M Core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#endif
/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
*/
#define __FPU_USED 0
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include <stdint.h> /* standard types definitions */
#include <core_cmInstr.h> /* Core Instruction Access */
#include <core_cmFunc.h> /* Core Function Access */
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/** \defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/** \brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
#else
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
#endif
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
#else
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
#endif
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/** \brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/*@} end of group CMSIS_CORE */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31];
__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31];
__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31];
__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31];
uint32_t RESERVED4[64];
__IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/** \brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/** \brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
are only accessible over DAP and not via processor. Therefore
they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Cortex-M0 Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
/** \brief Enable External Interrupt
The function enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Disable External Interrupt
The function disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Get Pending Interrupt
The function reads the pending register in the NVIC and returns the pending bit
for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
/** \brief Set Pending Interrupt
The function sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Clear Pending Interrupt
The function clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
}
/** \brief Set Interrupt Priority
The function sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if(IRQn < 0) {
SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
else {
NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
}
/** \brief Get Interrupt Priority
The function reads the priority of an interrupt. The interrupt
number can be positive to specify an external (device specific)
interrupt, or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority. Value is aligned automatically to the implemented
priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if(IRQn < 0) {
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
else {
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
}
/** \brief System Reset
The function initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
while(1); /* wait until reset */
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if (__Vendor_SysTickConfig == 0)
/** \brief System Tick Configuration
The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
SysTick->LOAD = ticks - 1; /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
#ifdef __cplusplus
}
#endif

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/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V3.20
* @date 25. February 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i" : : : "memory");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f" : : : "memory");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f" : : : "memory");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
__ASM volatile ("");
return(result);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
__ASM volatile ("");
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

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/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V3.20
* @date 05. March 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
#define __WFI __wfi
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/* Define macros for porting to both thumb1 and thumb2.
* For thumb1, use low register (r0-r7), specified by constrant "l"
* Otherwise, use general registers, specified by constrant "r" */
#if defined (__thumb__) && !defined (__thumb2__)
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
#define __CMSIS_GCC_USE_REG(r) "l" (r)
#else
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
#define __CMSIS_GCC_USE_REG(r) "r" (r)
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
{
__ASM volatile ("isb");
}
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
{
__ASM volatile ("dsb");
}
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
{
__ASM volatile ("dmb");
}
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
return __builtin_bswap32(value);
#else
uint32_t result;
__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
return (short)__builtin_bswap16(value);
#else
uint32_t result;
__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << (32 - op2));
}
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __ASM volatile ("bkpt "#value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return(result);
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return(result);
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
return(result);
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
{
__ASM volatile ("clrex" ::: "memory");
}
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
{
uint32_t result;
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

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/*
* @brief Error code returned by Boot ROM drivers/library functions
* @ingroup Common
*
* This file contains unified error codes to be used across driver,
* middleware, applications, hal and demo software.
*
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __LPC_ERROR_H__
#define __LPC_ERROR_H__
/** Error code returned by Boot ROM drivers/library functions
*
* Error codes are a 32-bit value with :
* - The 16 MSB contains the peripheral code number
* - The 16 LSB contains an error code number associated to that peripheral
*
*/
typedef enum
{
/**\b 0x00000000*/ LPC_OK=0, /**< enum value returned on Success */
/**\b 0xFFFFFFFF*/ ERR_FAILED = -1, /**< enum value returned on general failure */
/**\b 0xFFFFFFFE*/ ERR_TIME_OUT = -2, /**< enum value returned on general timeout */
/**\b 0xFFFFFFFD*/ ERR_BUSY = -3, /**< enum value returned when resource is busy */
/* ISP related errors */
ERR_ISP_BASE = 0x00000000,
/*0x00000001*/ ERR_ISP_INVALID_COMMAND = ERR_ISP_BASE + 1,
/*0x00000002*/ ERR_ISP_SRC_ADDR_ERROR, /* Source address not on word boundary */
/*0x00000003*/ ERR_ISP_DST_ADDR_ERROR, /* Destination address not on word or 256 byte boundary */
/*0x00000004*/ ERR_ISP_SRC_ADDR_NOT_MAPPED,
/*0x00000005*/ ERR_ISP_DST_ADDR_NOT_MAPPED,
/*0x00000006*/ ERR_ISP_COUNT_ERROR, /* Byte count is not multiple of 4 or is not a permitted value */
/*0x00000007*/ ERR_ISP_INVALID_SECTOR,
/*0x00000008*/ ERR_ISP_SECTOR_NOT_BLANK,
/*0x00000009*/ ERR_ISP_SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION,
/*0x0000000A*/ ERR_ISP_COMPARE_ERROR,
/*0x0000000B*/ ERR_ISP_BUSY, /* Flash programming hardware interface is busy */
/*0x0000000C*/ ERR_ISP_PARAM_ERROR, /* Insufficient number of parameters */
/*0x0000000D*/ ERR_ISP_ADDR_ERROR, /* Address not on word boundary */
/*0x0000000E*/ ERR_ISP_ADDR_NOT_MAPPED,
/*0x0000000F*/ ERR_ISP_CMD_LOCKED, /* Command is locked */
/*0x00000010*/ ERR_ISP_INVALID_CODE, /* Unlock code is invalid */
/*0x00000011*/ ERR_ISP_INVALID_BAUD_RATE,
/*0x00000012*/ ERR_ISP_INVALID_STOP_BIT,
/*0x00000013*/ ERR_ISP_CODE_READ_PROTECTION_ENABLED,
/* ROM API related errors */
ERR_API_BASE = 0x00010000,
/**\b 0x00010001*/ ERR_API_INVALID_PARAMS = ERR_API_BASE + 1, /**< Invalid parameters*/
/**\b 0x00010002*/ ERR_API_INVALID_PARAM1, /**< PARAM1 is invalid */
/**\b 0x00010003*/ ERR_API_INVALID_PARAM2, /**< PARAM2 is invalid */
/**\b 0x00010004*/ ERR_API_INVALID_PARAM3, /**< PARAM3 is invalid */
/**\b 0x00010005*/ ERR_API_MOD_INIT, /**< API is called before module init */
/* SPIFI API related errors */
ERR_SPIFI_BASE = 0x00020000,
/*0x00020001*/ ERR_SPIFI_DEVICE_ERROR =ERR_SPIFI_BASE+1,
/*0x00020002*/ ERR_SPIFI_INTERNAL_ERROR,
/*0x00020003*/ ERR_SPIFI_TIMEOUT,
/*0x00020004*/ ERR_SPIFI_OPERAND_ERROR,
/*0x00020005*/ ERR_SPIFI_STATUS_PROBLEM,
/*0x00020006*/ ERR_SPIFI_UNKNOWN_EXT,
/*0x00020007*/ ERR_SPIFI_UNKNOWN_ID,
/*0x00020008*/ ERR_SPIFI_UNKNOWN_TYPE,
/*0x00020009*/ ERR_SPIFI_UNKNOWN_MFG,
/* Security API related errors */
ERR_SEC_BASE = 0x00030000,
/*0x00030001*/ ERR_SEC_AES_WRONG_CMD=ERR_SEC_BASE+1,
/*0x00030002*/ ERR_SEC_AES_NOT_SUPPORTED,
/*0x00030003*/ ERR_SEC_AES_KEY_ALREADY_PROGRAMMED,
/* USB device stack related errors */
ERR_USBD_BASE = 0x00040000,
/**\b 0x00040001*/ ERR_USBD_INVALID_REQ = ERR_USBD_BASE + 1, /**< invalid request */
/**\b 0x00040002*/ ERR_USBD_UNHANDLED, /**< Callback did not process the event */
/**\b 0x00040003*/ ERR_USBD_STALL, /**< Stall the endpoint on which the call back is called */
/**\b 0x00040004*/ ERR_USBD_SEND_ZLP, /**< Send ZLP packet on the endpoint on which the call back is called */
/**\b 0x00040005*/ ERR_USBD_SEND_DATA, /**< Send data packet on the endpoint on which the call back is called */
/**\b 0x00040006*/ ERR_USBD_BAD_DESC, /**< Bad descriptor*/
/**\b 0x00040007*/ ERR_USBD_BAD_CFG_DESC,/**< Bad config descriptor*/
/**\b 0x00040008*/ ERR_USBD_BAD_INTF_DESC,/**< Bad interface descriptor*/
/**\b 0x00040009*/ ERR_USBD_BAD_EP_DESC,/**< Bad endpoint descriptor*/
/**\b 0x0004000a*/ ERR_USBD_BAD_MEM_BUF, /**< Bad alignment of buffer passed. */
/**\b 0x0004000b*/ ERR_USBD_TOO_MANY_CLASS_HDLR, /**< Too many class handlers. */
/* CGU related errors */
ERR_CGU_BASE = 0x00050000,
/*0x00050001*/ ERR_CGU_NOT_IMPL=ERR_CGU_BASE+1,
/*0x00050002*/ ERR_CGU_INVALID_PARAM,
/*0x00050003*/ ERR_CGU_INVALID_SLICE,
/*0x00050004*/ ERR_CGU_OUTPUT_GEN,
/*0x00050005*/ ERR_CGU_DIV_SRC,
/*0x00050006*/ ERR_CGU_DIV_VAL,
/*0x00050007*/ ERR_CGU_SRC
} ErrorCode_t;
#ifndef offsetof
#define offsetof(s,m) (int)&(((s *)0)->m)
#endif
#define COMPILE_TIME_ASSERT(pred) switch(0){case 0:case pred:;}
#endif /* __LPC_ERROR_H__ */

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/*
* @brief FLASH Memory Controller (FMC) registers and control functions
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __FMC_11XX_H_
#define __FMC_11XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup FMC_11XX CHIP: LPC11xx FLASH Memory Controller driver
* @ingroup CHIP_11XX_Drivers
* @{
*/
/**
* @brief FLASH Memory Controller Unit register block structure
*/
typedef struct {/*!< FMC Structure */
__I uint32_t RESERVED1[4];
__IO uint32_t FLASHTIM;
__I uint32_t RESERVED2[3];
__IO uint32_t FMSSTART;
__IO uint32_t FMSSTOP;
__I uint32_t RESERVED3;
__I uint32_t FMSW[4];
__I uint32_t RESERVED4[25];
#if defined(CHIP_LPC11AXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX)
__IO uint32_t EEMSSTART;
__IO uint32_t EEMSSTOP;
__I uint32_t EEMSSIG;
__I uint32_t RESERVED5[974];
#else
__I uint32_t RESERVED5[977];
#endif
__I uint32_t FMSTAT;
__I uint32_t RESERVED6;
__O uint32_t FMSTATCLR;
} LPC_FMC_T;
/**
* @brief FLASH Access time definitions
*/
typedef enum {
FLASHTIM_20MHZ_CPU = 0, /*!< Flash accesses use 1 CPU clocks. Use for up to 20 MHz CPU clock*/
FLASHTIM_40MHZ_CPU = 1, /*!< Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock*/
FLASHTIM_50MHZ_CPU = 2, /*!< Flash accesses use 3 CPU clocks. Use for up to 50 MHz CPU clock*/
} FMC_FLASHTIM_T;
/**
* @brief Set FLASH access time in clocks
* @param clks : Clock cycles for FLASH access (minus 1)
* @return Nothing
* @note For CPU speed up to 20MHz, use a value of 0. For up to 40MHz, use
* a value of 1. For up to 50MHz, use a value of 2.
*/
STATIC INLINE void Chip_FMC_SetFLASHAccess(FMC_FLASHTIM_T clks)
{
uint32_t tmp = LPC_FMC->FLASHTIM & (~(0x3));
/* Don't alter upper bits */
LPC_FMC->FLASHTIM = tmp | clks;
}
/**
* @brief Start computation of a signature for a FLASH memory range
* @param start : Starting FLASH address for computation
* @param stop : Ending FLASH address for computation
* @return Nothing
* @note Only bits 20..4 are used for the FLASH signature computation.
* Use the Chip_FMC_IsSignatureBusy() function to determine when the
* signature computation operation is complete and use the
* Chip_FMC_GetSignature() function to get the computed signature.
*/
STATIC INLINE void Chip_FMC_ComputeSignature(uint32_t start, uint32_t stop)
{
LPC_FMC->FMSSTART = start;
LPC_FMC->FMSTATCLR = (1 << 2);
LPC_FMC->FMSSTOP = stop | (1 << 17);
}
/**
* @brief Clear signature generation completion flag
* @return Nothing
*/
STATIC INLINE void Chip_FMC_ClearSignatureBusy(void)
{
LPC_FMC->FMSTATCLR = (1 << 2);
}
/**
* @brief Check for signature generation completion
* @return true if the signature computation is running, false if finished
*/
STATIC INLINE bool Chip_FMC_IsSignatureBusy(void)
{
return (bool) ((LPC_FMC->FMSTAT & (1 << 2)) != 0);
}
/**
* @brief Returns the generated FLASH signature value
* @param index : Signature index to get - use 0 to FMSW0, 1 to FMSW1, etc.
* @return the generated FLASH signature value
*/
STATIC INLINE uint32_t Chip_FMC_GetSignature(int index)
{
return LPC_FMC->FMSW[index];
}
#if defined(CHIP_LPC11AXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX)
/**
* @brief Start computation of a signature for a EEPROM memory range
* @param start : Starting EEPROM address for computation
* @param stop : Ending EEPROM address for computation
* @return Nothing
* @note Only bits 13..1 are used for the EEPROM signature computation.
* Use the Chip_FMC_IsEEPROMSignatureBusy() function to determine when the
* signature computation operation is complete.
*/
STATIC INLINE void Chip_FMC_ComputeEEPROMSignature(uint32_t start, uint32_t stop)
{
LPC_FMC->EEMSSTART = start;
LPC_FMC->EEMSSTOP = stop | (1UL << 31);
}
/**
* @brief Check for EEPROM signature generation completion
* @return true if the EEPROM signature computation is running, false if finished
*/
STATIC INLINE bool Chip_FMC_IsEEPROMSignatureBusy(void)
{
return (bool) ((LPC_FMC->EEMSSTOP & (1UL << 31)) != 0);
}
/**
* @brief Returns the generated EEPROM data signature value
* @return the generated EEPROM data signature value
*/
STATIC INLINE uint32_t Chip_FMC_GetEEPROMDataSignature(void)
{
return LPC_FMC->EEMSSIG & 0xFFFF;
}
/**
* @brief Returns the generated EEPROM parity signature value
* @return the generated EEPROM parity signature value
*/
STATIC INLINE uint32_t Chip_FMC_GetEEPROMParitySignature(void)
{
return LPC_FMC->EEMSSIG >> 16;
}
#endif /* defined(CHIP_LPC11AXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __FMC_11XX_H_ */

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/*
* @brief LPC11xx GPIO driver for CHIP_LPC11AXX, CHIP_LPC11EXX, and
* CHIP_LPC11UXX families only.
*
* @note
* Copyright(C) NXP Semiconductors, 2013
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __GPIO_11XX_1_H_
#define __GPIO_11XX_1_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup GPIO_11XX_1 CHIP: LPC11xx GPIO driver for CHIP_LPC11(A/E/U)XX families
* @ingroup CHIP_11XX_Drivers
* For device familes identified with CHIP definitions CHIP_LPC11AXX,
* CHIP_LPC11EXX, and CHIP_LPC11UXX only.
* @{
*/
#if defined(CHIP_LPC11AXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX)
/**
* @brief GPIO port register block structure
*/
typedef struct { /*!< GPIO_PORT Structure */
__IO uint8_t B[128][32]; /*!< Offset 0x0000: Byte pin registers ports 0 to n; pins PIOn_0 to PIOn_31 */
__IO uint32_t W[32][32]; /*!< Offset 0x1000: Word pin registers port 0 to n */
__IO uint32_t DIR[32]; /*!< Offset 0x2000: Direction registers port n */
__IO uint32_t MASK[32]; /*!< Offset 0x2080: Mask register port n */
__IO uint32_t PIN[32]; /*!< Offset 0x2100: Portpin register port n */
__IO uint32_t MPIN[32]; /*!< Offset 0x2180: Masked port register port n */
__IO uint32_t SET[32]; /*!< Offset 0x2200: Write: Set register for port n Read: output bits for port n */
__O uint32_t CLR[32]; /*!< Offset 0x2280: Clear port n */
__O uint32_t NOT[32]; /*!< Offset 0x2300: Toggle port n */
} LPC_GPIO_T;
/**
* @brief Initialize GPIO block
* @param pGPIO : The base of GPIO peripheral on the chip
* @return Nothing
*/
void Chip_GPIO_Init(LPC_GPIO_T *pGPIO);
/**
* @brief De-Initialize GPIO block
* @param pGPIO : The base of GPIO peripheral on the chip
* @return Nothing
*/
void Chip_GPIO_DeInit(LPC_GPIO_T *pGPIO);
/**
* @brief Set a GPIO port/bit state
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO port to set
* @param pin : GPIO pin to set
* @param setting : true for high, false for low
* @return Nothing
*/
STATIC INLINE void Chip_GPIO_WritePortBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t pin, bool setting)
{
pGPIO->B[port][pin] = setting;
}
/**
* @brief Set a GPIO pin state via the GPIO byte register
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @param pin : GPIO pin to set
* @param setting : true for high, false for low
* @return Nothing
* @note This function replaces Chip_GPIO_WritePortBit()
*/
STATIC INLINE void Chip_GPIO_SetPinState(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, bool setting)
{
pGPIO->B[port][pin] = setting;
}
/**
* @brief Read a GPIO state
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO port to read
* @param pin : GPIO pin to read
* @return true of the GPIO is high, false if low
* @note It is recommended to use the Chip_GPIO_GetPinState() function instead.
*/
STATIC INLINE bool Chip_GPIO_ReadPortBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t pin)
{
return (bool) pGPIO->B[port][pin];
}
/**
* @brief Get a GPIO pin state via the GPIO byte register
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @param pin : GPIO pin to get state for
* @return true if the GPIO is high, false if low
* @note This function replaces Chip_GPIO_ReadPortBit()
*/
STATIC INLINE bool Chip_GPIO_GetPinState(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
{
return (bool) pGPIO->B[port][pin];
}
/**
* @brief Set a GPIO direction
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO port to set
* @param bit : GPIO bit to set
* @param setting : true for output, false for input
* @return Nothing
* @note It is recommended to use the Chip_GPIO_SetPinDIROutput(),
* Chip_GPIO_SetPinDIRInput() or Chip_GPIO_SetPinDIR() functions instead
* of this function.
*/
void Chip_GPIO_WriteDirBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t bit, bool setting);
/**
* @brief Set GPIO direction for a single GPIO pin to an output
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @param pin : GPIO pin to set direction on as output
* @return Nothing
*/
STATIC INLINE void Chip_GPIO_SetPinDIROutput(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
{
pGPIO->DIR[port] |= 1UL << pin;
}
/**
* @brief Set GPIO direction for a single GPIO pin to an input
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @param pin : GPIO pin to set direction on as input
* @return Nothing
*/
STATIC INLINE void Chip_GPIO_SetPinDIRInput(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
{
pGPIO->DIR[port] &= ~(1UL << pin);
}
/**
* @brief Set GPIO direction for a single GPIO pin
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @param pin : GPIO pin to set direction for
* @param output : true for output, false for input
* @return Nothing
*/
void Chip_GPIO_SetPinDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, bool output);
/**
* @brief Read a GPIO direction (out or in)
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO port to read
* @param bit : GPIO bit to read
* @return true of the GPIO is an output, false if input
* @note It is recommended to use the Chip_GPIO_GetPinDIR() function instead.
*/
STATIC INLINE bool Chip_GPIO_ReadDirBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t bit)
{
return (bool) (((pGPIO->DIR[port]) >> bit) & 1);
}
/**
* @brief Get GPIO direction for a single GPIO pin
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @param pin : GPIO pin to get direction for
* @return true if the GPIO is an output, false if input
*/
STATIC INLINE bool Chip_GPIO_GetPinDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
{
return (bool) (((pGPIO->DIR[port]) >> pin) & 1);
}
/**
* @brief Set Direction for a GPIO port
* @param pGPIO : The base of GPIO peripheral on the chip
* @param portNum : port Number
* @param bitValue : GPIO bit to set
* @param out : Direction value, 0 = input, !0 = output
* @return None
* @note Bits set to '0' are not altered. It is recommended to use the
* Chip_GPIO_SetPortDIR() function instead.
*/
void Chip_GPIO_SetDir(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue, uint8_t out);
/**
* @brief Set GPIO direction for a all selected GPIO pins to an output
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @param pinMask : GPIO pin mask to set direction on as output (bits 0..b for pins 0..n)
* @return Nothing
* @note Sets multiple GPIO pins to the output direction, each bit's position that is
* high sets the corresponding pin number for that bit to an output.
*/
STATIC INLINE void Chip_GPIO_SetPortDIROutput(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pinMask)
{
pGPIO->DIR[port] |= pinMask;
}
/**
* @brief Set GPIO direction for a all selected GPIO pins to an input
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @param pinMask : GPIO pin mask to set direction on as input (bits 0..b for pins 0..n)
* @return Nothing
* @note Sets multiple GPIO pins to the input direction, each bit's position that is
* high sets the corresponding pin number for that bit to an input.
*/
STATIC INLINE void Chip_GPIO_SetPortDIRInput(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pinMask)
{
pGPIO->DIR[port] &= ~pinMask;
}
/**
* @brief Set GPIO direction for a all selected GPIO pins to an input or output
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @param pinMask : GPIO pin mask to set direction on (bits 0..b for pins 0..n)
* @param outSet : Direction value, false = set as inputs, true = set as outputs
* @return Nothing
* @note Sets multiple GPIO pins to the input direction, each bit's position that is
* high sets the corresponding pin number for that bit to an input.
*/
void Chip_GPIO_SetPortDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pinMask, bool outSet);
/**
* @brief Get GPIO direction for a all GPIO pins
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @return a bitfield containing the input and output states for each pin
* @note For pins 0..n, a high state in a bit corresponds to an output state for the
* same pin, while a low state corresponds to an input state.
*/
STATIC INLINE uint32_t Chip_GPIO_GetPortDIR(LPC_GPIO_T *pGPIO, uint8_t port)
{
return pGPIO->DIR[port];
}
/**
* @brief Set GPIO port mask value for GPIO masked read and write
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @param mask : Mask value for read and write
* @return Nothing
* @note Controls which bits corresponding to PIO0_n are active in the P0MPORT
* register (bit 0 = PIO0_0, bit 1 = PIO0_1, ..., bit 17 = PIO0_17).
*/
STATIC INLINE void Chip_GPIO_SetPortMask(LPC_GPIO_T *pGPIO, uint32_t port, uint32_t mask)
{
pGPIO->MASK[port] = mask;
}
/**
* @brief Get GPIO port mask value used for GPIO masked read and write
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @return Returns value set with the Chip_GPIO_SetPortMask() function.
*/
STATIC INLINE uint32_t Chip_GPIO_GetPortMask(LPC_GPIO_T *pGPIO, uint8_t port)
{
return pGPIO->MASK[port];
}
/**
* @brief Set all GPIO raw pin states (regardless of masking)
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @param value : Value to set all GPIO pin states (0..n) to
* @return Nothing
*/
STATIC INLINE void Chip_GPIO_SetPortValue(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t value)
{
pGPIO->PIN[port] = value;
}
/**
* @brief Get all GPIO raw pin states (regardless of masking)
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @return Current (raw) state of all GPIO pins
*/
STATIC INLINE uint32_t Chip_GPIO_GetPortValue(LPC_GPIO_T *pGPIO, uint8_t port)
{
return pGPIO->PIN[port];
}
/**
* @brief Set all GPIO pin states, but mask via the MASKP0 register
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @param value : Value to set all GPIO pin states (0..n) to
* @return Nothing
*/
STATIC INLINE void Chip_GPIO_SetMaskedPortValue(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t value)
{
pGPIO->MPIN[port] = value;
}
/**
* @brief Get all GPIO pin statesm but mask via the MASKP0 register
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @return Current (masked) state of all GPIO pins
*/
STATIC INLINE uint32_t Chip_GPIO_GetMaskedPortValue(LPC_GPIO_T *pGPIO, uint8_t port)
{
return pGPIO->MPIN[port];
}
/**
* @brief Set a GPIO port/bit to the high state
* @param pGPIO : The base of GPIO peripheral on the chip
* @param portNum : port number
* @param bitValue : bit(s) in the port to set high
* @return None
* @note Any bit set as a '0' will not have it's state changed. This only
* applies to ports configured as an output. It is recommended to use the
* Chip_GPIO_SetPortOutHigh() function instead.
*/
STATIC INLINE void Chip_GPIO_SetValue(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue)
{
pGPIO->SET[portNum] = bitValue;
}
/**
* @brief Set selected GPIO output pins to the high state
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @param pins : pins (0..n) to set high
* @return None
* @note Any bit set as a '0' will not have it's state changed. This only
* applies to ports configured as an output.
*/
STATIC INLINE void Chip_GPIO_SetPortOutHigh(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pins)
{
pGPIO->SET[port] = pins;
}
/**
* @brief Set an individual GPIO output pin to the high state
* @param pGPIO : The base of GPIO peripheral on the chip'
* @param port : GPIO Port number where @a pin is located
* @param pin : pin number (0..n) to set high
* @return None
* @note Any bit set as a '0' will not have it's state changed. This only
* applies to ports configured as an output.
*/
STATIC INLINE void Chip_GPIO_SetPinOutHigh(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
{
pGPIO->SET[port] = (1 << pin);
}
/**
* @brief Set a GPIO port/bit to the low state
* @param pGPIO : The base of GPIO peripheral on the chip
* @param portNum : port number
* @param bitValue : bit(s) in the port to set low
* @return None
* @note Any bit set as a '0' will not have it's state changed. This only
* applies to ports configured as an output.
*/
STATIC INLINE void Chip_GPIO_ClearValue(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue)
{
pGPIO->CLR[portNum] = bitValue;
}
/**
* @brief Set selected GPIO output pins to the low state
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @param pins : pins (0..n) to set low
* @return None
* @note Any bit set as a '0' will not have it's state changed. This only
* applies to ports configured as an output.
*/
STATIC INLINE void Chip_GPIO_SetPortOutLow(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pins)
{
pGPIO->CLR[port] = pins;
}
/**
* @brief Set an individual GPIO output pin to the low state
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @param pin : pin number (0..n) to set low
* @return None
* @note Any bit set as a '0' will not have it's state changed. This only
* applies to ports configured as an output.
*/
STATIC INLINE void Chip_GPIO_SetPinOutLow(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
{
pGPIO->CLR[port] = (1 << pin);
}
/**
* @brief Toggle selected GPIO output pins to the opposite state
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @param pins : pins (0..n) to toggle
* @return None
* @note Any bit set as a '0' will not have it's state changed. This only
* applies to ports configured as an output.
*/
STATIC INLINE void Chip_GPIO_SetPortToggle(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pins)
{
pGPIO->NOT[port] = pins;
}
/**
* @brief Toggle an individual GPIO output pin to the opposite state
* @param pGPIO : The base of GPIO peripheral on the chip
* @param port : GPIO Port number where @a pin is located
* @param pin : pin number (0..n) to toggle
* @return None
* @note Any bit set as a '0' will not have it's state changed. This only
* applies to ports configured as an output.
*/
STATIC INLINE void Chip_GPIO_SetPinToggle(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin)
{
pGPIO->NOT[port] = (1 << pin);
}
/**
* @brief Read current bit states for the selected port
* @param pGPIO : The base of GPIO peripheral on the chip
* @param portNum : port number to read
* @return Current value of GPIO port
* @note The current states of the bits for the port are read, regardless of
* whether the GPIO port bits are input or output.
*/
STATIC INLINE uint32_t Chip_GPIO_ReadValue(LPC_GPIO_T *pGPIO, uint8_t portNum)
{
return pGPIO->PIN[portNum];
}
#endif /* defined(CHIP_LPC11AXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __GPIO_11XX_1_H_ */

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/*
* @brief LPC11xx GPIO group driver for CHIP_LPC11AXX, CHIP_LPC11EXX, and
* CHIP_LPC11UXX families only.
*
* @note
* Copyright(C) NXP Semiconductors, 2013
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __GPIOGROUP_11XX_H_
#define __GPIOGROUP_11XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup GPIOGP_11XX CHIP: LPC11xx GPIO group driver for CHIP_LPC11(A/E/U)XX families
* @ingroup CHIP_11XX_Drivers
* For device familes identified with CHIP definitions CHIP_LPC11AXX,
* CHIP_LPC11EXX, and CHIP_LPC11UXX only.
* @{
*/
#if defined(CHIP_LPC11AXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX)
/**
* @brief GPIO grouped interrupt register block structure
*/
typedef struct { /*!< GPIO_GROUP_INTn Structure */
__IO uint32_t CTRL; /*!< GPIO grouped interrupt control register */
__I uint32_t RESERVED0[7];
__IO uint32_t PORT_POL[8]; /*!< GPIO grouped interrupt port polarity register */
__IO uint32_t PORT_ENA[8]; /*!< GPIO grouped interrupt port m enable register */
uint32_t RESERVED1[4072];
} LPC_GPIOGROUPINT_T;
/**
* LPC11xx GPIO group bit definitions
*/
#define GPIOGR_INT (1 << 0) /*!< GPIO interrupt pending/clear bit */
#define GPIOGR_COMB (1 << 1) /*!< GPIO interrupt OR(0)/AND(1) mode bit */
#define GPIOGR_TRIG (1 << 2) /*!< GPIO interrupt edge(0)/level(1) mode bit */
/**
* @brief Clear interrupt pending status for the selected group
* @param pGPIOGPINT : Pointer to GPIO group register block
* @param group : GPIO group number
* @return None
*/
STATIC INLINE void Chip_GPIOGP_ClearIntStatus(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group)
{
uint32_t temp;
temp = pGPIOGPINT[group].CTRL;
pGPIOGPINT[group].CTRL = temp | GPIOGR_INT;
}
/**
* @brief Returns current GPIO group inetrrupt pending status
* @param pGPIOGPINT : Pointer to GPIO group register block
* @param group : GPIO group number
* @return true if the group interrupt is pending, otherwise false.
*/
STATIC INLINE bool Chip_GPIOGP_GetIntStatus(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group)
{
return (bool) ((pGPIOGPINT[group].CTRL & GPIOGR_INT) != 0);
}
/**
* @brief Selected GPIO group functionality for trigger on any pin in group (OR mode)
* @param pGPIOGPINT : Pointer to GPIO group register block
* @param group : GPIO group number
* @return None
*/
STATIC INLINE void Chip_GPIOGP_SelectOrMode(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group)
{
pGPIOGPINT[group].CTRL &= ~GPIOGR_COMB;
}
/**
* @brief Selected GPIO group functionality for trigger on all matching pins in group (AND mode)
* @param pGPIOGPINT : Pointer to GPIO group register block
* @param group : GPIO group number
* @return None
*/
STATIC INLINE void Chip_GPIOGP_SelectAndMode(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group)
{
pGPIOGPINT[group].CTRL |= GPIOGR_COMB;
}
/**
* @brief Selected GPIO group functionality edge trigger mode
* @param pGPIOGPINT : Pointer to GPIO group register block
* @param group : GPIO group number
* @return None
*/
STATIC INLINE void Chip_GPIOGP_SelectEdgeMode(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group)
{
pGPIOGPINT[group].CTRL &= ~GPIOGR_TRIG;
}
/**
* @brief Selected GPIO group functionality level trigger mode
* @param pGPIOGPINT : Pointer to GPIO group register block
* @param group : GPIO group number
* @return None
*/
STATIC INLINE void Chip_GPIOGP_SelectLevelMode(LPC_GPIOGROUPINT_T *pGPIOGPINT, uint8_t group)
{
pGPIOGPINT[group].CTRL |= GPIOGR_TRIG;
}
/**
* @brief Set selected pins for the group and port to low level trigger
* @param pGPIOGPINT : Pointer to GPIO group register block
* @param group : GPIO group number
* @param port : GPIO port number
* @param pinMask : Or'ed value of pins to select for low level (bit 0 = pin 0, 1 = pin1, etc.)
* @return None
*/
STATIC INLINE void Chip_GPIOGP_SelectLowLevel(LPC_GPIOGROUPINT_T *pGPIOGPINT,
uint8_t group,
uint8_t port,
uint32_t pinMask)
{
pGPIOGPINT[group].PORT_POL[port] &= ~pinMask;
}
/**
* @brief Set selected pins for the group and port to high level trigger
* @param pGPIOGPINT : Pointer to GPIO group register block
* @param group : GPIO group number
* @param port : GPIO port number
* @param pinMask : Or'ed value of pins to select for high level (bit 0 = pin 0, 1 = pin1, etc.)
* @return None
*/
STATIC INLINE void Chip_GPIOGP_SelectHighLevel(LPC_GPIOGROUPINT_T *pGPIOGPINT,
uint8_t group,
uint8_t port,
uint32_t pinMask)
{
pGPIOGPINT[group].PORT_POL[port] |= pinMask;
}
/**
* @brief Disabled selected pins for the group interrupt
* @param pGPIOGPINT : Pointer to GPIO group register block
* @param group : GPIO group number
* @param port : GPIO port number
* @param pinMask : Or'ed value of pins to disable interrupt for (bit 0 = pin 0, 1 = pin1, etc.)
* @return None
* @note Disabled pins do not contrinute to the group interrupt.
*/
STATIC INLINE void Chip_GPIOGP_DisableGroupPins(LPC_GPIOGROUPINT_T *pGPIOGPINT,
uint8_t group,
uint8_t port,
uint32_t pinMask)
{
pGPIOGPINT[group].PORT_ENA[port] &= ~pinMask;
}
/**
* @brief Enable selected pins for the group interrupt
* @param pGPIOGPINT : Pointer to GPIO group register block
* @param group : GPIO group number
* @param port : GPIO port number
* @param pinMask : Or'ed value of pins to enable interrupt for (bit 0 = pin 0, 1 = pin1, etc.)
* @return None
* @note Enabled pins contribute to the group interrupt.
*/
STATIC INLINE void Chip_GPIOGP_EnableGroupPins(LPC_GPIOGROUPINT_T *pGPIOGPINT,
uint8_t group,
uint8_t port,
uint32_t pinMask)
{
pGPIOGPINT[group].PORT_ENA[port] |= pinMask;
}
#endif /* defined(CHIP_LPC11AXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __GPIOGROUP_11XX_H_ */

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/*
* @brief LPC11xx I2C driver
*
* @note
* Copyright(C) NXP Semiconductors, 2013
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __I2C_11XX_H_
#define __I2C_11XX_H_
#include "i2c_common_11xx.h"
#ifdef __cplusplus
extern "C" {
#endif
/** @ingroup CHIP_11XX_Drivers
* @{
*/
/**
* @brief Return values for SLAVE handler
* @note
* Chip drivers will usally be designed to match their events with this value
*/
#define RET_SLAVE_TX 6 /**< Return value, when 1 byte TX'd successfully */
#define RET_SLAVE_RX 5 /**< Return value, when 1 byte RX'd successfully */
#define RET_SLAVE_IDLE 2 /**< Return value, when slave enter idle mode */
#define RET_SLAVE_BUSY 0 /**< Return value, when slave is busy */
/**
* @brief I2C state handle return values
*/
#define I2C_STA_STO_RECV 0x20
/*
* @brief I2C return status code definitions
*/
#define I2C_I2STAT_NO_INF ((0xF8))/*!< No relevant information */
#define I2C_I2STAT_BUS_ERROR ((0x00))/*!< Bus Error */
/*
* @brief I2C status values
*/
#define I2C_SETUP_STATUS_ARBF (1 << 8) /**< Arbitration false */
#define I2C_SETUP_STATUS_NOACKF (1 << 9) /**< No ACK returned */
#define I2C_SETUP_STATUS_DONE (1 << 10) /**< Status DONE */
/*
* @brief I2C state handle return values
*/
#define I2C_OK 0x00
#define I2C_BYTE_SENT 0x01
#define I2C_BYTE_RECV 0x02
#define I2C_LAST_BYTE_RECV 0x04
#define I2C_SEND_END 0x08
#define I2C_RECV_END 0x10
#define I2C_STA_STO_RECV 0x20
#define I2C_ERR (0x10000000)
#define I2C_NAK_RECV (0x10000000 | 0x01)
#define I2C_CheckError(ErrorCode) (ErrorCode & 0x10000000)
/*
* @brief I2C monitor control configuration defines
*/
#define I2C_MONITOR_CFG_SCL_OUTPUT I2C_I2MMCTRL_ENA_SCL /**< SCL output enable */
#define I2C_MONITOR_CFG_MATCHALL I2C_I2MMCTRL_MATCH_ALL /**< Select interrupt register match */
/**
* @brief I2C Slave Identifiers
*/
typedef enum {
I2C_SLAVE_GENERAL, /**< Slave ID for general calls */
I2C_SLAVE_0, /**< Slave ID fo Slave Address 0 */
I2C_SLAVE_1, /**< Slave ID fo Slave Address 1 */
I2C_SLAVE_2, /**< Slave ID fo Slave Address 2 */
I2C_SLAVE_3, /**< Slave ID fo Slave Address 3 */
I2C_SLAVE_NUM_INTERFACE /**< Number of slave interfaces */
} I2C_SLAVE_ID;
/**
* @brief I2C transfer status
*/
typedef enum {
I2C_STATUS_DONE, /**< Transfer done successfully */
I2C_STATUS_NAK, /**< NAK received during transfer */
I2C_STATUS_ARBLOST, /**< Aribitration lost during transfer */
I2C_STATUS_BUSERR, /**< Bus error in I2C transfer */
I2C_STATUS_BUSY, /**< I2C is busy doing transfer */
I2C_STATUS_SLAVENAK,/**< NAK received after SLA+W or SLA+R */
} I2C_STATUS_T;
/**
* @brief Master transfer data structure definitions
*/
typedef struct {
uint8_t slaveAddr; /**< 7-bit I2C Slave address */
const uint8_t *txBuff; /**< Pointer to array of bytes to be transmitted */
int txSz; /**< Number of bytes in transmit array,
if 0 only receive transfer will be carried on */
uint8_t *rxBuff; /**< Pointer memory where bytes received from I2C be stored */
int rxSz; /**< Number of bytes to received,
if 0 only transmission we be carried on */
I2C_STATUS_T status; /**< Status of the current I2C transfer */
} I2C_XFER_T;
/**
* @brief I2C interface IDs
* @note
* All Chip functions will take this as the first parameter,
* I2C_NUM_INTERFACE must never be used for calling any Chip
* functions, it is only used to find the number of interfaces
* available in the Chip.
*/
typedef enum I2C_ID {
I2C0, /**< ID I2C0 */
I2C_NUM_INTERFACE /**< Number of I2C interfaces in the chip */
} I2C_ID_T;
/**
* @brief I2C master events
*/
typedef enum {
I2C_EVENT_WAIT = 1, /**< I2C Wait event */
I2C_EVENT_DONE, /**< Done event that wakes up Wait event */
I2C_EVENT_LOCK, /**< Re-entrency lock event for I2C transfer */
I2C_EVENT_UNLOCK, /**< Re-entrency unlock event for I2C transfer */
I2C_EVENT_SLAVE_RX, /**< Slave receive event */
I2C_EVENT_SLAVE_TX, /**< Slave transmit event */
} I2C_EVENT_T;
/**
* @brief Event handler function type
*/
typedef void (*I2C_EVENTHANDLER_T)(I2C_ID_T, I2C_EVENT_T);
/**
* @brief Initializes the LPC_I2C peripheral with specified parameter.
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @return Nothing
*/
void Chip_I2C_Init(I2C_ID_T id);
/**
* @brief De-initializes the I2C peripheral registers to their default reset values
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @return Nothing
*/
void Chip_I2C_DeInit(I2C_ID_T id);
/**
* @brief Set up clock rate for LPC_I2C peripheral.
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @param clockrate : Target clock rate value to initialized I2C peripheral (Hz)
* @return Nothing
* @note
* Parameter @a clockrate for I2C0 should be from 1000 up to 1000000
* (1 KHz to 1 MHz), as I2C0 support Fast Mode Plus. If the @a clockrate
* is more than 400 KHz (Fast Plus Mode) Board_I2C_EnableFastPlus()
* must be called prior to calling this function.
*/
void Chip_I2C_SetClockRate(I2C_ID_T id, uint32_t clockrate);
/**
* @brief Get current clock rate for LPC_I2C peripheral.
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @return The current I2C peripheral clock rate
*/
uint32_t Chip_I2C_GetClockRate(I2C_ID_T id);
/**
* @brief Transmit and Receive data in master mode
* @param id : I2C peripheral selected (I2C0, I2C1 etc)
* @param xfer : Pointer to a I2C_XFER_T structure see notes below
* @return
* Any of #I2C_STATUS_T values, xfer->txSz will have number of bytes
* not sent due to error, xfer->rxSz will have the number of bytes yet
* to be received.
* @note
* The parameter @a xfer should have its member @a slaveAddr initialized
* to the 7-Bit slave address to which the master will do the xfer, Bit0
* to bit6 should have the address and Bit8 is ignored. During the transfer
* no code (like event handler) must change the content of the memory
* pointed to by @a xfer. The member of @a xfer, @a txBuff and @a txSz be
* initialized to the memory from which the I2C must pick the data to be
* transfered to slave and the number of bytes to send respectively, similarly
* @a rxBuff and @a rxSz must have pointer to memroy where data received
* from slave be stored and the number of data to get from slave respectilvely.
*/
int Chip_I2C_MasterTransfer(I2C_ID_T id, I2C_XFER_T *xfer);
/**
* @brief Transmit data to I2C slave using I2C Master mode
* @param id : I2C peripheral ID (I2C0, I2C1 .. etc)
* @param slaveAddr : Slave address to which the data be written
* @param buff : Pointer to buffer having the array of data
* @param len : Number of bytes to be transfered from @a buff
* @return Number of bytes successfully transfered
*/
int Chip_I2C_MasterSend(I2C_ID_T id, uint8_t slaveAddr, const uint8_t *buff, uint8_t len);
/**
* @brief Transfer a command to slave and receive data from slave after a repeated start
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @param slaveAddr : Slave address of the I2C device
* @param cmd : Command (Address/Register) to be written
* @param buff : Pointer to memory that will hold the data received
* @param len : Number of bytes to receive
* @return Number of bytes successfully received
*/
int Chip_I2C_MasterCmdRead(I2C_ID_T id, uint8_t slaveAddr, uint8_t cmd, uint8_t *buff, int len);
/**
* @brief Get pointer to current function handling the events
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @return Pointer to function handing events of I2C
*/
I2C_EVENTHANDLER_T Chip_I2C_GetMasterEventHandler(I2C_ID_T id);
/**
* @brief Set function that must handle I2C events
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @param event : Pointer to function that will handle the event (Should not be NULL)
* @return 1 when successful, 0 when a transfer is on going with its own event handler
*/
int Chip_I2C_SetMasterEventHandler(I2C_ID_T id, I2C_EVENTHANDLER_T event);
/**
* @brief Set function that must handle I2C events
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @param slaveAddr : Slave address from which data be read
* @param buff : Pointer to memory where data read be stored
* @param len : Number of bytes to read from slave
* @return Number of bytes read successfully
*/
int Chip_I2C_MasterRead(I2C_ID_T id, uint8_t slaveAddr, uint8_t *buff, int len);
/**
* @brief Default event handler for polling operation
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @param event : Event ID of the event that called the function
* @return Nothing
*/
void Chip_I2C_EventHandlerPolling(I2C_ID_T id, I2C_EVENT_T event);
/**
* @brief Default event handler for interrupt base operation
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @param event : Event ID of the event that called the function
* @return Nothing
*/
void Chip_I2C_EventHandler(I2C_ID_T id, I2C_EVENT_T event);
/**
* @brief I2C Master transfer state change handler
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @return Nothing
* @note Usually called from the appropriate Interrupt handler
*/
void Chip_I2C_MasterStateHandler(I2C_ID_T id);
/**
* @brief Disable I2C peripheral's operation
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @return Nothing
*/
void Chip_I2C_Disable(I2C_ID_T id);
/**
* @brief Checks if master xfer in progress
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @return 1 if master xfer in progress 0 otherwise
* @note
* This API is generally used in interrupt handler
* of the application to decide whether to call
* master state handler or to call slave state handler
*/
int Chip_I2C_IsMasterActive(I2C_ID_T id);
/**
* @brief Setup a slave I2C device
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @param sid : I2C Slave peripheral ID (I2C_SLAVE_0, I2C_SLAVE_1 etc)
* @param xfer : Pointer to transfer structure (see note below for more info)
* @param event : Event handler for slave transfers
* @param addrMask : Address mask to use along with slave address (see notes below for more info)
* @return Nothing
* @note
* Parameter @a xfer should point to a valid I2C_XFER_T structure object
* and must have @a slaveAddr initialized with 7bit Slave address (From Bit1 to Bit7),
* Bit0 when set enables general call handling, @a slaveAddr along with @a addrMask will
* be used to match the slave address. @a rxBuff and @a txBuff must point to valid buffers
* where slave can receive or send the data from, size of which will be provided by
* @a rxSz and @a txSz respectively. Function pointed to by @a event will be called
* for the following events #I2C_EVENT_SLAVE_RX (One byte of data received successfully
* from the master and stored inside memory pointed by xfer->rxBuff, incremented
* the pointer and decremented the @a xfer->rxSz), #I2C_EVENT_SLAVE_TX (One byte of
* data from xfer->txBuff was sent to master successfully, incremented the pointer
* and decremented xfer->txSz), #I2C_EVENT_DONE (Master is done doing its transfers
* with the slave).<br>
* <br>Bit-0 of the parameter @a addrMask is reserved and should always be 0. Any bit (BIT1
* to BIT7) set in @a addrMask will make the corresponding bit in *xfer->slaveAddr* as
* don't care. Thit is, if *xfer->slaveAddr* is (0x10 << 1) and @a addrMask is (0x03 << 1) then
* 0x10, 0x11, 0x12, 0x13 will all be considered as valid slave addresses for the registered
* slave. Upon receving any event *xfer->slaveAddr* (BIT1 to BIT7) will hold the actual
* address which was received from master.<br>
* <br><b>General Call Handling</b><br>
* Slave can receive data from master using general call address (0x00). General call
* handling must be setup as given below
* - Call Chip_I2C_SlaveSetup() with argument @a sid as I2C_SLAVE_GENERAL
* - xfer->slaveAddr ignored, argument @a addrMask ignored
* - function provided by @a event will registered to be called when slave received data using addr 0x00
* - xfer->rxBuff and xfer->rxSz should be valid in argument @a xfer
* - To handle General Call only (No other slaves are configured)
* - Call Chip_I2C_SlaveSetup() with sid as I2C_SLAVE_X (X=0,1,2,3)
* - setup @a xfer with slaveAddr member set to 0, @a event is ignored hence can be NULL
* - provide @a addrMask (typically 0, if not you better be knowing what you are doing)
* - To handler General Call when other slave is active
* - Call Chip_I2C_SlaveSetup() with sid as I2C_SLAVE_X (X=0,1,2,3)
* - setup @a xfer with slaveAddr member set to 7-Bit Slave address [from Bit1 to 7]
* - Set Bit0 of @a xfer->slaveAddr as 1
* - Provide appropriate @a addrMask
* - Argument @a event must point to function, that handles events from actual slaveAddress and not the GC
* @warning
* If the slave has only one byte in its txBuff, once that byte is transfered to master the event handler
* will be called for event #I2C_EVENT_DONE. If the master attempts to read more bytes in the same transfer
* then the slave hardware will send 0xFF to master till the end of transfer, event handler will not be
* called to notify this. For more info see section below<br>
* <br><b> Last data handling in slave </b><br>
* If the user wants to implement a slave which will read a byte from a specific location over and over
* again whenever master reads the slave. If the user initializes the xfer->txBuff as the location to read
* the byte from and xfer->txSz as 1, then say, if master reads one byte; slave will send the byte read from
* xfer->txBuff and will call the event handler with #I2C_EVENT_DONE. If the master attempts to read another
* byte instead of sending the byte read from xfer->txBuff the slave hardware will send 0xFF and no event will
* occur. To handle this issue, slave should set xfer->txSz to 2, in which case when master reads the byte
* event handler will be called with #I2C_EVENT_SLAVE_TX, in which the slave implementation can reset the buffer
* and size back to original location (i.e, xfer->txBuff--, xfer->txSz++), if the master reads another byte
* in the same transfer, byte read from xfer->txBuff will be sent and #I2C_EVENT_SLAVE_TX will be called again, and
* the process repeats.
*/
void Chip_I2C_SlaveSetup(I2C_ID_T id,
I2C_SLAVE_ID sid,
I2C_XFER_T *xfer,
I2C_EVENTHANDLER_T event,
uint8_t addrMask);
/**
* @brief I2C Slave event handler
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @return Nothing
*/
void Chip_I2C_SlaveStateHandler(I2C_ID_T id);
/**
* @brief I2C peripheral state change checking
* @param id : I2C peripheral ID (I2C0, I2C1 ... etc)
* @return 1 if I2C peripheral @a id has changed its state,
* 0 if there is no state change
* @note
* This function must be used by the application when
* the polling has to be done based on state change.
*/
int Chip_I2C_IsStateChanged(I2C_ID_T id);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __I2C_11XX_H_ */

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/*
* @brief LPC11xx I2C driver
*
* @note
* Copyright(C) NXP Semiconductors, 2013
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __I2C_COMMON_11XX_H_
#define __I2C_COMMON_11XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup I2C_11XX CHIP: LPC11xx I2C driver
* @ingroup CHIP_11XX_Drivers
* @{
*/
/**
* @brief I2C register block structure
*/
typedef struct { /* I2C0 Structure */
__IO uint32_t CONSET; /*!< I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
__I uint32_t STAT; /*!< I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
__IO uint32_t DAT; /*!< I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
__IO uint32_t ADR0; /*!< I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
__IO uint32_t SCLH; /*!< SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
__IO uint32_t SCLL; /*!< SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
__O uint32_t CONCLR; /*!< I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
__IO uint32_t MMCTRL; /*!< Monitor mode control register. */
__IO uint32_t ADR1; /*!< I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
__IO uint32_t ADR2; /*!< I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
__IO uint32_t ADR3; /*!< I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
__I uint32_t DATA_BUFFER; /*!< Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
__IO uint32_t MASK[4]; /*!< I2C Slave address mask register */
} LPC_I2C_T;
/*
* @brief I2C Control Set register description
*/
#define I2C_I2CONSET_AA ((0x04))/*!< Assert acknowledge flag */
#define I2C_I2CONSET_SI ((0x08))/*!< I2C interrupt flag */
#define I2C_I2CONSET_STO ((0x10))/*!< STOP flag */
#define I2C_I2CONSET_STA ((0x20))/*!< START flag */
#define I2C_I2CONSET_I2EN ((0x40))/*!< I2C interface enable */
/*
* @brief I2C Control Clear register description
*/
#define I2C_I2CONCLR_AAC ((1 << 2)) /*!< Assert acknowledge Clear bit */
#define I2C_I2CONCLR_SIC ((1 << 3)) /*!< I2C interrupt Clear bit */
#define I2C_I2CONCLR_STOC ((1 << 4)) /*!< I2C STOP Clear bit */
#define I2C_I2CONCLR_STAC ((1 << 5)) /*!< START flag Clear bit */
#define I2C_I2CONCLR_I2ENC ((1 << 6)) /*!< I2C interface Disable bit */
/*
* @brief I2C Common Control register description
*/
#define I2C_CON_AA (1UL << 2) /*!< Assert acknowledge bit */
#define I2C_CON_SI (1UL << 3) /*!< I2C interrupt bit */
#define I2C_CON_STO (1UL << 4) /*!< I2C STOP bit */
#define I2C_CON_STA (1UL << 5) /*!< START flag bit */
#define I2C_CON_I2EN (1UL << 6) /*!< I2C interface bit */
/*
* @brief I2C Status Code definition (I2C Status register)
*/
#define I2C_STAT_CODE_BITMASK ((0xF8))/*!< Return Code mask in I2C status register */
#define I2C_STAT_CODE_ERROR ((0xFF))/*!< Return Code error mask in I2C status register */
/*
* @brief I2C Master transmit mode
*/
#define I2C_I2STAT_M_TX_START ((0x08))/*!< A start condition has been transmitted */
#define I2C_I2STAT_M_TX_RESTART ((0x10))/*!< A repeat start condition has been transmitted */
#define I2C_I2STAT_M_TX_SLAW_ACK ((0x18))/*!< SLA+W has been transmitted, ACK has been received */
#define I2C_I2STAT_M_TX_SLAW_NACK ((0x20))/*!< SLA+W has been transmitted, NACK has been received */
#define I2C_I2STAT_M_TX_DAT_ACK ((0x28))/*!< Data has been transmitted, ACK has been received */
#define I2C_I2STAT_M_TX_DAT_NACK ((0x30))/*!< Data has been transmitted, NACK has been received */
#define I2C_I2STAT_M_TX_ARB_LOST ((0x38))/*!< Arbitration lost in SLA+R/W or Data bytes */
/*
* @brief I2C Master receive mode
*/
#define I2C_I2STAT_M_RX_START ((0x08))/*!< A start condition has been transmitted */
#define I2C_I2STAT_M_RX_RESTART ((0x10))/*!< A repeat start condition has been transmitted */
#define I2C_I2STAT_M_RX_ARB_LOST ((0x38))/*!< Arbitration lost */
#define I2C_I2STAT_M_RX_SLAR_ACK ((0x40))/*!< SLA+R has been transmitted, ACK has been received */
#define I2C_I2STAT_M_RX_SLAR_NACK ((0x48))/*!< SLA+R has been transmitted, NACK has been received */
#define I2C_I2STAT_M_RX_DAT_ACK ((0x50))/*!< Data has been received, ACK has been returned */
#define I2C_I2STAT_M_RX_DAT_NACK ((0x58))/*!< Data has been received, NACK has been returned */
/*
* @brief I2C Slave receive mode
*/
#define I2C_I2STAT_S_RX_SLAW_ACK ((0x60))/*!< Own slave address has been received, ACK has been returned */
#define I2C_I2STAT_S_RX_ARB_LOST_M_SLA ((0x68))/*!< Arbitration lost in SLA+R/W as master */
// #define I2C_I2STAT_S_RX_SLAW_ACK ((0x68)) /*!< Own SLA+W has been received, ACK returned */
#define I2C_I2STAT_S_RX_GENCALL_ACK ((0x70))/*!< General call address has been received, ACK has been returned */
#define I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL ((0x78))/*!< Arbitration lost in SLA+R/W (GENERAL CALL) as master */
// #define I2C_I2STAT_S_RX_GENCALL_ACK ((0x78)) /*!< General call address has been received, ACK has been returned */
#define I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK ((0x80))/*!< Previously addressed with own SLA; Data has been received, ACK has been returned */
#define I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK ((0x88))/*!< Previously addressed with own SLA;Data has been received and NOT ACK has been returned */
#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK ((0x90))/*!< Previously addressed with General Call; Data has been received and ACK has been returned */
#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK ((0x98))/*!< Previously addressed with General Call; Data has been received and NOT ACK has been returned */
#define I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX ((0xA0))/*!< A STOP condition or repeated START condition has been received while still addressed as SLV/REC (Slave Receive) or
SLV/TRX (Slave Transmit) */
/*
* @brief I2C Slave transmit mode
*/
#define I2C_I2STAT_S_TX_SLAR_ACK ((0xA8))/*!< Own SLA+R has been received, ACK has been returned */
#define I2C_I2STAT_S_TX_ARB_LOST_M_SLA ((0xB0))/*!< Arbitration lost in SLA+R/W as master */
// #define I2C_I2STAT_S_TX_SLAR_ACK ((0xB0)) /*!< Own SLA+R has been received, ACK has been returned */
#define I2C_I2STAT_S_TX_DAT_ACK ((0xB8))/*!< Data has been transmitted, ACK has been received */
#define I2C_I2STAT_S_TX_DAT_NACK ((0xC0))/*!< Data has been transmitted, NACK has been received */
#define I2C_I2STAT_S_TX_LAST_DAT_ACK ((0xC8))/*!< Last data byte in I2DAT has been transmitted (AA = 0); ACK has been received */
#define I2C_SLAVE_TIME_OUT 0x10000000UL/*!< Time out in case of using I2C slave mode */
/*
* @brief I2C Data register definition
*/
#define I2C_I2DAT_BITMASK ((0xFF))/*!< Mask for I2DAT register */
#define I2C_I2DAT_IDLE_CHAR (0xFF) /*!< Idle data value will be send out in slave mode in case of the actual expecting data requested from the master is greater than
its sending data length that can be supported */
/*
* @brief I2C Monitor mode control register description
*/
#define I2C_I2MMCTRL_MM_ENA ((1 << 0)) /**< Monitor mode enable */
#define I2C_I2MMCTRL_ENA_SCL ((1 << 1)) /**< SCL output enable */
#define I2C_I2MMCTRL_MATCH_ALL ((1 << 2)) /**< Select interrupt register match */
#define I2C_I2MMCTRL_BITMASK ((0x07)) /**< Mask for I2MMCTRL register */
/*
* @brief I2C Data buffer register description
*/
#define I2DATA_BUFFER_BITMASK ((0xFF))/*!< I2C Data buffer register bit mask */
/*
* @brief I2C Slave Address registers definition
*/
#define I2C_I2ADR_GC ((1 << 0)) /*!< General Call enable bit */
#define I2C_I2ADR_BITMASK ((0xFF))/*!< I2C Slave Address registers bit mask */
/*
* @brief I2C Mask Register definition
*/
#define I2C_I2MASK_MASK(n) ((n & 0xFE))/*!< I2C Mask Register mask field */
/*
* @brief I2C SCL HIGH duty cycle Register definition
*/
#define I2C_I2SCLH_BITMASK ((0xFFFF)) /*!< I2C SCL HIGH duty cycle Register bit mask */
/*
* @brief I2C SCL LOW duty cycle Register definition
*/
#define I2C_I2SCLL_BITMASK ((0xFFFF)) /*!< I2C SCL LOW duty cycle Register bit mask */
/*
* @brief I2C monitor control configuration defines
*/
#define I2C_MONITOR_CFG_SCL_OUTPUT I2C_I2MMCTRL_ENA_SCL /**< SCL output enable */
#define I2C_MONITOR_CFG_MATCHALL I2C_I2MMCTRL_MATCH_ALL /**< Select interrupt register match */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __I2C_COMMON_11XX_H_ */

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/*
* @brief LPC11xx I2C driver
*
* @note
* Copyright(C) NXP Semiconductors, 2013
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __I2CM_11XX_H_
#define __I2CM_11XX_H_
#include "i2c_common_11xx.h"
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup I2CM_11XX CHIP: LPC11xx I2C master-only driver
* @ingroup I2C_11XX
* This driver only works in master mode. To describe the I2C transactions
* following symbols are used in driver documentation.
*
* Key to symbols
* ==============
* S (1 bit) : Start bit
* P (1 bit) : Stop bit
* Rd/Wr (1 bit) : Read/Write bit. Rd equals 1, Wr equals 0.
* A, NA (1 bit) : Acknowledge and Not-Acknowledge bit.
* Addr (7 bits): I2C 7 bit address. Note that this can be expanded as usual to
* get a 10 bit I2C address.
* Data (8 bits): A plain data byte. Sometimes, I write DataLow, DataHigh
* for 16 bit data.
* [..]: Data sent by I2C device, as opposed to data sent by the host adapter.
* @{
*/
/** I2CM_11XX_OPTIONS_TYPES I2C master transfer options
* @{
*/
/** Ignore NACK during data transfer. By default transfer is aborted. */
#define I2CM_XFER_OPTION_IGNORE_NACK 0x01
/** ACK last byte received. By default we NACK last byte we receive per I2C spec. */
#define I2CM_XFER_OPTION_LAST_RX_ACK 0x02
/**
* @}
*/
/** I2CM_11XX_STATUS_TYPES I2C master transfer status types
* @{
*/
#define I2CM_STATUS_OK 0x00 /*!< Requested Request was executed successfully. */
#define I2CM_STATUS_ERROR 0x01 /*!< Unknown error condition. */
#define I2CM_STATUS_NAK 0x02 /*!< No acknowledgement received from slave. */
#define I2CM_STATUS_BUS_ERROR 0x03 /*!< I2C bus error */
#define I2CM_STATUS_SLAVE_NAK 0x04 /*!< No device responded for given slave address during SLA+W or SLA+R */
#define I2CM_STATUS_ARBLOST 0x05 /*!< Arbitration lost. */
#define I2CM_STATUS_BUSY 0xFF /*!< I2C transmistter is busy. */
/**
* @}
*/
/**
* @brief Master transfer data structure definitions
*/
typedef struct {
uint8_t slaveAddr; /*!< 7-bit I2C Slave address */
uint8_t options; /*!< Options for transfer*/
uint16_t status; /*!< Status of the current I2C transfer */
uint16_t txSz; /*!< Number of bytes in transmit array,
if 0 only receive transfer will be carried on */
uint16_t rxSz; /*!< Number of bytes to received,
if 0 only transmission we be carried on */
const uint8_t *txBuff; /*!< Pointer to array of bytes to be transmitted */
uint8_t *rxBuff; /*!< Pointer memory where bytes received from I2C be stored */
} I2CM_XFER_T;
/**
* @brief Initialize I2C Interface
* @param pI2C : Pointer to selected I2C peripheral
* @return Nothing
* @note This function enables the I2C clock.
*/
void Chip_I2CM_Init(LPC_I2C_T *pI2C);
/**
* @brief Shutdown I2C Interface
* @param pI2C : Pointer to selected I2C peripheral
* @return Nothing
* @note This function disables the I2C clock.
*/
void Chip_I2CM_DeInit(LPC_I2C_T *pI2C);
/**
* @brief Sets HIGH and LOW duty cycle registers
* @param pI2C : Pointer to selected I2C peripheral
* @param sclH : Number of I2C_PCLK cycles for the SCL HIGH time.
* @param sclL : Number of I2C_PCLK cycles for the SCL LOW time.
* @return Nothing
* @note The frequency is determined by the following formula (I2C_PCLK
* is the frequency of the peripheral I2C clock): <br>
* I2C_bitFrequency = (I2C_PCLK)/(sclH + sclL);
*/
static INLINE void Chip_I2CM_SetDutyCycle(LPC_I2C_T *pI2C, uint16_t sclH, uint16_t sclL)
{
pI2C->SCLH = (uint32_t) sclH;
pI2C->SCLL = (uint32_t) sclL;
}
/**
* @brief Set up bus speed for LPC_I2C controller
* @param busSpeed : I2C bus clock rate
* @return Nothing
* @note Per I2C specification the busSpeed should be
* @li 100000 for Standard mode
* @li 400000 for Fast mode
* @li 1000000 for Fast mode plus
* IOCON registers corresponding to I2C pads should be updated
* according to the bus mode.
*/
void Chip_I2CM_SetBusSpeed(LPC_I2C_T *pI2C, uint32_t busSpeed);
/**
* @brief Transmit START or Repeat-START signal on I2C bus
* @param pI2C : Pointer to selected I2C peripheral
* @return Nothing
* @note This function sets the controller to transmit START condition when
* the bus becomes free.
*/
static INLINE void Chip_I2CM_SendStart(LPC_I2C_T *pI2C)
{
pI2C->CONSET = I2C_CON_I2EN | I2C_CON_STA;
}
/**
* @brief Reset I2C controller state
* @param pI2C : Pointer to selected I2C peripheral
* @return Nothing
* @note This function clears all control/status flags.
*/
static INLINE void Chip_I2CM_ResetControl(LPC_I2C_T *pI2C)
{
/* Reset STA, STO, SI */
pI2C->CONCLR = I2C_CON_SI | I2C_CON_STO | I2C_CON_STA | I2C_CON_AA;
}
/**
* @brief Transmit a single data byte through the I2C peripheral
* @param pI2C : Pointer to selected I2C peripheral
* @param data : Byte to transmit
* @return Nothing
* @note This function attempts to place a byte into the UART transmit
* FIFO or transmit hold register regard regardless of UART state
*
*/
static INLINE void Chip_I2CM_WriteByte(LPC_I2C_T *pI2C, uint8_t data)
{
pI2C->DAT = (uint32_t) data;
}
/**
* @brief Read a single byte data from the I2C peripheral
* @param pI2C : Pointer to selected I2C peripheral
* @return A single byte of data read
* @note This function reads a byte from the I2C receive hold register
* regardless of I2C state. The I2C status should be read first prior
* to using this function.
*/
static INLINE uint8_t Chip_I2CM_ReadByte(LPC_I2C_T *pI2C)
{
return (uint8_t) (pI2C->DAT & I2C_I2DAT_BITMASK);
}
/**
* @brief Generate NACK after receiving next byte
* @param pI2C : Pointer to selected I2C peripheral
* @return Nothing
* @note This function sets the controller to NACK after receiving next
* byte from slave transmitter. Used before receiving last byte.
*/
static INLINE void Chip_I2CM_NackNextByte(LPC_I2C_T *pI2C)
{
pI2C->CONCLR = I2C_CON_AA;
}
/**
* @brief Transmit STOP signal on I2C bus
* @param pI2C : Pointer to selected I2C peripheral
* @return Nothing
* @note This function sets the controller to transmit STOP condition.
*/
static INLINE void Chip_I2CM_SendStop(LPC_I2C_T *pI2C)
{
pI2C->CONSET = I2C_CON_STO;
}
/**
* @brief Force start I2C transmit
* @param pI2C : Pointer to selected I2C peripheral
* @return Nothing
* @note This function force I2C state machine to start transmitting.
* If an uncontrolled source generates a superfluous START or masks
* a STOP condition, then the I2C-bus stays busy indefinitely. If
* the STA flag is set and bus access is not obtained within a
* reasonable amount of time, then a forced access to the I2C-bus is
* possible. This is achieved by setting the STO flag while the STA
* flag is still set. No STOP condition is transmitted.
*/
static INLINE void Chip_I2CM_ForceStart(LPC_I2C_T *pI2C)
{
/* check if we are pending on start */
if (pI2C->CONSET & I2C_CON_STA) {
pI2C->CONSET = I2C_CON_STO;
}
else {
Chip_I2CM_SendStart(pI2C);
}
}
/**
* @brief Transmit STOP+START signal on I2C bus
* @param pI2C : Pointer to selected I2C peripheral
* @return Nothing
* @note This function sets the controller to transmit STOP condition
* followed by a START condition.
*/
static INLINE void Chip_I2CM_SendStartAfterStop(LPC_I2C_T *pI2C)
{
pI2C->CONSET = I2C_CON_STO | I2C_CON_STA;
}
/**
* @brief Check if I2C controller state changed
* @param pI2C : Pointer to selected I2C peripheral
* @return Returns 0 if state didn't change
* @note
*/
static INLINE uint32_t Chip_I2CM_StateChanged(LPC_I2C_T *pI2C)
{
return pI2C->CONSET & I2C_CON_SI;
}
/**
* @brief Clear state change interrupt flag
* @param pI2C : Pointer to selected I2C peripheral
* @return Nothing
* @note
*/
static INLINE void Chip_I2CM_ClearSI(LPC_I2C_T *pI2C)
{
pI2C->CONCLR = I2C_CON_SI | I2C_CON_STO | I2C_CON_STA;
}
/**
* @brief Check if I2C bus is free per our controller
* @param pI2C : Pointer to selected I2C peripheral
* @return Returns 0 if busy else a non-zero value.
* @note I2C controller clears STO bit when it sees STOP
* condition after a START condition on the bus.
*/
static INLINE uint32_t Chip_I2CM_BusFree(LPC_I2C_T *pI2C)
{
return !(pI2C->CONSET & I2C_CON_STO);
}
/**
* @brief Get current state of the I2C controller
* @param pI2C : Pointer to selected I2C peripheral
* @return Returns 0 if busy else a non-zero value.
* @note I2C controller clears STO bit when it sees STOP
* condition after a START condition on the bus.
*/
static INLINE uint32_t Chip_I2CM_GetCurState(LPC_I2C_T *pI2C)
{
return pI2C->STAT & I2C_STAT_CODE_BITMASK;
}
/**
* @brief Disable I2C interface
* @param pI2C : Pointer to selected I2C peripheral
* @return Nothing
* @note
*/
static INLINE void Chip_I2CM_Disable(LPC_I2C_T *pI2C)
{
pI2C->CONCLR = I2C_CON_I2EN;
}
/**
* @brief Transfer state change handler handler
* @param pI2C : Pointer to selected I2C peripheral
* @param xfer : Pointer to a I2CM_XFER_T structure see notes below
* @return Returns non-zero value on completion of transfer. The @a status
* member of @a xfer structure contains the current status of the
* transfer at the end of the call.
* @note
* The parameter @a xfer should be same as the one passed to Chip_I2CM_Xfer()
* routine.
*/
uint32_t Chip_I2CM_XferHandler(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer);
/**
* @brief Transmit and Receive data in master mode
* @param pI2C : Pointer to selected I2C peripheral
* @param xfer : Pointer to a I2CM_XFER_T structure see notes below
* @return Nothing.
* @note
* The parameter @a xfer should have its member @a slaveAddr initialized
* to the 7-Bit slave address to which the master will do the xfer, Bit0
* to bit6 should have the address and Bit8 is ignored. During the transfer
* no code (like event handler) must change the content of the memory
* pointed to by @a xfer. The member of @a xfer, @a txBuff and @a txSz be
* initialized to the memory from which the I2C must pick the data to be
* transfered to slave and the number of bytes to send respectively, similarly
* @a rxBuff and @a rxSz must have pointer to memroy where data received
* from slave be stored and the number of data to get from slave respectilvely.
* Following types of transfers are possible:
* - Write-only transfer: When @a rxSz member of @a xfer is set to 0.
*
* S Addr Wr [A] txBuff0 [A] txBuff1 [A] ... txBuffN [A] P
*
* - If I2CM_XFER_OPTION_IGNORE_NACK is set in @a options memeber
*
* S Addr Wr [A] txBuff0 [A or NA] ... txBuffN [A or NA] P
*
* - Read-only transfer: When @a txSz member of @a xfer is set to 0.
*
* S Addr Rd [A] [rxBuff0] A [rxBuff1] A ... [rxBuffN] NA P
*
* - If I2CM_XFER_OPTION_LAST_RX_ACK is set in @a options memeber
*
* S Addr Rd [A] [rxBuff0] A [rxBuff1] A ... [rxBuffN] A P
*
* - Read-Write transfer: When @a rxSz and @ txSz members of @a xfer are non-zero.
*
* S Addr Wr [A] txBuff0 [A] txBuff1 [A] ... txBuffN [A]
* S Addr Rd [A] [rxBuff0] A [rxBuff1] A ... [rxBuffN] NA P
*
*/
void Chip_I2CM_Xfer(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer);
/**
* @brief Transmit and Receive data in master mode
* @param id : I2C peripheral selected (I2C0, I2C1 etc)
* @param xfer : Pointer to a I2CM_XFER_T structure see notes below
* @return Returns non-zero value on succesful completion of transfer.
* @note
* This function operates same as Chip_I2CM_Xfer(), but is a blocking call.
*/
uint32_t Chip_I2CM_XferBlocking(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer);
/**
* @brief Write given buffer of data to I2C interface
* @param pI2C : Pointer to selected I2C peripheral
* @param buff : Pointer to buffer to be transmitted
* @param len : Length of the buffer
* @return Returns number of bytes written.
* @note This function is a blocking call. The function generates
* START/repeat-START condition on bus and starts transmitting
* data untill transfer finishes or a NACK is received. No
* STOP condition is transmitted on the bus.
*
* S Data0 [A] Data1 [A] ... DataN [A]
*/
uint32_t Chip_I2CM_Write(LPC_I2C_T *pI2C, const uint8_t *buff, uint32_t len);
/**
* @brief Read data from I2C slave to given buffer
* @param pI2C : Pointer to selected I2C peripheral
* @param buff : Pointer to buffer for data received from I2C slave
* @param len : Length of the buffer
* @return Returns number of bytes read.
* @note This function is a blocking call. The function generates
* START/repeat-START condition on bus and starts reading
* data untill requested number of bytes are read. No
* STOP condition is transmitted on the bus.
*
* S [Data0] A [Data1] A ... [DataN] A
*/
uint32_t Chip_I2CM_Read(LPC_I2C_T *pI2C, uint8_t *buff, uint32_t len);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __I2C_11XX_H_ */

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/*
* @brief IOCON registers and control functions
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __IOCON_11XX_H_
#define __IOCON_11XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup IOCON_11XX CHIP: LPC11xx IO Control driver
* @ingroup CHIP_11XX_Drivers
* @{
*/
/**
* @brief IO Configuration Unit register block structure
*/
#if defined(CHIP_LPC11UXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11AXX)
typedef struct { /*!< LPC11AXX/LPC11UXX/LPC11EXX IOCON Structure */
__IO uint32_t PIO0[24];
__IO uint32_t PIO1[32];
} LPC_IOCON_T;
#else
/**
* @brief LPC11XX I/O Configuration register offset
*/
typedef enum CHIP_IOCON_PIO {
IOCON_PIO0_0 = (0x00C >> 2),
IOCON_PIO0_1 = (0x010 >> 2),
IOCON_PIO0_2 = (0x01C >> 2),
IOCON_PIO0_3 = (0x02C >> 2),
IOCON_PIO0_4 = (0x030 >> 2),
IOCON_PIO0_5 = (0x034 >> 2),
IOCON_PIO0_6 = (0x04C >> 2),
IOCON_PIO0_7 = (0x050 >> 2),
IOCON_PIO0_8 = (0x060 >> 2),
IOCON_PIO0_9 = (0x064 >> 2),
IOCON_PIO0_10 = (0x068 >> 2),
IOCON_PIO0_11 = (0x074 >> 2),
IOCON_PIO1_0 = (0x078 >> 2),
IOCON_PIO1_1 = (0x07C >> 2),
IOCON_PIO1_2 = (0x080 >> 2),
IOCON_PIO1_3 = (0x090 >> 2),
IOCON_PIO1_4 = (0x094 >> 2),
IOCON_PIO1_5 = (0x0A0 >> 2),
IOCON_PIO1_6 = (0x0A4 >> 2),
IOCON_PIO1_7 = (0x0A8 >> 2),
IOCON_PIO1_8 = (0x014 >> 2),
IOCON_PIO1_9 = (0x038 >> 2),
IOCON_PIO1_10 = (0x06C >> 2),
IOCON_PIO1_11 = (0x098 >> 2),
IOCON_PIO2_0 = (0x008 >> 2),
IOCON_PIO2_1 = (0x028 >> 2),
IOCON_PIO2_2 = (0x05C >> 2),
IOCON_PIO2_3 = (0x08C >> 2),
IOCON_PIO2_4 = (0x040 >> 2),
IOCON_PIO2_5 = (0x044 >> 2),
IOCON_PIO2_6 = (0x000 >> 2),
IOCON_PIO2_7 = (0x020 >> 2),
IOCON_PIO2_8 = (0x024 >> 2),
IOCON_PIO2_9 = (0x054 >> 2),
IOCON_PIO2_10 = (0x058 >> 2),
#if !defined(CHIP_LPC1125)
IOCON_PIO2_11 = (0x070 >> 2),
#endif
IOCON_PIO3_0 = (0x084 >> 2),
#if !defined(CHIP_LPC1125)
IOCON_PIO3_1 = (0x088 >> 2),
#endif
IOCON_PIO3_2 = (0x09C >> 2),
IOCON_PIO3_3 = (0x0AC >> 2),
IOCON_PIO3_4 = (0x03C >> 2),
IOCON_PIO3_5 = (0x048 >> 2),
} CHIP_IOCON_PIO_T;
/**
* @brief LPC11XX Pin location select
*/
typedef enum CHIP_IOCON_PIN_LOC {
IOCON_SCKLOC_PIO0_10 = (0xB0), /*!< Selects SCK0 function in pin location PIO0_10 */
#if !defined(CHIP_LPC1125)
IOCON_SCKLOC_PIO2_11 = (0xB0 | 1), /*!< Selects SCK0 function in pin location PIO2_11 */
#endif
IOCON_SCKLOC_PIO0_6 = (0xB0 | 2), /*!< Selects SCK0 function in pin location PIO0_6 */
IOCON_DSRLOC_PIO2_1 = (0xB4), /*!< Selects DSR function in pin location PIO2_1 */
#if !defined(CHIP_LPC1125)
IOCON_DSRLOC_PIO3_1 = (0xB4 | 1), /*!< Selects DSR function in pin location PIO3_1 */
#endif
IOCON_DCDLOC_PIO2_2 = (0xB8), /*!< Selects DCD function in pin location PIO2_2 */
IOCON_DCDLOC_PIO3_2 = (0xB8 | 1), /*!< Selects DCD function in pin location PIO3_2 */
IOCON_RILOC_PIO2_3 = (0xBC), /*!< Selects RI function in pin location PIO2_3 */
IOCON_RILOC_PIO3_3 = (0xBC | 1), /*!< Selects Ri function in pin location PIO3_3 */
#if defined(CHIP_LPC1125)
IOCON_SSEL1_LOC_PIO2_2 = (0x18), /*!< Selects SSEL1 function in pin location PIO2_2 */
IOCON_SSEL1_LOC_PIO2_4 = (0x18 | 1), /*!< Selects SSEL1 function in pin location PIO2_4 */
IOCON_CT16B0_CAP0_LOC_PIO0_2 = (0xC0), /*!< Selects SSEL1 CTB16B0_CAP0 function in pin location PIO0_2 */
IOCON_CT16B0_CAP0_LOC_PIO3_3 = (0xC0 | 1), /*!< Selects SSEL1 CTB16B0_CAP0 function in pin location PIO3_3 */
IOCON_SCK1_LOC_PIO2_1 = (0xC4), /*!< Selects SCK1 function in pin location PIO2_1 */
IOCON_SCK1_LOC_PIO3_2 = (0xC4 | 1), /*!< Selects SCK1 function in pin location PIO3_2 */
IOCON_MISO1_LOC_PIO2_2 = (0xC8), /*!< Selects MISO1 function in pin location PIO2_2 */
IOCON_MISO1_LOC_PIO1_10 = (0xC8 | 1), /*!< Selects MISO1 function in pin location PIO1_10 */
IOCON_MOSI1_LOC_PIO2_3 = (0xCC), /*!< Selects MOSI1 function in pin location PIO2_3 */
IOCON_MOSI1_LOC_PIO1_9 = (0xCC), /*!< Selects MOSI1 function in pin location PIO1_9 */
IOCON_CT326B0_CAP0_LOC_PIO1_5 = (0xD0), /*!< Selects CT32B0_CAP0 function in pin location PIO1_5 */
IOCON_CT326B0_CAP0_LOC_PIO2_9 = (0xD0 | 1), /*!< Selects CT32B0_CAP0 function in pin location PIO2_9 */
IOCON_U0_RXD_LOC_PIO1_6 = (0xD4), /*!< Selects U0 RXD function in pin location PIO1_6 */
IOCON_U0_RXD_LOC_PIO2_7 = (0xD4 | 1), /*!< Selects U0 RXD function in pin location PIO2_7 */
IOCON_U0_RXD_LOC_PIO3_4 = (0xD4 | 3), /*!< Selects U0 RXD function in pin location PIO3_4 */
#endif
} CHIP_IOCON_PIN_LOC_T;
typedef struct { /*!< LPC11XX/LPC11XXLV/LPC11UXX IOCON Structure */
__IO uint32_t REG[48];
} LPC_IOCON_T;
#endif
/**
* IOCON function and mode selection definitions
* See the User Manual for specific modes and functions supported by the
* various LPC11xx devices. Functionality can vary per device.
*/
#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */
#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */
#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */
#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */
#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */
#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */
#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */
#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */
#define IOCON_MODE_INACT (0x0 << 3) /*!< No addition pin function */
#define IOCON_MODE_PULLDOWN (0x1 << 3) /*!< Selects pull-down function */
#define IOCON_MODE_PULLUP (0x2 << 3) /*!< Selects pull-up function */
#define IOCON_MODE_REPEATER (0x3 << 3) /*!< Selects pin repeater function */
#define IOCON_HYS_EN (0x1 << 5) /*!< Enables hysteresis */
#define IOCON_INV_EN (0x1 << 6) /*!< Enables invert function on input */
#define IOCON_ADMODE_EN (0x0 << 7) /*!< Enables analog input function (analog pins only) */
#define IOCON_DIGMODE_EN (0x1 << 7) /*!< Enables digital function (analog pins only) */
#define IOCON_SFI2C_EN (0x0 << 8) /*!< I2C standard mode/fast-mode */
#define IOCON_STDI2C_EN (0x1 << 8) /*!< I2C standard I/O functionality */
#define IOCON_FASTI2C_EN (0x2 << 8) /*!< I2C Fast-mode Plus */
#define IOCON_FILT_DIS (0x1 << 8) /*!< Disables noise pulses filtering (10nS glitch filter) */
#define IOCON_OPENDRAIN_EN (0x1 << 10) /*!< Enables open-drain function */
/**
* IOCON function and mode selection definitions (old)
* For backwards compatibility.
*/
#define MD_PLN (0x0 << 3) /*!< Disable pull-down and pull-up resistor at resistor at pad */
#define MD_PDN (0x1 << 3) /*!< Enable pull-down resistor at pad */
#define MD_PUP (0x2 << 3) /*!< Enable pull-up resistor at pad */
#define MD_BUK (0x3 << 3) /*!< Enable pull-down and pull-up resistor at resistor at pad (repeater mode) */
#define MD_HYS (0x1 << 5) /*!< Enable hysteresis */
#define MD_INV (0x1 << 6) /*!< Invert enable */
#define MD_ADMODE (0x0 << 7) /*!< Select analog mode */
#define MD_DIGMODE (0x1 << 7) /*!< Select digitial mode */
#define MD_DISFIL (0x0 << 8) /*!< Disable 10nS input glitch filter */
#define MD_ENFIL (0x1 << 8) /*!< Enable 10nS input glitch filter */
#define MD_SFI2C (0x0 << 8) /*!< I2C standard mode/fast-mode */
#define MD_STDI2C (0x1 << 8) /*!< I2C standard I/O functionality */
#define MD_FASTI2C (0x2 << 8) /*!< I2C Fast-mode Plus */
#define MD_OPENDRAIN (0x1 << 10) /*!< Open drain mode bit */
#define FUNC0 0x0
#define FUNC1 0x1
#define FUNC2 0x2
#define FUNC3 0x3
#define FUNC4 0x4
#define FUNC5 0x5
#define FUNC6 0x6
#define FUNC7 0x7
#if defined(CHIP_LPC11UXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11AXX)
/**
* @brief Sets I/O Control pin mux
* @param pIOCON : The base of IOCON peripheral on the chip
* @param port : GPIO port to mux
* @param pin : GPIO pin to mux
* @param modefunc : OR'ed values or type IOCON_*
* @return Nothing
*/
void Chip_IOCON_PinMuxSet(LPC_IOCON_T *pIOCON, uint8_t port, uint8_t pin, uint32_t modefunc);
/**
* @brief I/O Control pin mux
* @param pIOCON : The base of IOCON peripheral on the chip
* @param port : GPIO port to mux
* @param pin : GPIO pin to mux
* @param mode : OR'ed values or type IOCON_*
* @param func : Pin function, value of type IOCON_FUNC?
* @return Nothing
*/
STATIC INLINE void Chip_IOCON_PinMux(LPC_IOCON_T *pIOCON, uint8_t port, uint8_t pin, uint16_t mode, uint8_t func)
{
Chip_IOCON_PinMuxSet(pIOCON, port, pin, (uint32_t) (mode | func));
}
#else
/**
* @brief Sets I/O Control pin mux
* @param pIOCON : The base of IOCON peripheral on the chip
* @param pin : GPIO pin to mux
* @param modefunc : OR'ed values or type IOCON_*
* @return Nothing
*/
STATIC INLINE void Chip_IOCON_PinMuxSet(LPC_IOCON_T *pIOCON, CHIP_IOCON_PIO_T pin, uint32_t modefunc)
{
pIOCON->REG[pin] = modefunc;
}
/**
* @brief I/O Control pin mux
* @param pIOCON : The base of IOCON peripheral on the chip
* @param pin : GPIO pin to mux
* @param mode : OR'ed values or type IOCON_*
* @param func : Pin function, value of type IOCON_FUNC?
* @return Nothing
*/
STATIC INLINE void Chip_IOCON_PinMux(LPC_IOCON_T *pIOCON, CHIP_IOCON_PIO_T pin, uint16_t mode, uint8_t func)
{
Chip_IOCON_PinMuxSet(pIOCON, pin, (uint32_t) (mode | func));
}
/**
* @brief Select pin location
* @param pIOCON : The base of IOCON peripheral on the chip
* @param sel : location selection
* @return Nothing
*/
STATIC INLINE void Chip_IOCON_PinLocSel(LPC_IOCON_T *pIOCON, CHIP_IOCON_PIN_LOC_T sel)
{
pIOCON->REG[sel >> 2] = sel & 0x03;
}
#endif /* defined(CHIP_LPC11UXX) || defined (CHIP_LPC11EXX) || defined (CHIP_LPC11AXX) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __IOCON_11XX_H_ */

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/*
* @brief Common types used in LPC functions
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __LPC_TYPES_H_
#define __LPC_TYPES_H_
#include <stdint.h>
#include <stdbool.h>
/** @defgroup LPC_Types CHIP: LPC Common Types
* @ingroup CHIP_Common
* @{
*/
/** @defgroup LPC_Types_Public_Types LPC Public Types
* @{
*/
/**
* @brief Boolean Type definition
*/
typedef enum {FALSE = 0, TRUE = !FALSE} Bool;
/**
* @brief Boolean Type definition
*/
#if !defined(__cplusplus)
// typedef enum {false = 0, true = !false} bool;
#endif
/**
* @brief Flag Status and Interrupt Flag Status type definition
*/
typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState;
#define PARAM_SETSTATE(State) ((State == RESET) || (State == SET))
/**
* @brief Functional State Definition
*/
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
#define PARAM_FUNCTIONALSTATE(State) ((State == DISABLE) || (State == ENABLE))
/**
* @ Status type definition
*/
typedef enum {ERROR = 0, SUCCESS = !ERROR} Status;
/**
* Read/Write transfer type mode (Block or non-block)
*/
typedef enum {
NONE_BLOCKING = 0, /**< None Blocking type */
BLOCKING, /**< Blocking type */
} TRANSFER_BLOCK_T;
/** Pointer to Function returning Void (any number of parameters) */
typedef void (*PFV)();
/** Pointer to Function returning int32_t (any number of parameters) */
typedef int32_t (*PFI)();
/**
* @}
*/
/** @defgroup LPC_Types_Public_Macros LPC Public Macros
* @{
*/
/* _BIT(n) sets the bit at position "n"
* _BIT(n) is intended to be used in "OR" and "AND" expressions:
* e.g., "(_BIT(3) | _BIT(7))".
*/
#undef _BIT
/* Set bit macro */
#define _BIT(n) (1 << (n))
/* _SBF(f,v) sets the bit field starting at position "f" to value "v".
* _SBF(f,v) is intended to be used in "OR" and "AND" expressions:
* e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)"
*/
#undef _SBF
/* Set bit field macro */
#define _SBF(f, v) ((v) << (f))
/* _BITMASK constructs a symbol with 'field_width' least significant
* bits set.
* e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF
* The symbol is intended to be used to limit the bit field width
* thusly:
* <a_register> = (any_expression) & _BITMASK(x), where 0 < x <= 32.
* If "any_expression" results in a value that is larger than can be
* contained in 'x' bits, the bits above 'x - 1' are masked off. When
* used with the _SBF example above, the example would be written:
* a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16))
* This ensures that the value written to a_reg is no wider than
* 16 bits, and makes the code easier to read and understand.
*/
#undef _BITMASK
/* Bitmask creation macro */
#define _BITMASK(field_width) ( _BIT(field_width) - 1)
/* NULL pointer */
#ifndef NULL
#define NULL ((void *) 0)
#endif
/* Number of elements in an array */
#define NELEMENTS(array) (sizeof(array) / sizeof(array[0]))
/* Static data/function define */
#define STATIC static
/* External data/function define */
#define EXTERN extern
#if !defined(MAX)
#define MAX(a, b) (((a) > (b)) ? (a) : (b))
#endif
#if !defined(MIN)
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
#endif
/**
* @}
*/
/* Old Type Definition compatibility */
/** @addtogroup LPC_Types_Public_Types
* @{
*/
/** LPC type for character type */
typedef char CHAR;
/** LPC type for 8 bit unsigned value */
typedef uint8_t UNS_8;
/** LPC type for 8 bit signed value */
typedef int8_t INT_8;
/** LPC type for 16 bit unsigned value */
typedef uint16_t UNS_16;
/** LPC type for 16 bit signed value */
typedef int16_t INT_16;
/** LPC type for 32 bit unsigned value */
typedef uint32_t UNS_32;
/** LPC type for 32 bit signed value */
typedef int32_t INT_32;
/** LPC type for 64 bit signed value */
typedef int64_t INT_64;
/** LPC type for 64 bit unsigned value */
typedef uint64_t UNS_64;
#ifdef __CODE_RED
#define BOOL_32 bool
#define BOOL_16 bool
#define BOOL_8 bool
#else
/** 32 bit boolean type */
typedef bool BOOL_32;
/** 16 bit boolean type */
typedef bool BOOL_16;
/** 8 bit boolean type */
typedef bool BOOL_8;
#endif
#ifdef __CC_ARM
#define INLINE __inline
#else
#define INLINE inline
#endif
/**
* @}
*/
/**
* @}
*/
#endif /* __LPC_TYPES_H_ */

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/*
* @brief LPC11xx Pin Interrupt and Pattern Match Registers and driver
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __PININT_11XX_H_
#define __PININT_11XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup PININT_11XX CHIP: LPC11xx Pin Interrupt and Pattern Match driver
* @ingroup CHIP_11XX_Drivers
* For device familes identified with CHIP definitions CHIP_LPC11AXX,
* CHIP_LPC11EXX, and CHIP_LPC11UXX only.
* @{
*/
#if defined(CHIP_LPC11AXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX)
/**
* @brief LPC11xx Pin Interrupt and Pattern Match register block structure
*/
typedef struct { /*!< PIN_INT Structure */
__IO uint32_t ISEL; /*!< Pin Interrupt Mode register */
__IO uint32_t IENR; /*!< Pin Interrupt Enable (Rising) register */
__IO uint32_t SIENR; /*!< Set Pin Interrupt Enable (Rising) register */
__IO uint32_t CIENR; /*!< Clear Pin Interrupt Enable (Rising) register */
__IO uint32_t IENF; /*!< Pin Interrupt Enable Falling Edge / Active Level register */
__IO uint32_t SIENF; /*!< Set Pin Interrupt Enable Falling Edge / Active Level register */
__IO uint32_t CIENF; /*!< Clear Pin Interrupt Enable Falling Edge / Active Level address */
__IO uint32_t RISE; /*!< Pin Interrupt Rising Edge register */
__IO uint32_t FALL; /*!< Pin Interrupt Falling Edge register */
__IO uint32_t IST; /*!< Pin Interrupt Status register */
} LPC_PIN_INT_T;
/**
* LPC11xx Pin Interrupt channel values
*/
#define PININTCH0 (1 << 0)
#define PININTCH1 (1 << 1)
#define PININTCH2 (1 << 2)
#define PININTCH3 (1 << 3)
#define PININTCH4 (1 << 4)
#define PININTCH5 (1 << 5)
#define PININTCH6 (1 << 6)
#define PININTCH7 (1 << 7)
#define PININTCH(ch) (1 << (ch))
/**
* @brief Initialize Pin interrupt block
* @param pPININT : The base address of Pin interrupt block
* @return Nothing
* @note This function should be used after the Chip_GPIO_Init() function.
*/
STATIC INLINE void Chip_PININT_Init(LPC_PIN_INT_T *pPININT) {}
/**
* @brief De-Initialize Pin interrupt block
* @param pPININT : The base address of Pin interrupt block
* @return Nothing
*/
STATIC INLINE void Chip_PININT_DeInit(LPC_PIN_INT_T *pPININT) {}
/**
* @brief Configure the pins as edge sensitive in Pin interrupt block
* @param pPININT : The base address of Pin interrupt block
* @param pins : Pins (ORed value of PININTCH*)
* @return Nothing
*/
STATIC INLINE void Chip_PININT_SetPinModeEdge(LPC_PIN_INT_T *pPININT, uint32_t pins)
{
pPININT->ISEL &= ~pins;
}
/**
* @brief Configure the pins as level sensitive in Pin interrupt block
* @param pPININT : The base address of Pin interrupt block
* @param pins : Pins (ORed value of PININTCH*)
* @return Nothing
*/
STATIC INLINE void Chip_PININT_SetPinModeLevel(LPC_PIN_INT_T *pPININT, uint32_t pins)
{
pPININT->ISEL |= pins;
}
/**
* @brief Return current PININT rising edge or high level interrupt enable state
* @param pPININT : The base address of Pin interrupt block
* @return A bifield containing the high edge/level interrupt enables for each
* interrupt. Bit 0 = PININT0, 1 = PININT1, etc.
* For each bit, a 0 means the high edge/level interrupt is disabled, while a 1
* means it's enabled.
*/
STATIC INLINE uint32_t Chip_PININT_GetHighEnabled(LPC_PIN_INT_T *pPININT)
{
return pPININT->IENR;
}
/**
* @brief Enable high edge/level PININT interrupts for pins
* @param pPININT : The base address of Pin interrupt block
* @param pins : Pins to enable (ORed value of PININTCH*)
* @return Nothing
*/
STATIC INLINE void Chip_PININT_EnableIntHigh(LPC_PIN_INT_T *pPININT, uint32_t pins)
{
pPININT->SIENR = pins;
}
/**
* @brief Disable high edge/level PININT interrupts for pins
* @param pPININT : The base address of Pin interrupt block
* @param pins : Pins to disable (ORed value of PININTCH*)
* @return Nothing
*/
STATIC INLINE void Chip_PININT_DisableIntHigh(LPC_PIN_INT_T *pPININT, uint32_t pins)
{
pPININT->CIENR = pins;
}
/**
* @brief Return current PININT falling edge or low level interrupt enable state
* @param pPININT : The base address of Pin interrupt block
* @return A bifield containing the low edge/level interrupt enables for each
* interrupt. Bit 0 = PININT0, 1 = PININT1, etc.
* For each bit, a 0 means the low edge/level interrupt is disabled, while a 1
* means it's enabled.
*/
STATIC INLINE uint32_t Chip_PININT_GetLowEnabled(LPC_PIN_INT_T *pPININT)
{
return pPININT->IENF;
}
/**
* @brief Enable low edge/level PININT interrupts for pins
* @param pPININT : The base address of Pin interrupt block
* @param pins : Pins to enable (ORed value of PININTCH*)
* @return Nothing
*/
STATIC INLINE void Chip_PININT_EnableIntLow(LPC_PIN_INT_T *pPININT, uint32_t pins)
{
pPININT->SIENF = pins;
}
/**
* @brief Disable low edge/level PININT interrupts for pins
* @param pPININT : The base address of Pin interrupt block
* @param pins : Pins to disable (ORed value of PININTCH*)
* @return Nothing
*/
STATIC INLINE void Chip_PININT_DisableIntLow(LPC_PIN_INT_T *pPININT, uint32_t pins)
{
pPININT->CIENF = pins;
}
/**
* @brief Return pin states that have a detected latched high edge (RISE) state
* @param pPININT : The base address of Pin interrupt block
* @return PININT states (bit n = high) with a latched rise state detected
*/
STATIC INLINE uint32_t Chip_PININT_GetRiseStates(LPC_PIN_INT_T *pPININT)
{
return pPININT->RISE;
}
/**
* @brief Clears pin states that had a latched high edge (RISE) state
* @param pPININT : The base address of Pin interrupt block
* @param pins : Pins with latched states to clear
* @return Nothing
*/
STATIC INLINE void Chip_PININT_ClearRiseStates(LPC_PIN_INT_T *pPININT, uint32_t pins)
{
pPININT->RISE = pins;
}
/**
* @brief Return pin states that have a detected latched falling edge (FALL) state
* @param pPININT : The base address of Pin interrupt block
* @return PININT states (bit n = high) with a latched rise state detected
*/
STATIC INLINE uint32_t Chip_PININT_GetFallStates(LPC_PIN_INT_T *pPININT)
{
return pPININT->FALL;
}
/**
* @brief Clears pin states that had a latched falling edge (FALL) state
* @param pPININT : The base address of Pin interrupt block
* @param pins : Pins with latched states to clear
* @return Nothing
*/
STATIC INLINE void Chip_PININT_ClearFallStates(LPC_PIN_INT_T *pPININT, uint32_t pins)
{
pPININT->FALL = pins;
}
/**
* @brief Get interrupt status from Pin interrupt block
* @param pPININT : The base address of Pin interrupt block
* @return Interrupt status (bit n for PININTn = high means interrupt ie pending)
*/
STATIC INLINE uint32_t Chip_PININT_GetIntStatus(LPC_PIN_INT_T *pPININT)
{
return pPININT->IST;
}
/**
* @brief Clear interrupt status in Pin interrupt block
* @param pPININT : The base address of Pin interrupt block
* @param pins : Pin interrupts to clear (ORed value of PININTCH*)
* @return Nothing
*/
STATIC INLINE void Chip_PININT_ClearIntStatus(LPC_PIN_INT_T *pPININT, uint32_t pins)
{
pPININT->IST = pins;
}
#endif /* defined(CHIP_LPC11AXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __PININT_11XX_H_ */

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/*
* @brief LPC11xx PMU chip driver
*
* @note
* Copyright(C) NXP Semiconductors, 2013
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __PMU_11XX_H_
#define __PMU_11XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup PMU_11XX CHIP: LPC11xx Power Management Unit block driver
* @ingroup CHIP_11XX_Drivers
* This driver only applies to devices in the CHIP_LPC11AXX, CHIP_LPC11CXX,
* CHIP_LPC11EXX, CHIP_LPC11UXX, and CHIP_LPC1125 families. Note different
* families may have slightly different PMU support.
* @{
*/
#if defined(CHIP_LPC11AXX) || defined(CHIP_LPC11CXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX) || \
defined(CHIP_LPC1125)
#if defined(CHIP_LPC1125)
#warning "LPC1125 support for the PMU driver is not ready"
#endif
/**
* @brief LPC11xx Power Management Unit register block structure
*/
typedef struct {
__IO uint32_t PCON; /*!< Offset: 0x000 Power control Register (R/W) */
__IO uint32_t GPREG[4]; /*!< Offset: 0x004 General purpose Registers 0..3 (R/W) */
} LPC_PMU_T;
/**
* @brief LPC11xx low power mode type definitions
*/
typedef enum CHIP_PMU_MCUPOWER {
PMU_MCU_SLEEP = 0, /*!< Sleep mode */
#if defined(CHIP_LPC11AXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX)
PMU_MCU_DEEP_SLEEP, /*!< Deep Sleep mode */
PMU_MCU_POWER_DOWN, /*!< Power down mode */
PMU_MCU_DEEP_PWRDOWN /*!< Deep power down mode */
#elif defined(CHIP_LPC11CXX)
PMU_MCU_DEEP_PWRDOWN = 3 /*!< Deep power down mode */
#endif
} CHIP_PMU_MCUPOWER_T;
/**
* PMU PCON register bit fields & masks
*/
#define PMU_PCON_PM_SLEEP (0x0) /*!< ARM WFI enter sleep mode */
#if defined(CHIP_LPC11AXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX)
#define PMU_PCON_PM_DEEPSLEEP (0x1) /*!< ARM WFI enter Deep-sleep mode */
#define PMU_PCON_PM_POWERDOWN (0x2) /*!< ARM WFI enter Power-down mode */
#define PMU_PCON_PM_DEEPPOWERDOWN (0x3) /*!< ARM WFI enter Deep Power-down mode */
#elif defined(CHIP_LPC11CXX)
#define PMU_PCON_PM_DEEPPOWERDOWN (0x2)
#endif
#define PMU_PCON_SLEEPFLAG (1 << 8) /*!< Sleep mode flag */
#define PMU_PCON_DPDFLAG (1 << 11) /*!< Deep power-down flag */
/**
* @brief Write a value to a GPREG register
* @param pPMU : Pointer to PMU register block
* @param regIndex : Register index to write to, must be 0..3
* @param value : Value to write
* @return None
*/
STATIC INLINE void Chip_PMU_WriteGPREG(LPC_PMU_T *pPMU, uint8_t regIndex, uint32_t value)
{
pPMU->GPREG[regIndex] = value;
}
/**
* @brief Read a value to a GPREG register
* @param pPMU : Pointer to PMU register block
* @param regIndex : Register index to read from, must be 0..3
* @return Value read from the GPREG register
*/
STATIC INLINE uint32_t Chip_PMU_ReadGPREG(LPC_PMU_T *pPMU, uint8_t regIndex)
{
return pPMU->GPREG[regIndex];
}
/**
* @brief Enter MCU Sleep mode
* @param pPMU : Pointer to PMU register block
* @return None
* @note The sleep mode affects the ARM Cortex-M0+ core only. Peripherals
* and memories are active.
*/
void Chip_PMU_SleepState(LPC_PMU_T *pPMU);
#if defined(CHIP_LPC11AXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX)
/**
* @brief Enter MCU Deep Sleep mode
* @param pPMU : Pointer to PMU register block
* @return None
* @note In Deep-sleep mode, the peripherals receive no internal clocks.
* The flash is in stand-by mode. The SRAM memory and all peripheral registers
* as well as the processor maintain their internal states. The WWDT, WKT,
* and BOD can remain active to wake up the system on an interrupt.
*/
void Chip_PMU_DeepSleepState(LPC_PMU_T *pPMU);
/**
* @brief Enter MCU Power down mode
* @param pPMU : Pointer to PMU register block
* @return None
* @note In Power-down mode, the peripherals receive no internal clocks.
* The internal SRAM memory and all peripheral registers as well as the
* processor maintain their internal states. The flash memory is powered
* down. The WWDT, WKT, and BOD can remain active to wake up the system
* on an interrupt.
*/
void Chip_PMU_PowerDownState(LPC_PMU_T *pPMU);
#endif
/**
* @brief Enter MCU Deep Power down mode
* @param pPMU : Pointer to PMU register block
* @return None
* @note For maximal power savings, the entire system is shut down
* except for the general purpose registers in the PMU and the self
* wake-up timer. Only the general purpose registers in the PMU maintain
* their internal states. The part can wake up on a pulse on the WAKEUP
* pin or when the self wake-up timer times out. On wake-up, the part
* reboots.
*/
void Chip_PMU_DeepPowerDownState(LPC_PMU_T *pPMU);
/**
* @brief Place the MCU in a low power state
* @param pPMU : Pointer to PMU register block
* @param SleepMode : Sleep mode
* @return None
*/
void Chip_PMU_Sleep(LPC_PMU_T *pPMU, CHIP_PMU_MCUPOWER_T SleepMode);
/**
* @brief Returns sleep/power-down flags
* @param pPMU : Pointer to PMU register block
* @return Or'ed values of PMU_PCON_SLEEPFLAG and PMU_PCON_DPDFLAG
* @note These indicate that the PMU is setup for entry into a low
* power state on the next WFI() instruction.
*/
STATIC INLINE uint32_t Chip_PMU_GetSleepFlags(LPC_PMU_T *pPMU)
{
return pPMU->PCON & (PMU_PCON_SLEEPFLAG | PMU_PCON_DPDFLAG);
}
/**
* @brief Clears sleep/power-down flags
* @param pPMU : Pointer to PMU register block
* @param flags : Or'ed value of PMU_PCON_SLEEPFLAG and PMU_PCON_DPDFLAG
* @return Nothing
* @note Use this function to clear a low power state prior to calling
* WFI().
*/
STATIC INLINE void Chip_PMU_ClearSleepFlags(LPC_PMU_T *pPMU, uint32_t flags)
{
pPMU->PCON &= ~flags;
}
#endif /* defined(CHIP_LPC11AXX) || defined(CHIP_LPC11CXX) || ... */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __PMU_11XX_H_ */

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/*
* @brief Common ring buffer support functions
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __RING_BUFFER_H_
#define __RING_BUFFER_H_
#include "lpc_types.h"
/** @defgroup Ring_Buffer CHIP: Simple ring buffer implementation
* @ingroup CHIP_Common
* @{
*/
/**
* @brief Ring buffer structure
*/
typedef struct {
void *data;
int count;
int itemSz;
uint32_t head;
uint32_t tail;
} RINGBUFF_T;
/**
* @def RB_VHEAD(rb)
* volatile typecasted head index
*/
#define RB_VHEAD(rb) (*(volatile uint32_t *) &(rb)->head)
/**
* @def RB_VTAIL(rb)
* volatile typecasted tail index
*/
#define RB_VTAIL(rb) (*(volatile uint32_t *) &(rb)->tail)
/**
* @brief Initialize ring buffer
* @param RingBuff : Pointer to ring buffer to initialize
* @param buffer : Pointer to buffer to associate with RingBuff
* @param itemSize : Size of each buffer item size
* @param count : Size of ring buffer
* @note Memory pointed by @a buffer must have correct alignment of
* @a itemSize, and @a count must be a power of 2 and must at
* least be 2 or greater.
* @return Nothing
*/
int RingBuffer_Init(RINGBUFF_T *RingBuff, void *buffer, int itemSize, int count);
/**
* @brief Resets the ring buffer to empty
* @param RingBuff : Pointer to ring buffer
* @return Nothing
*/
STATIC INLINE void RingBuffer_Flush(RINGBUFF_T *RingBuff)
{
RingBuff->head = RingBuff->tail = 0;
}
/**
* @brief Return size the ring buffer
* @param RingBuff : Pointer to ring buffer
* @return Size of the ring buffer in bytes
*/
STATIC INLINE int RingBuffer_GetSize(RINGBUFF_T *RingBuff)
{
return RingBuff->count;
}
/**
* @brief Return number of items in the ring buffer
* @param RingBuff : Pointer to ring buffer
* @return Number of items in the ring buffer
*/
STATIC INLINE int RingBuffer_GetCount(RINGBUFF_T *RingBuff)
{
return RB_VHEAD(RingBuff) - RB_VTAIL(RingBuff);
}
/**
* @brief Return number of free items in the ring buffer
* @param RingBuff : Pointer to ring buffer
* @return Number of free items in the ring buffer
*/
STATIC INLINE int RingBuffer_GetFree(RINGBUFF_T *RingBuff)
{
return RingBuff->count - RingBuffer_GetCount(RingBuff);
}
/**
* @brief Return number of items in the ring buffer
* @param RingBuff : Pointer to ring buffer
* @return 1 if the ring buffer is full, otherwise 0
*/
STATIC INLINE int RingBuffer_IsFull(RINGBUFF_T *RingBuff)
{
return (RingBuffer_GetCount(RingBuff) >= RingBuff->count);
}
/**
* @brief Return empty status of ring buffer
* @param RingBuff : Pointer to ring buffer
* @return 1 if the ring buffer is empty, otherwise 0
*/
STATIC INLINE int RingBuffer_IsEmpty(RINGBUFF_T *RingBuff)
{
return RB_VHEAD(RingBuff) == RB_VTAIL(RingBuff);
}
/**
* @brief Insert a single item into ring buffer
* @param RingBuff : Pointer to ring buffer
* @param data : pointer to item
* @return 1 when successfully inserted,
* 0 on error (Buffer not initialized using
* RingBuffer_Init() or attempted to insert
* when buffer is full)
*/
int RingBuffer_Insert(RINGBUFF_T *RingBuff, const void *data);
/**
* @brief Insert an array of items into ring buffer
* @param RingBuff : Pointer to ring buffer
* @param data : Pointer to first element of the item array
* @param num : Number of items in the array
* @return number of items successfully inserted,
* 0 on error (Buffer not initialized using
* RingBuffer_Init() or attempted to insert
* when buffer is full)
*/
int RingBuffer_InsertMult(RINGBUFF_T *RingBuff, const void *data, int num);
/**
* @brief Pop an item from the ring buffer
* @param RingBuff : Pointer to ring buffer
* @param data : Pointer to memory where popped item be stored
* @return 1 when item popped successfuly onto @a data,
* 0 When error (Buffer not initialized using
* RingBuffer_Init() or attempted to pop item when
* the buffer is empty)
*/
int RingBuffer_Pop(RINGBUFF_T *RingBuff, void *data);
/**
* @brief Pop an array of items from the ring buffer
* @param RingBuff : Pointer to ring buffer
* @param data : Pointer to memory where popped items be stored
* @param num : Max number of items array @a data can hold
* @return Number of items popped onto @a data,
* 0 on error (Buffer not initialized using RingBuffer_Init()
* or attempted to pop when the buffer is empty)
*/
int RingBuffer_PopMult(RINGBUFF_T *RingBuff, void *data, int num);
/**
* @}
*/
#endif /* __RING_BUFFER_H_ */

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/*
* @brief LPC11xx ROM API declarations and functions
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __ROMAPI_11XX_H_
#define __ROMAPI_11XX_H_
#include "error.h"
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup ROMAPI_11XX CHIP: LPC11XX ROM API declarations and functions
* @ingroup CHIP_11XX_Drivers
* @{
*/
/**
* @brief LPC11XX High level ROM API structure
*/
typedef struct {
const uint32_t usbdApiBase; /*!< USBD API function table base address */
const uint32_t reserved0; /*!< Reserved */
const uint32_t candApiBase; /*!< CAN API function table base address */
const uint32_t pwrApiBase; /*!< Power API function table base address */
const uint32_t reserved1; /*!< Reserved */
const uint32_t reserved2; /*!< Reserved */
const uint32_t reserved3; /*!< Reserved */
const uint32_t reserved4; /*!< Reserved */
} LPC_ROM_API_T;
/**
* @brief LPC11XX IAP_ENTRY API function type
*/
typedef void (*IAP_ENTRY_T)(unsigned int[], unsigned int[]);
static INLINE void iap_entry(unsigned int cmd_param[], unsigned int status_result[])
{
((IAP_ENTRY_T) IAP_ENTRY_LOCATION)(cmd_param, status_result);
}
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __ROMAPI_11XX_H_ */

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/*
* @brief LPC11xx SSP Registers and control functions
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __SSP_11XX_H_
#define __SSP_11XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup SSP_11XX CHIP: LPC11xx SSP register block and driver
* @ingroup CHIP_11XX_Drivers
* @{
*/
/**
* @brief SSP register block structure
*/
typedef struct { /*!< SSPn Structure */
__IO uint32_t CR0; /*!< Control Register 0. Selects the serial clock rate, bus type, and data size. */
__IO uint32_t CR1; /*!< Control Register 1. Selects master/slave and other modes. */
__IO uint32_t DR; /*!< Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
__I uint32_t SR; /*!< Status Register */
__IO uint32_t CPSR; /*!< Clock Prescale Register */
__IO uint32_t IMSC; /*!< Interrupt Mask Set and Clear Register */
__I uint32_t RIS; /*!< Raw Interrupt Status Register */
__I uint32_t MIS; /*!< Masked Interrupt Status Register */
__O uint32_t ICR; /*!< SSPICR Interrupt Clear Register */
} LPC_SSP_T;
/**
* Macro defines for CR0 register
*/
/** SSP data size select, must be 4 bits to 16 bits */
#define SSP_CR0_DSS(n) ((uint32_t) ((n) & 0xF))
/** SSP control 0 Motorola SPI mode */
#define SSP_CR0_FRF_SPI ((uint32_t) (0 << 4))
/** SSP control 0 TI synchronous serial mode */
#define SSP_CR0_FRF_TI ((uint32_t) (1 << 4))
/** SSP control 0 National Micro-wire mode */
#define SSP_CR0_FRF_MICROWIRE ((uint32_t) (2 << 4))
/** SPI clock polarity bit (used in SPI mode only), (1) = maintains the
bus clock high between frames, (0) = low */
#define SSP_CR0_CPOL_LO ((uint32_t) (0))
#define SSP_CR0_CPOL_HI ((uint32_t) (1 << 6))
/** SPI clock out phase bit (used in SPI mode only), (1) = captures data
on the second clock transition of the frame, (0) = first */
#define SSP_CR0_CPHA_FIRST ((uint32_t) (0))
#define SSP_CR0_CPHA_SECOND ((uint32_t) (1 << 7))
/** SSP serial clock rate value load macro, divider rate is
PERIPH_CLK / (cpsr * (SCR + 1)) */
#define SSP_CR0_SCR(n) ((uint32_t) ((n & 0xFF) << 8))
/** SSP CR0 bit mask */
#define SSP_CR0_BITMASK ((uint32_t) (0xFFFF))
/** SSP CR0 bit mask */
#define SSP_CR0_BITMASK ((uint32_t) (0xFFFF))
/** SSP serial clock rate value load macro, divider rate is
PERIPH_CLK / (cpsr * (SCR + 1)) */
#define SSP_CR0_SCR(n) ((uint32_t) ((n & 0xFF) << 8))
/**
* Macro defines for CR1 register
*/
/** SSP control 1 loopback mode enable bit */
#define SSP_CR1_LBM_EN ((uint32_t) (1 << 0))
/** SSP control 1 enable bit */
#define SSP_CR1_SSP_EN ((uint32_t) (1 << 1))
/** SSP control 1 slave enable */
#define SSP_CR1_SLAVE_EN ((uint32_t) (1 << 2))
#define SSP_CR1_MASTER_EN ((uint32_t) (0))
/** SSP control 1 slave out disable bit, disables transmit line in slave
mode */
#define SSP_CR1_SO_DISABLE ((uint32_t) (1 << 3))
/** SSP CR1 bit mask */
#define SSP_CR1_BITMASK ((uint32_t) (0x0F))
/** SSP CPSR bit mask */
#define SSP_CPSR_BITMASK ((uint32_t) (0xFF))
/**
* Macro defines for DR register
*/
/** SSP data bit mask */
#define SSP_DR_BITMASK(n) ((n) & 0xFFFF)
/**
* Macro defines for SR register
*/
/** SSP SR bit mask */
#define SSP_SR_BITMASK ((uint32_t) (0x1F))
/** ICR bit mask */
#define SSP_ICR_BITMASK ((uint32_t) (0x03))
/**
* @brief SSP Type of Status
*/
typedef enum _SSP_STATUS {
SSP_STAT_TFE = ((uint32_t)(1 << 0)),/**< TX FIFO Empty */
SSP_STAT_TNF = ((uint32_t)(1 << 1)),/**< TX FIFO not full */
SSP_STAT_RNE = ((uint32_t)(1 << 2)),/**< RX FIFO not empty */
SSP_STAT_RFF = ((uint32_t)(1 << 3)),/**< RX FIFO full */
SSP_STAT_BSY = ((uint32_t)(1 << 4)),/**< SSP Busy */
} SSP_STATUS_T;
/**
* @brief SSP Type of Interrupt Mask
*/
typedef enum _SSP_INTMASK {
SSP_RORIM = ((uint32_t)(1 << 0)), /**< Overun */
SSP_RTIM = ((uint32_t)(1 << 1)),/**< TimeOut */
SSP_RXIM = ((uint32_t)(1 << 2)),/**< Rx FIFO is at least half full */
SSP_TXIM = ((uint32_t)(1 << 3)),/**< Tx FIFO is at least half empty */
SSP_INT_MASK_BITMASK = ((uint32_t)(0xF)),
} SSP_INTMASK_T;
/**
* @brief SSP Type of Mask Interrupt Status
*/
typedef enum _SSP_MASKINTSTATUS {
SSP_RORMIS = ((uint32_t)(1 << 0)), /**< Overun */
SSP_RTMIS = ((uint32_t)(1 << 1)), /**< TimeOut */
SSP_RXMIS = ((uint32_t)(1 << 2)), /**< Rx FIFO is at least half full */
SSP_TXMIS = ((uint32_t)(1 << 3)), /**< Tx FIFO is at least half empty */
SSP_MASK_INT_STAT_BITMASK = ((uint32_t)(0xF)),
} SSP_MASKINTSTATUS_T;
/**
* @brief SSP Type of Raw Interrupt Status
*/
typedef enum _SSP_RAWINTSTATUS {
SSP_RORRIS = ((uint32_t)(1 << 0)), /**< Overun */
SSP_RTRIS = ((uint32_t)(1 << 1)), /**< TimeOut */
SSP_RXRIS = ((uint32_t)(1 << 2)), /**< Rx FIFO is at least half full */
SSP_TXRIS = ((uint32_t)(1 << 3)), /**< Tx FIFO is at least half empty */
SSP_RAW_INT_STAT_BITMASK = ((uint32_t)(0xF)),
} SSP_RAWINTSTATUS_T;
typedef enum _SSP_INTCLEAR {
SSP_RORIC = 0x0,
SSP_RTIC = 0x1,
SSP_INT_CLEAR_BITMASK = 0x3,
} SSP_INTCLEAR_T;
/*
* @brief SSP clock format
*/
typedef enum CHIP_SSP_CLOCK_FORMAT {
SSP_CLOCK_CPHA0_CPOL0 = (0 << 6), /**< CPHA = 0, CPOL = 0 */
SSP_CLOCK_CPHA0_CPOL1 = (1u << 6), /**< CPHA = 0, CPOL = 1 */
SSP_CLOCK_CPHA1_CPOL0 = (2u << 6), /**< CPHA = 1, CPOL = 0 */
SSP_CLOCK_CPHA1_CPOL1 = (3u << 6), /**< CPHA = 1, CPOL = 1 */
SSP_CLOCK_MODE0 = SSP_CLOCK_CPHA0_CPOL0,/**< alias */
SSP_CLOCK_MODE1 = SSP_CLOCK_CPHA1_CPOL0,/**< alias */
SSP_CLOCK_MODE2 = SSP_CLOCK_CPHA0_CPOL1,/**< alias */
SSP_CLOCK_MODE3 = SSP_CLOCK_CPHA1_CPOL1,/**< alias */
} CHIP_SSP_CLOCK_MODE_T;
/*
* @brief SSP frame format
*/
typedef enum CHIP_SSP_FRAME_FORMAT {
SSP_FRAMEFORMAT_SPI = (0 << 4), /**< Frame format: SPI */
CHIP_SSP_FRAME_FORMAT_TI = (1u << 4), /**< Frame format: TI SSI */
SSP_FRAMEFORMAT_MICROWIRE = (2u << 4), /**< Frame format: Microwire */
} CHIP_SSP_FRAME_FORMAT_T;
/*
* @brief Number of bits per frame
*/
typedef enum CHIP_SSP_BITS {
SSP_BITS_4 = (3u << 0), /*!< 4 bits/frame */
SSP_BITS_5 = (4u << 0), /*!< 5 bits/frame */
SSP_BITS_6 = (5u << 0), /*!< 6 bits/frame */
SSP_BITS_7 = (6u << 0), /*!< 7 bits/frame */
SSP_BITS_8 = (7u << 0), /*!< 8 bits/frame */
SSP_BITS_9 = (8u << 0), /*!< 9 bits/frame */
SSP_BITS_10 = (9u << 0), /*!< 10 bits/frame */
SSP_BITS_11 = (10u << 0), /*!< 11 bits/frame */
SSP_BITS_12 = (11u << 0), /*!< 12 bits/frame */
SSP_BITS_13 = (12u << 0), /*!< 13 bits/frame */
SSP_BITS_14 = (13u << 0), /*!< 14 bits/frame */
SSP_BITS_15 = (14u << 0), /*!< 15 bits/frame */
SSP_BITS_16 = (15u << 0), /*!< 16 bits/frame */
} CHIP_SSP_BITS_T;
/*
* @brief SSP config format
*/
typedef struct SSP_ConfigFormat {
CHIP_SSP_BITS_T bits; /*!< Format config: bits/frame */
CHIP_SSP_CLOCK_MODE_T clockMode; /*!< Format config: clock phase/polarity */
CHIP_SSP_FRAME_FORMAT_T frameFormat; /*!< Format config: SPI/TI/Microwire */
} SSP_ConfigFormat;
/**
* @brief Enable SSP operation
* @param pSSP : The base of SSP peripheral on the chip
* @return Nothing
*/
STATIC INLINE void Chip_SSP_Enable(LPC_SSP_T *pSSP)
{
pSSP->CR1 |= SSP_CR1_SSP_EN;
}
/**
* @brief Disable SSP operation
* @param pSSP : The base of SSP peripheral on the chip
* @return Nothing
*/
STATIC INLINE void Chip_SSP_Disable(LPC_SSP_T *pSSP)
{
pSSP->CR1 &= (~SSP_CR1_SSP_EN) & SSP_CR1_BITMASK;
}
/**
* @brief Enable loopback mode
* @param pSSP : The base of SSP peripheral on the chip
* @return Nothing
* @note Serial input is taken from the serial output (MOSI or MISO) rather
* than the serial input pin
*/
STATIC INLINE void Chip_SSP_EnableLoopBack(LPC_SSP_T *pSSP)
{
pSSP->CR1 |= SSP_CR1_LBM_EN;
}
/**
* @brief Disable loopback mode
* @param pSSP : The base of SSP peripheral on the chip
* @return Nothing
* @note Serial input is taken from the serial output (MOSI or MISO) rather
* than the serial input pin
*/
STATIC INLINE void Chip_SSP_DisableLoopBack(LPC_SSP_T *pSSP)
{
pSSP->CR1 &= (~SSP_CR1_LBM_EN) & SSP_CR1_BITMASK;
}
/**
* @brief Get the current status of SSP controller
* @param pSSP : The base of SSP peripheral on the chip
* @param Stat : Type of status, should be :
* - SSP_STAT_TFE
* - SSP_STAT_TNF
* - SSP_STAT_RNE
* - SSP_STAT_RFF
* - SSP_STAT_BSY
* @return SSP controller status, SET or RESET
*/
STATIC INLINE FlagStatus Chip_SSP_GetStatus(LPC_SSP_T *pSSP, SSP_STATUS_T Stat)
{
return (pSSP->SR & Stat) ? SET : RESET;
}
/**
* @brief Get the masked interrupt status
* @param pSSP : The base of SSP peripheral on the chip
* @return SSP Masked Interrupt Status Register value
* @note The return value contains a 1 for each interrupt condition that is asserted and enabled (masked)
*/
STATIC INLINE uint32_t Chip_SSP_GetIntStatus(LPC_SSP_T *pSSP)
{
return pSSP->MIS;
}
/**
* @brief Get the raw interrupt status
* @param pSSP : The base of SSP peripheral on the chip
* @param RawInt : Interrupt condition to be get status, shoud be :
* - SSP_RORRIS
* - SSP_RTRIS
* - SSP_RXRIS
* - SSP_TXRIS
* @return Raw interrupt status corresponding to interrupt condition , SET or RESET
* @note Get the status of each interrupt condition ,regardless of whether or not the interrupt is enabled
*/
STATIC INLINE IntStatus Chip_SSP_GetRawIntStatus(LPC_SSP_T *pSSP, SSP_RAWINTSTATUS_T RawInt)
{
return (pSSP->RIS & RawInt) ? SET : RESET;
}
/**
* @brief Get the number of bits transferred in each frame
* @param pSSP : The base of SSP peripheral on the chip
* @return the number of bits transferred in each frame minus one
* @note The return value is 0x03 -> 0xF corresponding to 4bit -> 16bit transfer
*/
STATIC INLINE uint8_t Chip_SSP_GetDataSize(LPC_SSP_T *pSSP)
{
return SSP_CR0_DSS(pSSP->CR0);
}
/**
* @brief Clear the corresponding interrupt condition(s) in the SSP controller
* @param pSSP : The base of SSP peripheral on the chip
* @param IntClear: Type of cleared interrupt, should be :
* - SSP_RORIC
* - SSP_RTIC
* @return Nothing
* @note Software can clear one or more interrupt condition(s) in the SSP controller
*/
STATIC INLINE void Chip_SSP_ClearIntPending(LPC_SSP_T *pSSP, SSP_INTCLEAR_T IntClear)
{
pSSP->ICR = IntClear;
}
/**
* @brief Enable interrupt for the SSP
* @param pSSP : The base of SSP peripheral on the chip
* @return Nothing
*/
STATIC INLINE void Chip_SSP_Int_Enable(LPC_SSP_T *pSSP)
{
pSSP->IMSC |= SSP_TXIM;
}
/**
* @brief Disable interrupt for the SSP
* @param pSSP : The base of SSP peripheral on the chip
* @return Nothing
*/
STATIC INLINE void Chip_SSP_Int_Disable(LPC_SSP_T *pSSP)
{
pSSP->IMSC &= (~SSP_TXIM);
}
/**
* @brief Get received SSP data
* @param pSSP : The base of SSP peripheral on the chip
* @return SSP 16-bit data received
*/
STATIC INLINE uint16_t Chip_SSP_ReceiveFrame(LPC_SSP_T *pSSP)
{
return (uint16_t) (SSP_DR_BITMASK(pSSP->DR));
}
/**
* @brief Send SSP 16-bit data
* @param pSSP : The base of SSP peripheral on the chip
* @param tx_data : SSP 16-bit data to be transmited
* @return Nothing
*/
STATIC INLINE void Chip_SSP_SendFrame(LPC_SSP_T *pSSP, uint16_t tx_data)
{
pSSP->DR = SSP_DR_BITMASK(tx_data);
}
/**
* @brief Set up output clocks per bit for SSP bus
* @param pSSP : The base of SSP peripheral on the chip
* @param clk_rate fs: The number of prescaler-output clocks per bit on the bus, minus one
* @param prescale : The factor by which the Prescaler divides the SSP peripheral clock PCLK
* @return Nothing
* @note The bit frequency is PCLK / (prescale x[clk_rate+1])
*/
void Chip_SSP_SetClockRate(LPC_SSP_T *pSSP, uint32_t clk_rate, uint32_t prescale);
/**
* @brief Set up the SSP frame format
* @param pSSP : The base of SSP peripheral on the chip
* @param bits : The number of bits transferred in each frame, should be SSP_BITS_4 to SSP_BITS_16
* @param frameFormat : Frame format, should be :
* - SSP_FRAMEFORMAT_SPI
* - SSP_FRAME_FORMAT_TI
* - SSP_FRAMEFORMAT_MICROWIRE
* @param clockMode : Select Clock polarity and Clock phase, should be :
* - SSP_CLOCK_CPHA0_CPOL0
* - SSP_CLOCK_CPHA0_CPOL1
* - SSP_CLOCK_CPHA1_CPOL0
* - SSP_CLOCK_CPHA1_CPOL1
* @return Nothing
* @note Note: The clockFormat is only used in SPI mode
*/
STATIC INLINE void Chip_SSP_SetFormat(LPC_SSP_T *pSSP, uint32_t bits, uint32_t frameFormat, uint32_t clockMode)
{
pSSP->CR0 = (pSSP->CR0 & ~0xFF) | bits | frameFormat | clockMode;
}
/**
* @brief Set the SSP working as master or slave mode
* @param pSSP : The base of SSP peripheral on the chip
* @param mode : Operating mode, should be
* - SSP_MODE_MASTER
* - SSP_MODE_SLAVE
* @return Nothing
*/
STATIC INLINE void Chip_SSP_Set_Mode(LPC_SSP_T *pSSP, uint32_t mode)
{
pSSP->CR1 = (pSSP->CR1 & ~(1 << 2)) | mode;
}
/*
* @brief SSP mode
*/
typedef enum CHIP_SSP_MODE {
SSP_MODE_MASTER = (0 << 2), /**< Master mode */
SSP_MODE_SLAVE = (1u << 2), /**< Slave mode */
} CHIP_SSP_MODE_T;
/*
* @brief SPI address
*/
typedef struct {
uint8_t port; /*!< Port Number */
uint8_t pin; /*!< Pin number */
} SPI_Address_t;
/*
* @brief SSP data setup structure
*/
typedef struct {
void *tx_data; /*!< Pointer to transmit data */
uint32_t tx_cnt; /*!< Transmit counter */
void *rx_data; /*!< Pointer to transmit data */
uint32_t rx_cnt; /*!< Receive counter */
uint32_t length; /*!< Length of transfer data */
} Chip_SSP_DATA_SETUP_T;
/** SSP configuration parameter defines */
/** Clock phase control bit */
#define SSP_CPHA_FIRST SSP_CR0_CPHA_FIRST
#define SSP_CPHA_SECOND SSP_CR0_CPHA_SECOND
/** Clock polarity control bit */
/* There's no bug here!!!
* - If bit[6] in SSPnCR0 is 0: SSP controller maintains the bus clock low between frames.
* That means the active clock is in HI state.
* - If bit[6] in SSPnCR0 is 1 (SSP_CR0_CPOL_HI): SSP controller maintains the bus clock
* high between frames. That means the active clock is in LO state.
*/
#define SSP_CPOL_HI SSP_CR0_CPOL_LO
#define SSP_CPOL_LO SSP_CR0_CPOL_HI
/** SSP master mode enable */
#define SSP_SLAVE_MODE SSP_CR1_SLAVE_EN
#define SSP_MASTER_MODE SSP_CR1_MASTER_EN
/**
* @brief Clean all data in RX FIFO of SSP
* @param pSSP : The base SSP peripheral on the chip
* @return Nothing
*/
void Chip_SSP_Int_FlushData(LPC_SSP_T *pSSP);
/**
* @brief SSP Interrupt Read/Write with 8-bit frame width
* @param pSSP : The base SSP peripheral on the chip
* @param xf_setup : Pointer to a SSP_DATA_SETUP_T structure that contains specified
* information about transmit/receive data configuration
* @return SUCCESS or ERROR
*/
Status Chip_SSP_Int_RWFrames8Bits(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup);
/**
* @brief SSP Interrupt Read/Write with 16-bit frame width
* @param pSSP : The base SSP peripheral on the chip
* @param xf_setup : Pointer to a SSP_DATA_SETUP_T structure that contains specified
* information about transmit/receive data configuration
* @return SUCCESS or ERROR
*/
Status Chip_SSP_Int_RWFrames16Bits(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup);
/**
* @brief SSP Polling Read/Write in blocking mode
* @param pSSP : The base SSP peripheral on the chip
* @param xf_setup : Pointer to a SSP_DATA_SETUP_T structure that contains specified
* information about transmit/receive data configuration
* @return Actual data length has been transferred
* @note
* This function can be used in both master and slave mode. It starts with writing phase and after that,
* a reading phase is generated to read any data available in RX_FIFO. All needed information is prepared
* through xf_setup param.
*/
uint32_t Chip_SSP_RWFrames_Blocking(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup);
/**
* @brief SSP Polling Write in blocking mode
* @param pSSP : The base SSP peripheral on the chip
* @param buffer : Buffer address
* @param buffer_len : Buffer length
* @return Actual data length has been transferred
* @note
* This function can be used in both master and slave mode. First, a writing operation will send
* the needed data. After that, a dummy reading operation is generated to clear data buffer
*/
uint32_t Chip_SSP_WriteFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len);
/**
* @brief SSP Polling Read in blocking mode
* @param pSSP : The base SSP peripheral on the chip
* @param buffer : Buffer address
* @param buffer_len : The length of buffer
* @return Actual data length has been transferred
* @note
* This function can be used in both master and slave mode. First, a dummy writing operation is generated
* to clear data buffer. After that, a reading operation will receive the needed data
*/
uint32_t Chip_SSP_ReadFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len);
/**
* @brief Initialize the SSP
* @param pSSP : The base SSP peripheral on the chip
* @return Nothing
*/
void Chip_SSP_Init(LPC_SSP_T *pSSP);
/**
* @brief Deinitialise the SSP
* @param pSSP : The base of SSP peripheral on the chip
* @return Nothing
* @note The SSP controller is disabled
*/
void Chip_SSP_DeInit(LPC_SSP_T *pSSP);
/**
* @brief Set the SSP operating modes, master or slave
* @param pSSP : The base SSP peripheral on the chip
* @param master : 1 to set master, 0 to set slave
* @return Nothing
*/
void Chip_SSP_SetMaster(LPC_SSP_T *pSSP, bool master);
/**
* @brief Set the clock frequency for SSP interface
* @param pSSP : The base SSP peripheral on the chip
* @param bitRate : The SSP bit rate
* @return Nothing
*/
void Chip_SSP_SetBitRate(LPC_SSP_T *pSSP, uint32_t bitRate);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __SSP_11XX_H_ */

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/*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __SYS_CONFIG_H_
#define __SYS_CONFIG_H_
/* Pick only one. Build for LPC11UXX family */
// #define CHIP_LPC110X
// #define CHIP_LPC11XXLV
// #define CHIP_LPC1125
// #define CHIP_LPC11AXX
// #define CHIP_LPC11CXX
// #define CHIP_LPC11EXX
#define CHIP_LPC11UXX
#endif /* __SYS_CONFIG_H_ */

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/*
* @brief LPC11XX System Control registers and control functions
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __SYSCTL_11XX_H_
#define __SYSCTL_11XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup SYSCTL_11XX CHIP: LPC11xx System Control block driver
* @ingroup CHIP_11XX_Drivers
* @{
*/
/**
* @brief LPC11XX System Control block structure
*/
typedef struct { /*!< SYSCTL Structure */
__IO uint32_t SYSMEMREMAP; /*!< System Memory remap register */
__IO uint32_t PRESETCTRL; /*!< Peripheral reset Control register */
__IO uint32_t SYSPLLCTRL; /*!< System PLL control register */
__I uint32_t SYSPLLSTAT; /*!< System PLL status register */
__IO uint32_t USBPLLCTRL; /*!< USB PLL control register, LPC11UXX only*/
__I uint32_t USBPLLSTAT; /*!< USB PLL status register, LPC11UXX only */
__I uint32_t RESERVED1[2];
__IO uint32_t SYSOSCCTRL; /*!< System Oscillator control register */
__IO uint32_t WDTOSCCTRL; /*!< Watchdog Oscillator control register */
__IO uint32_t IRCCTRL; /*!< IRC control register, not on LPC11UXX and LPC11EXX */
__IO uint32_t LFOSCCTRL; /*!< LF oscillator control, LPC11AXX only */
__IO uint32_t SYSRSTSTAT; /*!< System Reset Status register */
__I uint32_t RESERVED2[3];
__IO uint32_t SYSPLLCLKSEL; /*!< System PLL clock source select register */
__IO uint32_t SYSPLLCLKUEN; /*!< System PLL clock source update enable register*/
__IO uint32_t USBPLLCLKSEL; /*!< USB PLL clock source select register, LPC11UXX only */
__IO uint32_t USBPLLCLKUEN; /*!< USB PLL clock source update enable register, LPC11UXX only */
__I uint32_t RESERVED3[8];
__IO uint32_t MAINCLKSEL; /*!< Main clock source select register */
__IO uint32_t MAINCLKUEN; /*!< Main clock source update enable register */
__IO uint32_t SYSAHBCLKDIV; /*!< System Clock divider register */
__I uint32_t RESERVED4;
__IO uint32_t SYSAHBCLKCTRL; /*!< System clock control register */
__I uint32_t RESERVED5[4];
__IO uint32_t SSP0CLKDIV; /*!< SSP0 clock divider register */
__IO uint32_t USARTCLKDIV; /*!< UART clock divider register */
__IO uint32_t SSP1CLKDIV; /*!< SSP1 clock divider register, not on CHIP_LPC110X, CHIP_LPC11XXLV */
__I uint32_t RESERVED6[8];
__IO uint32_t USBCLKSEL; /*!< USB clock source select register, LPC11UXX only */
__IO uint32_t USBCLKUEN; /*!< USB clock source update enable register, LPC11UXX only */
__IO uint32_t USBCLKDIV; /*!< USB clock source divider register, LPC11UXX only */
__I uint32_t RESERVED7;
__IO uint32_t WDTCLKSEL; /*!< WDT clock source select register, some parts only */
__IO uint32_t WDTCLKUEN; /*!< WDT clock source update enable register, some parts only */
__IO uint32_t WDTCLKDIV; /*!< WDT clock divider register, some parts only */
__I uint32_t RESERVED8;
__IO uint32_t CLKOUTSEL; /*!< Clock out source select register, not on LPC1102/04 */
__IO uint32_t CLKOUTUEN; /*!< Clock out source update enable register, not on LPC1102/04 */
__IO uint32_t CLKOUTDIV; /*!< Clock out divider register, not on LPC1102/04 */
__I uint32_t RESERVED9[5];
__I uint32_t PIOPORCAP[2];/*!< POR captured PIO status registers, index 1 on LPC1102/04 */
__I uint32_t RESERVED10[18];
__IO uint32_t BODCTRL; /*!< Brown Out Detect register */
__IO uint32_t SYSTCKCAL; /*!< System tick counter calibration register */
__I uint32_t RESERVED11[6];
__IO uint32_t IRQLATENCY; /*!< IRQ delay register, on LPC11UXX and LPC11EXX only */
__IO uint32_t NMISRC; /*!< NMI source control register,some parts only */
__IO uint32_t PINTSEL[8]; /*!< GPIO pin interrupt select register 0-7, not on CHIP_LPC110X, CHIP_LPC11XXLV, CHIP_LPC11CXX */
__IO uint32_t USBCLKCTRL; /*!< USB clock control register, LPC11UXX only */
__I uint32_t USBCLKST; /*!< USB clock status register, LPC11UXX only */
__I uint32_t RESERVED12[24];
__IO uint32_t STARTAPRP0; /*!< Start loigc 0 interrupt wake up enable register 0, on CHIP_LPC110X, CHIP_LPC11XXLV, CHIP_LPC11CXX */
__IO uint32_t STARTERP0; /*!< Start loigc signal enable register 0, not on LPC11AXX */
__IO uint32_t STARTRSRP0CLR; /*!< Start loigc reset register 0, on CHIP_LPC110X, CHIP_LPC11XXLV, CHIP_LPC11CXX */
__IO uint32_t STARTSRP0; /*!< Start loigc status register 0, on CHIP_LPC110X, CHIP_LPC11XXLV, CHIP_LPC11CXX */
__I uint32_t RESERVED13;
__IO uint32_t STARTERP1; /*!< Start logic 1 interrupt wake up enable register 1, on LPC11UXX and LPC11EXX only */
__I uint32_t RESERVED14[6];
__IO uint32_t PDSLEEPCFG; /*!< Power down states in deep sleep mode register, not on LPC11AXX */
__IO uint32_t PDWAKECFG; /*!< Power down states in wake up from deep sleep register, not on LPC11AXX */
__IO uint32_t PDRUNCFG; /*!< Power configuration register*/
__I uint32_t RESERVED15[110];
__I uint32_t DEVICEID; /*!< Device ID register */
} LPC_SYSCTL_T;
/**
* System memory remap modes used to remap interrupt vectors
*/
typedef enum CHIP_SYSCTL_BOOT_MODE_REMAP {
REMAP_BOOT_LOADER_MODE, /*!< Interrupt vectors are re-mapped to Boot ROM */
REMAP_USER_RAM_MODE, /*!< Interrupt vectors are re-mapped to Static RAM */
REMAP_USER_FLASH_MODE /*!< Interrupt vectors are not re-mapped and reside in Flash */
} CHIP_SYSCTL_BOOT_MODE_REMAP_T;
/**
* @brief Re-map interrupt vectors
* @param remap : system memory map value
* @return Nothing
*/
STATIC INLINE void Chip_SYSCTL_Map(CHIP_SYSCTL_BOOT_MODE_REMAP_T remap)
{
LPC_SYSCTL->SYSMEMREMAP = (uint32_t) remap;
}
/**
* Peripheral reset identifiers, not available on all devices
*/
typedef enum {
RESET_SSP0, /*!< SSP0 reset control */
RESET_I2C0, /*!< I2C0 reset control */
RESET_SSP1, /*!< SSP1 reset control */
#if !defined(CHIP_LPC1125)
RESET_CAN0, /*!< CAN0 reset control */
RESET_UART0, /*!< UART0 reset control */
RESET_TIMER0_16, /*!< 16-bit Timer 0 reset control */
RESET_TIMER1_16, /*!< 16-bit Timer 1 reset control */
RESET_TIMER0_32, /*!< 32-bit Timer 0 reset control */
RESET_TIMER1_32, /*!< 32-bit Timer 1 reset control */
RESET_ACMP, /*!< Analog comparator reset control */
RESET_DAC0, /*!< DAC reset control */
RESET_ADC0 /*!< ADC reset control */
#endif
} CHIP_SYSCTL_PERIPH_RESET_T;
/**
* @brief Assert reset for a peripheral
* @param periph : Peripheral to assert reset for
* @return Nothing
* @note The peripheral will stay in reset until reset is de-asserted. Call
* Chip_SYSCTL_DeassertPeriphReset() to de-assert the reset.
*/
STATIC INLINE void Chip_SYSCTL_AssertPeriphReset(CHIP_SYSCTL_PERIPH_RESET_T periph)
{
LPC_SYSCTL->PRESETCTRL &= ~(1 << (uint32_t) periph);
}
/**
* @brief De-assert reset for a peripheral
* @param periph : Peripheral to de-assert reset for
* @return Nothing
*/
STATIC INLINE void Chip_SYSCTL_DeassertPeriphReset(CHIP_SYSCTL_PERIPH_RESET_T periph)
{
LPC_SYSCTL->PRESETCTRL |= (1 << (uint32_t) periph);
}
/**
* @brief Resets a peripheral
* @param periph : Peripheral to reset
* @return Nothing
*/
STATIC INLINE void Chip_SYSCTL_PeriphReset(CHIP_SYSCTL_PERIPH_RESET_T periph)
{
Chip_SYSCTL_AssertPeriphReset(periph);
Chip_SYSCTL_DeassertPeriphReset(periph);
}
/**
* System reset status
*/
#define SYSCTL_RST_POR (1 << 0) /*!< POR reset status */
#define SYSCTL_RST_EXTRST (1 << 1) /*!< External reset status */
#define SYSCTL_RST_WDT (1 << 2) /*!< Watchdog reset status */
#define SYSCTL_RST_BOD (1 << 3) /*!< Brown-out detect reset status */
#define SYSCTL_RST_SYSRST (1 << 4) /*!< software system reset status */
/**
* Non-Maskable Interrupt Enable/Disable value
*/
#define SYSCTL_NMISRC_ENABLE ((uint32_t) 1 << 31) /*!< Enable the Non-Maskable Interrupt (NMI) source */
/**
* @brief Get system reset status
* @return An Or'ed value of SYSCTL_RST_*
* @note This function returns the detected reset source(s).
*/
STATIC INLINE uint32_t Chip_SYSCTL_GetSystemRSTStatus(void)
{
return LPC_SYSCTL->SYSRSTSTAT;
}
/**
* @brief Clear system reset status
* @param reset : An Or'ed value of SYSCTL_RST_* status to clear
* @return Nothing
* @note This function returns the detected reset source(s).
*/
STATIC INLINE void Chip_SYSCTL_ClearSystemRSTStatus(uint32_t reset)
{
LPC_SYSCTL->SYSRSTSTAT = reset;
}
/**
* @brief Read POR captured PIO status
* @param index : POR register index, 0 or 1
* @return captured POR PIO status
* @note Some devices only support index 0.
*/
STATIC INLINE uint32_t Chip_SYSCTL_GetPORPIOStatus(int index)
{
return LPC_SYSCTL->PIOPORCAP[index];
}
/**
* Brown-out detector reset level
*/
typedef enum CHIP_SYSCTL_BODRSTLVL {
#if defined(CHIP_LPC11CXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX) || defined(CHIP_LPC11XXLV) || \
defined(CHIP_LPC1125)
SYSCTL_BODRSTLVL_1_46V, /*!< Brown-out reset at 1.46v */
#else
SYSCTL_BODRSTLVL_RESERVED1, /*!< Only possible value for LPC11A/02/XXLV */
#endif
#if defined(CHIP_LPC11XXLV)
SYSCTL_BODRSTLVL_RESERVED1,
SYSCTL_BODRSTLVL_RESERVED2,
SYSCTL_BODRSTLVL_RESERVED3,
#elif defined(CHIP_LPC11AXX)
SYSCTL_BODRSTLVL_RESERVED2,
SYSCTL_BODRSTLVL_2_52V, /*!< Brown-out reset at 2.52v */
SYSCTL_BODRSTLVL_2_80V, /*!< Brown-out reset at 2.80v */
#else
SYSCTL_BODRSTLVL_2_06V, /*!< Brown-out reset at 2.06v */
SYSCTL_BODRSTLVL_2_35V, /*!< Brown-out reset at 2.35v */
SYSCTL_BODRSTLVL_2_63V, /*!< Brown-out reset at 2.63v */
#endif
} CHIP_SYSCTL_BODRSTLVL_T;
/**
* Brown-out detector interrupt level
*/
typedef enum CHIP_SYSCTL_BODRINTVAL {
SYSCTL_BODINTVAL_RESERVED1,
#if defined(CHIP_LPC110X) || defined(CHIP_LPC11CXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX) || \
defined(CHIP_LPC1125)
SYSCTL_BODINTVAL_2_22V, /*!< Brown-out interrupt at 2.22v */
SYSCTL_BODINTVAL_2_52V, /*!< Brown-out interrupt at 2.52v */
SYSCTL_BODINTVAL_2_80V, /*!< Brown-out interrupt at 2.8v */
#endif
} CHIP_SYSCTL_BODRINTVAL_T;
/**
* @brief Set brown-out detection interrupt and reset levels
* @param rstlvl : Brown-out detector reset level
* @param intlvl : Brown-out interrupt level
* @return Nothing
* @note Brown-out detection reset will be disabled upon exiting this function.
* Use Chip_SYSCTL_EnableBODReset() to re-enable.
*/
STATIC INLINE void Chip_SYSCTL_SetBODLevels(CHIP_SYSCTL_BODRSTLVL_T rstlvl,
CHIP_SYSCTL_BODRINTVAL_T intlvl)
{
LPC_SYSCTL->BODCTRL = ((uint32_t) rstlvl) | (((uint32_t) intlvl) << 2);
}
#if defined(CHIP_LPC11AXX)
/**
* @brief Returns brown-out detection interrupt status
* @return true if the BOD interrupt is pending, otherwise false
*/
STATIC INLINE bool Chip_SYSCTL_GetBODIntStatus(void)
{
return (bool) ((LPC_SYSCTL->BODCTRL & (1 << 6)) != 0);
}
#else
/**
* @brief Enable brown-out detection reset
* @return Nothing
*/
STATIC INLINE void Chip_SYSCTL_EnableBODReset(void)
{
LPC_SYSCTL->BODCTRL |= (1 << 4);
}
/**
* @brief Disable brown-out detection reset
* @return Nothing
*/
STATIC INLINE void Chip_SYSCTL_DisableBODReset(void)
{
LPC_SYSCTL->BODCTRL &= ~(1 << 4);
}
#endif
/**
* @brief Set System tick timer calibration value
* @param sysCalVal : System tick timer calibration value
* @return Nothing
*/
STATIC INLINE void Chip_SYSCTL_SetSYSTCKCAL(uint32_t sysCalVal)
{
LPC_SYSCTL->SYSTCKCAL = sysCalVal;
}
#if defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX) || defined(CHIP_LPC1125)
/**
* @brief Set System IRQ latency
* @param latency : Latency in clock ticks
* @return Nothing
* @note Sets the IRQ latency, a value between 0 and 255 clocks. Lower
* values allow better latency.
*/
STATIC INLINE void Chip_SYSCTL_SetIRQLatency(uint32_t latency)
{
LPC_SYSCTL->IRQLATENCY = latency;
}
/**
* @brief Get System IRQ latency
* @return Latency in clock ticks
*/
STATIC INLINE uint32_t Chip_SYSCTL_GetIRQLatency(void)
{
return LPC_SYSCTL->IRQLATENCY;
}
#endif
#if defined(CHIP_LPC11AXX) || defined(CHIP_LPC11CXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX) || \
defined(CHIP_LPC1125)
/**
* @brief Set source for non-maskable interrupt (NMI)
* @param intsrc : IRQ number to assign to the NMI
* @return Nothing
* @note The NMI source will be disabled upon exiting this function. use the
* Chip_SYSCTL_EnableNMISource() function to enable the NMI source.
*/
STATIC INLINE void Chip_SYSCTL_SetNMISource(uint32_t intsrc)
{
LPC_SYSCTL->NMISRC = intsrc;
}
/**
* @brief Enable interrupt used for NMI source
* @return Nothing
*/
STATIC INLINE void Chip_SYSCTL_EnableNMISource(void)
{
LPC_SYSCTL->NMISRC |= SYSCTL_NMISRC_ENABLE;
}
/**
* @brief Disable interrupt used for NMI source
* @return Nothing
*/
STATIC INLINE void Chip_SYSCTL_DisableNMISource(void)
{
LPC_SYSCTL->NMISRC &= ~(SYSCTL_NMISRC_ENABLE);
}
#endif
#if defined(CHIP_LPC11AXX)
/**
* @brief Setup a pin source for the pin interrupts (0-7)
* @param intno : IRQ number
* @param port : port number 0/1)
* @param pin : pin number (0->31)
* @return Nothing
*/
STATIC INLINE void Chip_SYSCTL_SetPinInterrupt(uint32_t intno, uint8_t port, uint8_t pin)
{
LPC_SYSCTL->PINTSEL[intno] = (uint32_t) ((port << 5) | pin);
}
#elif defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX)
/**
* @brief Setup a pin source for the pin interrupts (0-7)
* @param intno : IRQ number
* @param port : port number 0/1)
* @param pin : pin number (0->23 for GPIO Port 0 and 0->31 for GPIO Port 1)
* @return Nothing
*/
STATIC INLINE void Chip_SYSCTL_SetPinInterrupt(uint32_t intno, uint8_t port, uint8_t pin)
{
/* Works for PIO0_0-23 and PIO0_0-31 */
LPC_SYSCTL->PINTSEL[intno] = (uint32_t) (port * 24 + pin);
}
#endif
#if defined(CHIP_LPC11UXX)
/**
* @brief Setup USB clock control
* @param ap_clk : USB need_clock signal control (0 or 1)
* @param pol_clk : USB need_clock polarity for triggering the USB wake-up interrupt (0 or 1)
* @return Nothing
* @note See the USBCLKCTRL register in the user manual for these settings.
*/
STATIC INLINE void Chip_SYSCTL_SetUSBCLKCTRL(uint32_t ap_clk, uint32_t pol_clk)
{
LPC_SYSCTL->USBCLKCTRL = ap_clk | (pol_clk << 1);
}
/**
* @brief Returns the status of the USB need_clock signal
* @return true if USB need_clock statis is high, otherwise false
*/
STATIC INLINE bool Chip_SYSCTL_GetUSBCLKStatus(void)
{
return (bool) ((LPC_SYSCTL->USBCLKST & 0x1) != 0);
}
#endif
#if defined(CHIP_LPC110X) || defined(CHIP_LPC11XXLV) || defined(CHIP_LPC11CXX) || defined(CHIP_LPC1125)
/**
* @brief Set edge for PIO start logic
* @param pin : PIO pin number
* @param edge : 0 for falling edge, 1 for rising edge
* @return Nothing
* @note Different devices support different pins, see the user manual for supported pins.
*/
STATIC INLINE void Chip_SYSCTL_SetStartPin(uint32_t pin, uint32_t edge)
{
if (edge) {
LPC_SYSCTL->STARTAPRP0 |= (1 << pin);
}
else {
LPC_SYSCTL->STARTAPRP0 &= ~(1 << pin);
}
}
/**
* @brief Enable PIO start logic for a pin
* @param pin : PIO pin number
* @return Nothing
* @note Different devices support different pins, see the user manual for supported pins.
*/
STATIC INLINE void Chip_SYSCTL_EnableStartPin(uint32_t pin)
{
LPC_SYSCTL->STARTERP0 |= (1 << pin);
}
/**
* @brief Disable PIO start logic for a pin
* @param pin : PIO pin number
* @return Nothing
* @note Different devices support different pins, see the user manual for supported pins.
*/
STATIC INLINE void Chip_SYSCTL_DisableStartPin(uint32_t pin)
{
LPC_SYSCTL->STARTERP0 &= ~(1 << pin);
}
/**
* @brief Clear PIO start logic state
* @param pin : PIO pin number
* @return Nothing
* @note Different devices support different pins, see the user manual for supported pins.
*/
STATIC INLINE void Chip_SYSCTL_ResetStartPin(uint32_t pin)
{
LPC_SYSCTL->STARTRSRP0CLR = (1 << pin);
}
/**
* @brief Returns status of pin wakeup
* @param pin : PIO pin number
* @return true if a pin start signal is pending, otherwise false
* @note Different devices support different pins, see the user manual for supported pins.
*/
STATIC INLINE bool Chip_SYSCTL_GetStartPinStatus(uint32_t pin)
{
return (bool) ((LPC_SYSCTL->STARTSRP0 & (1 << pin)) != 0);
}
#endif
#if defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX)
/**
* @brief Enables a pin's (PINT) wakeup logic
* @param pin : pin number
* @return Nothing
* @note Different devices support different pins, see the user manual for supported pins.
*/
STATIC INLINE void Chip_SYSCTL_EnablePINTWakeup(uint32_t pin)
{
LPC_SYSCTL->STARTERP0 |= (1 << pin);
}
/**
* @brief Disables a pin's (PINT) wakeup logic
* @param pin : pin number
* @return Nothing
* @note Different devices support different pins, see the user manual for supported pins.
*/
STATIC INLINE void Chip_SYSCTL_DisablePINTWakeup(uint32_t pin)
{
LPC_SYSCTL->STARTERP0 &= ~(1 << pin);
}
/**
* Peripheral interrupt wakeup events, LPC11E/Uxx only
*/
#define SYSCTL_WAKEUP_WWDTINT (1 << 12) /*!< WWDT interrupt wake-up */
#define SYSCTL_WAKEUP_BODINT (1 << 13) /*!< Brown Out Detect (BOD) interrupt wake-up */
#define SYSCTL_WAKEUP_USB_WAKEUP (1 << 19) /*!< USB need_clock signal wake-up, LPC11Uxx only */
#define SYSCTL_WAKEUP_GPIOINT0 (1 << 20) /*!< GPIO GROUP0 interrupt wake-up */
#define SYSCTL_WAKEUP_GPIOINT1 (1 << 21) /*!< GPIO GROUP1 interrupt wake-up */
/**
* @brief Enables a peripheral's wakeup logic
* @param periphmask : OR'ed values of SYSCTL_WAKEUP_* for wakeup
* @return Nothing
*/
STATIC INLINE void Chip_SYSCTL_EnablePeriphWakeup(uint32_t periphmask)
{
LPC_SYSCTL->STARTERP1 |= periphmask;
}
/**
* @brief Disables a peripheral's wakeup logic
* @param periphmask : OR'ed values of SYSCTL_WAKEUP_* for wakeup
* @return Nothing
*/
STATIC INLINE void Chip_SYSCTL_DisablePeriphWakeup(uint32_t periphmask)
{
LPC_SYSCTL->STARTERP1 &= ~periphmask;
}
#endif
#if !defined(LPC11AXX)
/**
* Deep sleep setup values
*/
#define SYSCTL_DEEPSLP_BOD_PD (1 << 3) /*!< BOD power-down control in Deep-sleep mode, powered down */
#define SYSCTL_DEEPSLP_WDTOSC_PD (1 << 6) /*!< Watchdog oscillator power control in Deep-sleep, powered down */
#if defined(CHIP_LPC11XXLV)
#define SYSCTL_DEEPSLP_IRCOUT_PD (1 << 0) /*!< IRC oscillator output in Deep-sleep mode, powered down */
#define SYSCTL_DEEPSLP_IRC_PD (1 << 1) /*!< IRC oscillator in Deep-sleep, powered down */
#endif
/**
* @brief Setup deep sleep behaviour for power down
* @param sleepmask : OR'ed values of SYSCTL_DEEPSLP_* values (high to powerdown on deepsleep)
* @return Nothing
* @note This must be setup prior to using deep sleep. See the user manual
****(PDSLEEPCFG register) for more info on setting this up. This function selects
* which peripherals are powered down on deep sleep.
* This function should only be called once with all options for power-down
* in that call.
*/
void Chip_SYSCTL_SetDeepSleepPD(uint32_t sleepmask);
/**
* @brief Returns current deep sleep mask
* @return OR'ed values of SYSCTL_DEEPSLP_* values
* @note A high bit indicates the peripheral will power down on deep sleep.
*/
STATIC INLINE uint32_t Chip_SYSCTL_GetDeepSleepPD(void)
{
return LPC_SYSCTL->PDSLEEPCFG;
}
/**
* Deep sleep to wakeup setup values
*/
#define SYSCTL_SLPWAKE_IRCOUT_PD (1 << 0) /*!< IRC oscillator output wake-up configuration */
#define SYSCTL_SLPWAKE_IRC_PD (1 << 1) /*!< IRC oscillator power-down wake-up configuration */
#define SYSCTL_SLPWAKE_FLASH_PD (1 << 2) /*!< Flash wake-up configuration */
#define SYSCTL_SLPWAKE_BOD_PD (1 << 3) /*!< BOD wake-up configuration */
#define SYSCTL_SLPWAKE_ADC_PD (1 << 4) /*!< ADC wake-up configuration */
#define SYSCTL_SLPWAKE_SYSOSC_PD (1 << 5) /*!< System oscillator wake-up configuration */
#define SYSCTL_SLPWAKE_WDTOSC_PD (1 << 6) /*!< Watchdog oscillator wake-up configuration */
#define SYSCTL_SLPWAKE_SYSPLL_PD (1 << 7) /*!< System PLL wake-up configuration */
#if defined(CHIP_LPC11UXX)
#define SYSCTL_SLPWAKE_USBPLL_PD (1 << 8) /*!< USB PLL wake-up configuration */
#define SYSCTL_SLPWAKE_USBPAD_PD (1 << 10) /*!< USB transceiver wake-up configuration */
#endif
/**
* @brief Setup wakeup behaviour from deep sleep
* @param wakeupmask : OR'ed values of SYSCTL_SLPWAKE_* values (high is powered down)
* @return Nothing
* @note This must be setup prior to using deep sleep. See the user manual
* (PDWAKECFG register) for more info on setting this up. This function selects
* which peripherals are powered up on exit from deep sleep.
* This function should only be called once with all options for wakeup
* in that call.
*/
void Chip_SYSCTL_SetWakeup(uint32_t wakeupmask);
/**
* @brief Return current wakeup mask
* @return OR'ed values of SYSCTL_SLPWAKE_* values
* @note A high state indicates the peripehral will powerup on wakeup.
*/
STATIC INLINE uint32_t Chip_SYSCTL_GetWakeup(void)
{
return LPC_SYSCTL->PDWAKECFG;
}
#endif
/**
* Power down configuration values
*/
#define SYSCTL_POWERDOWN_IRCOUT_PD (1 << 0) /*!< IRC oscillator output power down */
#define SYSCTL_POWERDOWN_IRC_PD (1 << 1) /*!< IRC oscillator power-down */
#define SYSCTL_POWERDOWN_FLASH_PD (1 << 2) /*!< Flash power down */
#if !defined(CHIP_LPC11AXX)
#define SYSCTL_POWERDOWN_BOD_PD (1 << 3) /*!< BOD power down */
#endif
#define SYSCTL_POWERDOWN_ADC_PD (1 << 4) /*!< ADC power down */
#define SYSCTL_POWERDOWN_SYSOSC_PD (1 << 5) /*!< System oscillator power down */
#define SYSCTL_POWERDOWN_WDTOSC_PD (1 << 6) /*!< Watchdog oscillator power down */
#define SYSCTL_POWERDOWN_SYSPLL_PD (1 << 7) /*!< System PLL power down */
#if defined(CHIP_LPC11UXX)
#define SYSCTL_POWERDOWN_USBPLL_PD (1 << 8) /*!< USB PLL power-down */
#define SYSCTL_POWERDOWN_USBPAD_PD (1 << 10)/*!< USB transceiver power-down */
#endif
#if defined(CHIP_LPC11AXX)
#define SYSCTL_POWERDOWN_LFOSC_PD (1 << 13) /*!< Low frequency oscillator power-down */
#define SYSCTL_POWERDOWN_DAC_PD (1 << 14) /*!< DAC power-down */
#define SYSCTL_POWERDOWN_TS_PD (1 << 15) /*!< Temperature Sensor power-down */
#define SYSCTL_POWERDOWN_ACOMP_PD (1 << 16) /*!< Analog Comparator power-down */
#endif
/**
* @brief Power down one or more blocks or peripherals
* @param powerdownmask : OR'ed values of SYSCTL_POWERDOWN_* values
* @return Nothing
*/
void Chip_SYSCTL_PowerDown(uint32_t powerdownmask);
/**
* @brief Power up one or more blocks or peripherals
* @param powerupmask : OR'ed values of SYSCTL_POWERDOWN_* values
* @return Nothing
*/
void Chip_SYSCTL_PowerUp(uint32_t powerupmask);
/**
* @brief Get power status
* @return OR'ed values of SYSCTL_POWERDOWN_* values
* @note A high state indicates the peripheral is powered down.
*/
STATIC INLINE uint32_t Chip_SYSCTL_GetPowerStates(void)
{
return LPC_SYSCTL->PDRUNCFG;
}
/**
* @brief Return the device ID
* @return the device ID
*/
STATIC INLINE uint32_t Chip_SYSCTL_GetDeviceID(void)
{
return LPC_SYSCTL->DEVICEID;
}
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*!< __SYSCTL_11XX_H_ */

446
basic-setup/components/u8g2/sys/arm/plain/lpc_chip_11uxx_lib/inc/timer_11xx.h Normal file
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@@ -0,0 +1,446 @@
/*
* @brief LPC11xx 16/32-bit Timer/PWM control functions
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __TIMER_11XX_H_
#define __TIMER_11XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup TIMER_11XX CHIP: LPC11xx 16/32-bit Timer driver
* @ingroup CHIP_11XX_Drivers
* @{
*/
/**
* @brief 32-bit Standard timer register block structure
*/
typedef struct { /*!< TIMERn Structure */
__IO uint32_t IR; /*!< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
__IO uint32_t TCR; /*!< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
__IO uint32_t TC; /*!< Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
__IO uint32_t PR; /*!< Prescale Register. The Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
__IO uint32_t PC; /*!< Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
__IO uint32_t MCR; /*!< Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
__IO uint32_t MR[4]; /*!< Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
__IO uint32_t CCR; /*!< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
__IO uint32_t CR[4]; /*!< Capture Register. CR is loaded with the value of TC when there is an event on the CAPn.0 input. */
__IO uint32_t EMR; /*!< External Match Register. The EMR controls the external match pins MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively). */
__I uint32_t RESERVED0[12];
__IO uint32_t CTCR; /*!< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
__IO uint32_t PWMC;
} LPC_TIMER_T;
/** Macro to clear interrupt pending */
#define TIMER_IR_CLR(n) _BIT(n)
/** Macro for getting a timer match interrupt bit */
#define TIMER_MATCH_INT(n) (_BIT((n) & 0x0F))
/** Macro for getting a capture event interrupt bit */
#define TIMER_CAP_INT(n) (_BIT((((n) & 0x0F) + 4)))
/** Timer/counter enable bit */
#define TIMER_ENABLE ((uint32_t) (1 << 0))
/** Timer/counter reset bit */
#define TIMER_RESET ((uint32_t) (1 << 1))
/** Bit location for interrupt on MRx match, n = 0 to 3 */
#define TIMER_INT_ON_MATCH(n) (_BIT(((n) * 3)))
/** Bit location for reset on MRx match, n = 0 to 3 */
#define TIMER_RESET_ON_MATCH(n) (_BIT((((n) * 3) + 1)))
/** Bit location for stop on MRx match, n = 0 to 3 */
#define TIMER_STOP_ON_MATCH(n) (_BIT((((n) * 3) + 2)))
/** Bit location for CAP.n on CRx rising edge, n = 0 to 3 */
#define TIMER_CAP_RISING(n) (_BIT(((n) * 3)))
/** Bit location for CAP.n on CRx falling edge, n = 0 to 3 */
#define TIMER_CAP_FALLING(n) (_BIT((((n) * 3) + 1)))
/** Bit location for CAP.n on CRx interrupt enable, n = 0 to 3 */
#define TIMER_INT_ON_CAP(n) (_BIT((((n) * 3) + 2)))
/**
* @brief Initialize a timer
* @param pTMR : Pointer to timer IP register address
* @return Nothing
*/
void Chip_TIMER_Init(LPC_TIMER_T *pTMR);
/**
* @brief Shutdown a timer
* @param pTMR : Pointer to timer IP register address
* @return Nothing
*/
void Chip_TIMER_DeInit(LPC_TIMER_T *pTMR);
/**
* @brief Determine if a match interrupt is pending
* @param pTMR : Pointer to timer IP register address
* @param matchnum : Match interrupt number to check
* @return false if the interrupt is not pending, otherwise true
* @note Determine if the match interrupt for the passed timer and match
* counter is pending.
*/
STATIC INLINE bool Chip_TIMER_MatchPending(LPC_TIMER_T *pTMR, int8_t matchnum)
{
return (bool) ((pTMR->IR & TIMER_MATCH_INT(matchnum)) != 0);
}
/**
* @brief Determine if a capture interrupt is pending
* @param pTMR : Pointer to timer IP register address
* @param capnum : Capture interrupt number to check
* @return false if the interrupt is not pending, otherwise true
* @note Determine if the capture interrupt for the passed capture pin is
* pending.
*/
STATIC INLINE bool Chip_TIMER_CapturePending(LPC_TIMER_T *pTMR, int8_t capnum)
{
return (bool) ((pTMR->IR & TIMER_CAP_INT(capnum)) != 0);
}
/**
* @brief Clears a (pending) match interrupt
* @param pTMR : Pointer to timer IP register address
* @param matchnum : Match interrupt number to clear
* @return Nothing
* @note Clears a pending timer match interrupt.
*/
STATIC INLINE void Chip_TIMER_ClearMatch(LPC_TIMER_T *pTMR, int8_t matchnum)
{
pTMR->IR = TIMER_IR_CLR(matchnum);
}
/**
* @brief Clears a (pending) capture interrupt
* @param pTMR : Pointer to timer IP register address
* @param capnum : Capture interrupt number to clear
* @return Nothing
* @note Clears a pending timer capture interrupt.
*/
STATIC INLINE void Chip_TIMER_ClearCapture(LPC_TIMER_T *pTMR, int8_t capnum)
{
pTMR->IR = (0x10 << capnum);
}
/**
* @brief Enables the timer (starts count)
* @param pTMR : Pointer to timer IP register address
* @return Nothing
* @note Enables the timer to start counting.
*/
STATIC INLINE void Chip_TIMER_Enable(LPC_TIMER_T *pTMR)
{
pTMR->TCR |= TIMER_ENABLE;
}
/**
* @brief Disables the timer (stops count)
* @param pTMR : Pointer to timer IP register address
* @return Nothing
* @note Disables the timer to stop counting.
*/
STATIC INLINE void Chip_TIMER_Disable(LPC_TIMER_T *pTMR)
{
pTMR->TCR &= ~TIMER_ENABLE;
}
/**
* @brief Returns the current timer count
* @param pTMR : Pointer to timer IP register address
* @return Current timer terminal count value
* @note Returns the current timer terminal count.
*/
STATIC INLINE uint32_t Chip_TIMER_ReadCount(LPC_TIMER_T *pTMR)
{
return pTMR->TC;
}
/**
* @brief Returns the current prescale count
* @param pTMR : Pointer to timer IP register address
* @return Current timer prescale count value
* @note Returns the current prescale count.
*/
STATIC INLINE uint32_t Chip_TIMER_ReadPrescale(LPC_TIMER_T *pTMR)
{
return pTMR->PC;
}
/**
* @brief Sets the prescaler value
* @param pTMR : Pointer to timer IP register address
* @param prescale : Prescale value to set the prescale register to
* @return Nothing
* @note Sets the prescale count value.
*/
STATIC INLINE void Chip_TIMER_PrescaleSet(LPC_TIMER_T *pTMR, uint32_t prescale)
{
pTMR->PR = prescale;
}
/**
* @brief Sets a timer match value
* @param pTMR : Pointer to timer IP register address
* @param matchnum : Match timer to set match count for
* @param matchval : Match value for the selected match count
* @return Nothing
* @note Sets one of the timer match values.
*/
STATIC INLINE void Chip_TIMER_SetMatch(LPC_TIMER_T *pTMR, int8_t matchnum, uint32_t matchval)
{
pTMR->MR[matchnum] = matchval;
}
/**
* @brief Reads a capture register
* @param pTMR : Pointer to timer IP register address
* @param capnum : Capture register to read
* @return The selected capture register value
* @note Returns the selected capture register value.
*/
STATIC INLINE uint32_t Chip_TIMER_ReadCapture(LPC_TIMER_T *pTMR, int8_t capnum)
{
return pTMR->CR[capnum];
}
/**
* @brief Resets the timer terminal and prescale counts to 0
* @param pTMR : Pointer to timer IP register address
* @return Nothing
*/
void Chip_TIMER_Reset(LPC_TIMER_T *pTMR);
/**
* @brief Enables a match interrupt that fires when the terminal count
* matches the match counter value.
* @param pTMR : Pointer to timer IP register address
* @param matchnum : Match timer, 0 to 3
* @return Nothing
*/
STATIC INLINE void Chip_TIMER_MatchEnableInt(LPC_TIMER_T *pTMR, int8_t matchnum)
{
pTMR->MCR |= TIMER_INT_ON_MATCH(matchnum);
}
/**
* @brief Disables a match interrupt for a match counter.
* @param pTMR : Pointer to timer IP register address
* @param matchnum : Match timer, 0 to 3
* @return Nothing
*/
STATIC INLINE void Chip_TIMER_MatchDisableInt(LPC_TIMER_T *pTMR, int8_t matchnum)
{
pTMR->MCR &= ~TIMER_INT_ON_MATCH(matchnum);
}
/**
* @brief For the specific match counter, enables reset of the terminal count register when a match occurs
* @param pTMR : Pointer to timer IP register address
* @param matchnum : Match timer, 0 to 3
* @return Nothing
*/
STATIC INLINE void Chip_TIMER_ResetOnMatchEnable(LPC_TIMER_T *pTMR, int8_t matchnum)
{
pTMR->MCR |= TIMER_RESET_ON_MATCH(matchnum);
}
/**
* @brief For the specific match counter, disables reset of the terminal count register when a match occurs
* @param pTMR : Pointer to timer IP register address
* @param matchnum : Match timer, 0 to 3
* @return Nothing
*/
STATIC INLINE void Chip_TIMER_ResetOnMatchDisable(LPC_TIMER_T *pTMR, int8_t matchnum)
{
pTMR->MCR &= ~TIMER_RESET_ON_MATCH(matchnum);
}
/**
* @brief Enable a match timer to stop the terminal count when a
* match count equals the terminal count.
* @param pTMR : Pointer to timer IP register address
* @param matchnum : Match timer, 0 to 3
* @return Nothing
*/
STATIC INLINE void Chip_TIMER_StopOnMatchEnable(LPC_TIMER_T *pTMR, int8_t matchnum)
{
pTMR->MCR |= TIMER_STOP_ON_MATCH(matchnum);
}
/**
* @brief Disable stop on match for a match timer. Disables a match timer
* to stop the terminal count when a match count equals the terminal count.
* @param pTMR : Pointer to timer IP register address
* @param matchnum : Match timer, 0 to 3
* @return Nothing
*/
STATIC INLINE void Chip_TIMER_StopOnMatchDisable(LPC_TIMER_T *pTMR, int8_t matchnum)
{
pTMR->MCR &= ~TIMER_STOP_ON_MATCH(matchnum);
}
/**
* @brief Enables capture on on rising edge of selected CAP signal for the
* selected capture register, enables the selected CAPn.capnum signal to load
* the capture register with the terminal coount on a rising edge.
* @param pTMR : Pointer to timer IP register address
* @param capnum : Capture signal/register to use
* @return Nothing
*/
STATIC INLINE void Chip_TIMER_CaptureRisingEdgeEnable(LPC_TIMER_T *pTMR, int8_t capnum)
{
pTMR->CCR |= TIMER_CAP_RISING(capnum);
}
/**
* @brief Disables capture on on rising edge of selected CAP signal. For the
* selected capture register, disables the selected CAPn.capnum signal to load
* the capture register with the terminal coount on a rising edge.
* @param pTMR : Pointer to timer IP register address
* @param capnum : Capture signal/register to use
* @return Nothing
*/
STATIC INLINE void Chip_TIMER_CaptureRisingEdgeDisable(LPC_TIMER_T *pTMR, int8_t capnum)
{
pTMR->CCR &= ~TIMER_CAP_RISING(capnum);
}
/**
* @brief Enables capture on on falling edge of selected CAP signal. For the
* selected capture register, enables the selected CAPn.capnum signal to load
* the capture register with the terminal coount on a falling edge.
* @param pTMR : Pointer to timer IP register address
* @param capnum : Capture signal/register to use
* @return Nothing
*/
STATIC INLINE void Chip_TIMER_CaptureFallingEdgeEnable(LPC_TIMER_T *pTMR, int8_t capnum)
{
pTMR->CCR |= TIMER_CAP_FALLING(capnum);
}
/**
* @brief Disables capture on on falling edge of selected CAP signal. For the
* selected capture register, disables the selected CAPn.capnum signal to load
* the capture register with the terminal coount on a falling edge.
* @param pTMR : Pointer to timer IP register address
* @param capnum : Capture signal/register to use
* @return Nothing
*/
STATIC INLINE void Chip_TIMER_CaptureFallingEdgeDisable(LPC_TIMER_T *pTMR, int8_t capnum)
{
pTMR->CCR &= ~TIMER_CAP_FALLING(capnum);
}
/**
* @brief Enables interrupt on capture of selected CAP signal. For the
* selected capture register, an interrupt will be generated when the enabled
* rising or falling edge on CAPn.capnum is detected.
* @param pTMR : Pointer to timer IP register address
* @param capnum : Capture signal/register to use
* @return Nothing
*/
STATIC INLINE void Chip_TIMER_CaptureEnableInt(LPC_TIMER_T *pTMR, int8_t capnum)
{
pTMR->CCR |= TIMER_INT_ON_CAP(capnum);
}
/**
* @brief Disables interrupt on capture of selected CAP signal
* @param pTMR : Pointer to timer IP register address
* @param capnum : Capture signal/register to use
* @return Nothing
*/
STATIC INLINE void Chip_TIMER_CaptureDisableInt(LPC_TIMER_T *pTMR, int8_t capnum)
{
pTMR->CCR &= ~TIMER_INT_ON_CAP(capnum);
}
/**
* @brief Standard timer initial match pin state and change state
*/
typedef enum IP_TIMER_PIN_MATCH_STATE {
TIMER_EXTMATCH_DO_NOTHING = 0, /*!< Timer match state does nothing on match pin */
TIMER_EXTMATCH_CLEAR = 1, /*!< Timer match state sets match pin low */
TIMER_EXTMATCH_SET = 2, /*!< Timer match state sets match pin high */
TIMER_EXTMATCH_TOGGLE = 3 /*!< Timer match state toggles match pin */
} TIMER_PIN_MATCH_STATE_T;
/**
* @brief Sets external match control (MATn.matchnum) pin control. For the pin
* selected with matchnum, sets the function of the pin that occurs on
* a terminal count match for the match count.
* @param pTMR : Pointer to timer IP register address
* @param initial_state : Initial state of the pin, high(1) or low(0)
* @param matchState : Selects the match state for the pin
* @param matchnum : MATn.matchnum signal to use
* @return Nothing
* @note For the pin selected with matchnum, sets the function of the pin that occurs on
* a terminal count match for the match count.
*/
void Chip_TIMER_ExtMatchControlSet(LPC_TIMER_T *pTMR, int8_t initial_state,
TIMER_PIN_MATCH_STATE_T matchState, int8_t matchnum);
/**
* @brief Standard timer clock and edge for count source
*/
typedef enum IP_TIMER_CAP_SRC_STATE {
TIMER_CAPSRC_RISING_PCLK = 0, /*!< Timer ticks on PCLK rising edge */
TIMER_CAPSRC_RISING_CAPN = 1, /*!< Timer ticks on CAPn.x rising edge */
TIMER_CAPSRC_FALLING_CAPN = 2, /*!< Timer ticks on CAPn.x falling edge */
TIMER_CAPSRC_BOTH_CAPN = 3 /*!< Timer ticks on CAPn.x both edges */
} TIMER_CAP_SRC_STATE_T;
/**
* @brief Sets timer count source and edge with the selected passed from CapSrc.
* If CapSrc selected a CAPn pin, select the specific CAPn pin with the capnum value.
* @param pTMR : Pointer to timer IP register address
* @param capSrc : timer clock source and edge
* @param capnum : CAPn.capnum pin to use (if used)
* @return Nothing
* @note If CapSrc selected a CAPn pin, select the specific CAPn pin with the capnum value.
*/
STATIC INLINE void Chip_TIMER_TIMER_SetCountClockSrc(LPC_TIMER_T *pTMR,
TIMER_CAP_SRC_STATE_T capSrc,
int8_t capnum)
{
pTMR->CTCR = (uint32_t) capSrc | ((uint32_t) capnum) << 2;
}
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __TIMER_11XX_H_ */

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/*
* @brief LPC11xx UART chip driver
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __UART_11XX_H_
#define __UART_11XX_H_
#include "ring_buffer.h"
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup UART_11XX CHIP: LPC11xx UART driver
* @ingroup CHIP_11XX_Drivers
* @{
*/
/**
* @brief USART register block structure
*/
typedef struct { /*!< USARTn Structure */
union {
__IO uint32_t DLL; /*!< Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
__O uint32_t THR; /*!< Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0). */
__I uint32_t RBR; /*!< Receiver Buffer Register. Contains the next received character to be read (DLAB = 0). */
};
union {
__IO uint32_t IER; /*!< Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB = 0). */
__IO uint32_t DLM; /*!< Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1). */
};
union {
__O uint32_t FCR; /*!< FIFO Control Register. Controls UART FIFO usage and modes. */
__I uint32_t IIR; /*!< Interrupt ID Register. Identifies which interrupt(s) are pending. */
};
__IO uint32_t LCR; /*!< Line Control Register. Contains controls for frame formatting and break generation. */
__IO uint32_t MCR; /*!< Modem Control Register. Only present on USART ports with full modem support. */
__I uint32_t LSR; /*!< Line Status Register. Contains flags for transmit and receive status, including line errors. */
__I uint32_t MSR; /*!< Modem Status Register. Only present on USART ports with full modem support. */
__IO uint32_t SCR; /*!< Scratch Pad Register. Eight-bit temporary storage for software. */
__IO uint32_t ACR; /*!< Auto-baud Control Register. Contains controls for the auto-baud feature. */
__IO uint32_t ICR; /*!< IrDA control register (not all UARTS) */
__IO uint32_t FDR; /*!< Fractional Divider Register. Generates a clock input for the baud rate divider. */
__IO uint32_t OSR; /*!< Oversampling Register. Controls the degree of oversampling during each bit time. Only on some UARTS. */
__IO uint32_t TER1; /*!< Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
uint32_t RESERVED0[3];
__IO uint32_t HDEN; /*!< Half-duplex enable Register- only on some UARTs */
__I uint32_t RESERVED1[1];
__IO uint32_t SCICTRL; /*!< Smart card interface control register- only on some UARTs */
__IO uint32_t RS485CTRL; /*!< RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
__IO uint32_t RS485ADRMATCH; /*!< RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
__IO uint32_t RS485DLY; /*!< RS-485/EIA-485 direction control delay. */
union {
__IO uint32_t SYNCCTRL; /*!< Synchronous mode control register. Only on USARTs. */
__I uint32_t FIFOLVL; /*!< FIFO Level register. Provides the current fill levels of the transmit and receive FIFOs. */
};
__IO uint32_t TER2; /*!< Transmit Enable Register. Only on LPC177X_8X UART4 and LPC18XX/43XX USART0/2/3. */
} LPC_USART_T;
/**
* @brief Macro defines for UART Receive Buffer register
*/
#define UART_RBR_MASKBIT (0xFF) /*!< UART Received Buffer mask bit (8 bits) */
/**
* @brief Macro defines for UART Divisor Latch LSB register
*/
#define UART_LOAD_DLL(div) ((div) & 0xFF) /*!< Macro for loading LSB of divisor */
#define UART_DLL_MASKBIT (0xFF) /*!< Divisor latch LSB bit mask */
/**
* @brief Macro defines for UART Divisor Latch MSB register
*/
#define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF) /*!< Macro for loading MSB of divisors */
#define UART_DLM_MASKBIT (0xFF) /*!< Divisor latch MSB bit mask */
/**
* @brief Macro defines for UART Interrupt Enable Register
*/
#define UART_IER_RBRINT (1 << 0) /*!< RBR Interrupt enable */
#define UART_IER_THREINT (1 << 1) /*!< THR Interrupt enable */
#define UART_IER_RLSINT (1 << 2) /*!< RX line status interrupt enable */
#define UART_IER_MSINT (1 << 3) /*!< Modem status interrupt enable - valid for 11xx, 17xx/40xx UART1, 18xx/43xx UART1 only */
#define UART_IER_CTSINT (1 << 7) /*!< CTS signal transition interrupt enable - valid for 17xx/40xx UART1, 18xx/43xx UART1 only */
#define UART_IER_ABEOINT (1 << 8) /*!< Enables the end of auto-baud interrupt */
#define UART_IER_ABTOINT (1 << 9) /*!< Enables the auto-baud time-out interrupt */
#define UART_IER_BITMASK (0x307) /*!< UART interrupt enable register bit mask - valid for 13xx, 17xx/40xx UART0/2/3, 18xx/43xx UART0/2/3 only*/
#define UART1_IER_BITMASK (0x30F) /*!< UART1 interrupt enable register bit mask - valid for 11xx only */
#define UART2_IER_BITMASK (0x38F) /*!< UART2 interrupt enable register bit mask - valid for 17xx/40xx UART1, 18xx/43xx UART1 only */
/**
* @brief Macro defines for UART Interrupt Identification Register
*/
#define UART_IIR_INTSTAT_PEND (1 << 0) /*!< Interrupt pending status - Active low */
#define UART_IIR_FIFO_EN (3 << 6) /*!< These bits are equivalent to FCR[0] */
#define UART_IIR_ABEO_INT (1 << 8) /*!< End of auto-baud interrupt */
#define UART_IIR_ABTO_INT (1 << 9) /*!< Auto-baud time-out interrupt */
#define UART_IIR_BITMASK (0x3CF) /*!< UART interrupt identification register bit mask */
/* Interrupt ID bit definitions */
#define UART_IIR_INTID_MASK (7 << 1) /*!< Interrupt identification: Interrupt ID mask */
#define UART_IIR_INTID_RLS (3 << 1) /*!< Interrupt identification: Receive line interrupt */
#define UART_IIR_INTID_RDA (2 << 1) /*!< Interrupt identification: Receive data available interrupt */
#define UART_IIR_INTID_CTI (6 << 1) /*!< Interrupt identification: Character time-out indicator interrupt */
#define UART_IIR_INTID_THRE (1 << 1) /*!< Interrupt identification: THRE interrupt */
#define UART_IIR_INTID_MODEM (0 << 1) /*!< Interrupt identification: Modem interrupt */
/**
* @brief Macro defines for UART FIFO Control Register
*/
#define UART_FCR_FIFO_EN (1 << 0) /*!< UART FIFO enable */
#define UART_FCR_RX_RS (1 << 1) /*!< UART RX FIFO reset */
#define UART_FCR_TX_RS (1 << 2) /*!< UART TX FIFO reset */
#define UART_FCR_DMAMODE_SEL (1 << 3) /*!< UART DMA mode selection - valid for 17xx/40xx, 18xx/43xx only */
#define UART_FCR_BITMASK (0xCF) /*!< UART FIFO control bit mask */
#define UART_TX_FIFO_SIZE (16)
/* FIFO trigger level bit definitions */
#define UART_FCR_TRG_LEV0 (0) /*!< UART FIFO trigger level 0: 1 character */
#define UART_FCR_TRG_LEV1 (1 << 6) /*!< UART FIFO trigger level 1: 4 character */
#define UART_FCR_TRG_LEV2 (2 << 6) /*!< UART FIFO trigger level 2: 8 character */
#define UART_FCR_TRG_LEV3 (3 << 6) /*!< UART FIFO trigger level 3: 14 character */
/**
* @brief Macro defines for UART Line Control Register
*/
/* UART word length select bit definitions */
#define UART_LCR_WLEN_MASK (3 << 0) /*!< UART word length select bit mask */
#define UART_LCR_WLEN5 (0 << 0) /*!< UART word length select: 5 bit data mode */
#define UART_LCR_WLEN6 (1 << 0) /*!< UART word length select: 6 bit data mode */
#define UART_LCR_WLEN7 (2 << 0) /*!< UART word length select: 7 bit data mode */
#define UART_LCR_WLEN8 (3 << 0) /*!< UART word length select: 8 bit data mode */
/* UART Stop bit select bit definitions */
#define UART_LCR_SBS_MASK (1 << 2) /*!< UART stop bit select: bit mask */
#define UART_LCR_SBS_1BIT (0 << 2) /*!< UART stop bit select: 1 stop bit */
#define UART_LCR_SBS_2BIT (1 << 2) /*!< UART stop bit select: 2 stop bits (in 5 bit data mode, 1.5 stop bits) */
/* UART Parity enable bit definitions */
#define UART_LCR_PARITY_EN (1 << 3) /*!< UART Parity Enable */
#define UART_LCR_PARITY_DIS (0 << 3) /*!< UART Parity Disable */
#define UART_LCR_PARITY_ODD (0 << 4) /*!< UART Parity select: Odd parity */
#define UART_LCR_PARITY_EVEN (1 << 4) /*!< UART Parity select: Even parity */
#define UART_LCR_PARITY_F_1 (2 << 4) /*!< UART Parity select: Forced 1 stick parity */
#define UART_LCR_PARITY_F_0 (3 << 4) /*!< UART Parity select: Forced 0 stick parity */
#define UART_LCR_BREAK_EN (1 << 6) /*!< UART Break transmission enable */
#define UART_LCR_DLAB_EN (1 << 7) /*!< UART Divisor Latches Access bit enable */
#define UART_LCR_BITMASK (0xFF) /*!< UART line control bit mask */
/**
* @brief Macro defines for UART Modem Control Register
*/
#define UART_MCR_DTR_CTRL (1 << 0) /*!< Source for modem output pin DTR */
#define UART_MCR_RTS_CTRL (1 << 1) /*!< Source for modem output pin RTS */
#define UART_MCR_LOOPB_EN (1 << 4) /*!< Loop back mode select */
#define UART_MCR_AUTO_RTS_EN (1 << 6) /*!< Enable Auto RTS flow-control */
#define UART_MCR_AUTO_CTS_EN (1 << 7) /*!< Enable Auto CTS flow-control */
#define UART_MCR_BITMASK (0xD3) /*!< UART bit mask value */
/**
* @brief Macro defines for UART Line Status Register
*/
#define UART_LSR_RDR (1 << 0) /*!< Line status: Receive data ready */
#define UART_LSR_OE (1 << 1) /*!< Line status: Overrun error */
#define UART_LSR_PE (1 << 2) /*!< Line status: Parity error */
#define UART_LSR_FE (1 << 3) /*!< Line status: Framing error */
#define UART_LSR_BI (1 << 4) /*!< Line status: Break interrupt */
#define UART_LSR_THRE (1 << 5) /*!< Line status: Transmit holding register empty */
#define UART_LSR_TEMT (1 << 6) /*!< Line status: Transmitter empty */
#define UART_LSR_RXFE (1 << 7) /*!< Line status: Error in RX FIFO */
#define UART_LSR_TXFE (1 << 8) /*!< Line status: Error in RX FIFO */
#define UART_LSR_BITMASK (0xFF) /*!< UART Line status bit mask */
#define UART1_LSR_BITMASK (0x1FF) /*!< UART1 Line status bit mask - valid for 11xx, 18xx/43xx UART0/2/3 only */
/**
* @brief Macro defines for UART Modem Status Register
*/
#define UART_MSR_DELTA_CTS (1 << 0) /*!< Modem status: State change of input CTS */
#define UART_MSR_DELTA_DSR (1 << 1) /*!< Modem status: State change of input DSR */
#define UART_MSR_LO2HI_RI (1 << 2) /*!< Modem status: Low to high transition of input RI */
#define UART_MSR_DELTA_DCD (1 << 3) /*!< Modem status: State change of input DCD */
#define UART_MSR_CTS (1 << 4) /*!< Modem status: Clear To Send State */
#define UART_MSR_DSR (1 << 5) /*!< Modem status: Data Set Ready State */
#define UART_MSR_RI (1 << 6) /*!< Modem status: Ring Indicator State */
#define UART_MSR_DCD (1 << 7) /*!< Modem status: Data Carrier Detect State */
#define UART_MSR_BITMASK (0xFF) /*!< Modem status: MSR register bit-mask value */
/**
* @brief Macro defines for UART Auto baudrate control register
*/
#define UART_ACR_START (1 << 0) /*!< UART Auto-baud start */
#define UART_ACR_MODE (1 << 1) /*!< UART Auto baudrate Mode 1 */
#define UART_ACR_AUTO_RESTART (1 << 2) /*!< UART Auto baudrate restart */
#define UART_ACR_ABEOINT_CLR (1 << 8) /*!< UART End of auto-baud interrupt clear */
#define UART_ACR_ABTOINT_CLR (1 << 9) /*!< UART Auto-baud time-out interrupt clear */
#define UART_ACR_BITMASK (0x307) /*!< UART Auto Baudrate register bit mask */
/**
* @brief Macro defines for UART RS485 Control register
*/
#define UART_RS485CTRL_NMM_EN (1 << 0) /*!< RS-485/EIA-485 Normal Multi-drop Mode (NMM) is disabled */
#define UART_RS485CTRL_RX_DIS (1 << 1) /*!< The receiver is disabled */
#define UART_RS485CTRL_AADEN (1 << 2) /*!< Auto Address Detect (AAD) is enabled */
#define UART_RS485CTRL_SEL_DTR (1 << 3) /*!< If direction control is enabled (bit DCTRL = 1), pin DTR is
used for direction control */
#define UART_RS485CTRL_DCTRL_EN (1 << 4) /*!< Enable Auto Direction Control */
#define UART_RS485CTRL_OINV_1 (1 << 5) /*!< This bit reverses the polarity of the direction
control signal on the RTS (or DTR) pin. The direction control pin
will be driven to logic "1" when the transmitter has data to be sent */
#define UART_RS485CTRL_BITMASK (0x3F) /*!< RS485 control bit-mask value */
/**
* @brief Macro defines for UART IrDA Control Register - valid for 11xx, 17xx/40xx UART0/2/3, 18xx/43xx UART3 only
*/
#define UART_ICR_IRDAEN (1 << 0) /*!< IrDA mode enable */
#define UART_ICR_IRDAINV (1 << 1) /*!< IrDA serial input inverted */
#define UART_ICR_FIXPULSE_EN (1 << 2) /*!< IrDA fixed pulse width mode */
#define UART_ICR_PULSEDIV(n) ((n & 0x07) << 3) /*!< PulseDiv - Configures the pulse when FixPulseEn = 1 */
#define UART_ICR_BITMASK (0x3F) /*!< UART IRDA bit mask */
/**
* @brief Macro defines for UART half duplex register - ????
*/
#define UART_HDEN_HDEN ((1 << 0)) /*!< enable half-duplex mode*/
/**
* @brief Macro defines for UART Smart card interface Control Register - valid for 11xx, 18xx/43xx UART0/2/3 only
*/
#define UART_SCICTRL_SCIEN (1 << 0) /*!< enable asynchronous half-duplex smart card interface*/
#define UART_SCICTRL_NACKDIS (1 << 1) /*!< NACK response is inhibited*/
#define UART_SCICTRL_PROTSEL_T1 (1 << 2) /*!< ISO7816-3 protocol T1 is selected*/
#define UART_SCICTRL_TXRETRY(n) ((n & 0x07) << 5) /*!< number of retransmission*/
#define UART_SCICTRL_GUARDTIME(n) ((n & 0xFF) << 8) /*!< Extra guard time*/
/**
* @brief Macro defines for UART Fractional Divider Register
*/
#define UART_FDR_DIVADDVAL(n) (n & 0x0F) /*!< Baud-rate generation pre-scaler divisor */
#define UART_FDR_MULVAL(n) ((n << 4) & 0xF0) /*!< Baud-rate pre-scaler multiplier value */
#define UART_FDR_BITMASK (0xFF) /*!< UART Fractional Divider register bit mask */
/**
* @brief Macro defines for UART Tx Enable Register
*/
#define UART_TER1_TXEN (1 << 7) /*!< Transmit enable bit - valid for 11xx, 13xx, 17xx/40xx only */
#define UART_TER2_TXEN (1 << 0) /*!< Transmit enable bit - valid for 18xx/43xx only */
/**
* @brief Macro defines for UART Synchronous Control Register - 11xx, 18xx/43xx UART0/2/3 only
*/
#define UART_SYNCCTRL_SYNC (1 << 0) /*!< enable synchronous mode*/
#define UART_SYNCCTRL_CSRC_MASTER (1 << 1) /*!< synchronous master mode*/
#define UART_SYNCCTRL_FES (1 << 2) /*!< sample on falling edge*/
#define UART_SYNCCTRL_TSBYPASS (1 << 3) /*!< to be defined*/
#define UART_SYNCCTRL_CSCEN (1 << 4) /*!< Continuous running clock enable (master mode only)*/
#define UART_SYNCCTRL_STARTSTOPDISABLE (1 << 5) /*!< Do not send start/stop bit*/
#define UART_SYNCCTRL_CCCLR (1 << 6) /*!< stop continuous clock*/
/**
* @brief Enable transmission on UART TxD pin
* @param pUART : Pointer to selected pUART peripheral
* @return Nothing
*/
STATIC INLINE void Chip_UART_TXEnable(LPC_USART_T *pUART)
{
pUART->TER1 = UART_TER1_TXEN;
}
/**
* @brief Disable transmission on UART TxD pin
* @param pUART : Pointer to selected pUART peripheral
* @return Nothing
*/
STATIC INLINE void Chip_UART_TXDisable(LPC_USART_T *pUART)
{
pUART->TER1 = 0;
}
/**
* @brief Transmit a single data byte through the UART peripheral
* @param pUART : Pointer to selected UART peripheral
* @param data : Byte to transmit
* @return Nothing
* @note This function attempts to place a byte into the UART transmit
* FIFO or transmit hold register regard regardless of UART state
*/
STATIC INLINE void Chip_UART_SendByte(LPC_USART_T *pUART, uint8_t data)
{
pUART->THR = (uint32_t) data;
}
/**
* @brief Read a single byte data from the UART peripheral
* @param pUART : Pointer to selected UART peripheral
* @return A single byte of data read
* @note This function reads a byte from the UART receive FIFO or
* receive hold register regard regardless of UART state. The
* FIFO status should be read first prior to using this function
*/
STATIC INLINE uint8_t Chip_UART_ReadByte(LPC_USART_T *pUART)
{
return (uint8_t) (pUART->RBR & UART_RBR_MASKBIT);
}
/**
* @brief Enable UART interrupts
* @param pUART : Pointer to selected UART peripheral
* @param intMask : OR'ed Interrupts to enable in the Interrupt Enable Register (IER)
* @return Nothing
* @note Use an OR'ed value of UART_IER_* definitions with this function
* to enable specific UART interrupts. The Divisor Latch Access Bit
* (DLAB) in LCR must be cleared in order to access the IER register.
* This function doesn't alter the DLAB state
*/
STATIC INLINE void Chip_UART_IntEnable(LPC_USART_T *pUART, uint32_t intMask)
{
pUART->IER |= intMask;
}
/**
* @brief Disable UART interrupts
* @param pUART : Pointer to selected UART peripheral
* @param intMask : OR'ed Interrupts to disable in the Interrupt Enable Register (IER)
* @return Nothing
* @note Use an OR'ed value of UART_IER_* definitions with this function
* to disable specific UART interrupts. The Divisor Latch Access Bit
* (DLAB) in LCR must be cleared in order to access the IER register.
* This function doesn't alter the DLAB state
*/
STATIC INLINE void Chip_UART_IntDisable(LPC_USART_T *pUART, uint32_t intMask)
{
pUART->IER &= ~intMask;
}
/**
* @brief Returns UART interrupts that are enabled
* @param pUART : Pointer to selected UART peripheral
* @return Returns the enabled UART interrupts
* @note Use an OR'ed value of UART_IER_* definitions with this function
* to determine which interrupts are enabled. You can check
* for multiple enabled bits if needed.
*/
STATIC INLINE uint32_t Chip_UART_GetIntsEnabled(LPC_USART_T *pUART)
{
return pUART->IER;
}
/**
* @brief Read the Interrupt Identification Register (IIR)
* @param pUART : Pointer to selected UART peripheral
* @return Current pending interrupt status per the IIR register
*/
STATIC INLINE uint32_t Chip_UART_ReadIntIDReg(LPC_USART_T *pUART)
{
return pUART->IIR;
}
/**
* @brief Setup the UART FIFOs
* @param pUART : Pointer to selected UART peripheral
* @param fcr : FIFO control register setup OR'ed flags
* @return Nothing
* @note Use OR'ed value of UART_FCR_* definitions with this function
* to select specific options. For example, to enable the FIFOs
* with a RX trip level of 8 characters, use something like
* (UART_FCR_FIFO_EN | UART_FCR_TRG_LEV2)
*/
STATIC INLINE void Chip_UART_SetupFIFOS(LPC_USART_T *pUART, uint32_t fcr)
{
pUART->FCR = fcr;
}
/**
* @brief Configure data width, parity and stop bits
* @param pUART : Pointer to selected pUART peripheral
* @param config : UART configuration, OR'ed values of UART_LCR_* defines
* @return Nothing
* @note Select OR'ed config options for the UART from the UART_LCR_*
* definitions. For example, a configuration of 8 data bits, 1
* stop bit, and even (enabled) parity would be
* (UART_LCR_WLEN8 | UART_LCR_SBS_1BIT | UART_LCR_PARITY_EN | UART_LCR_PARITY_EVEN)
*/
STATIC INLINE void Chip_UART_ConfigData(LPC_USART_T *pUART, uint32_t config)
{
pUART->LCR = config;
}
/**
* @brief Enable access to Divisor Latches
* @param pUART : Pointer to selected UART peripheral
* @return Nothing
*/
STATIC INLINE void Chip_UART_EnableDivisorAccess(LPC_USART_T *pUART)
{
pUART->LCR |= UART_LCR_DLAB_EN;
}
/**
* @brief Disable access to Divisor Latches
* @param pUART : Pointer to selected UART peripheral
* @return Nothing
*/
STATIC INLINE void Chip_UART_DisableDivisorAccess(LPC_USART_T *pUART)
{
pUART->LCR &= ~UART_LCR_DLAB_EN;
}
/**
* @brief Set LSB and MSB divisor latch registers
* @param pUART : Pointer to selected UART peripheral
* @param dll : Divisor Latch LSB value
* @param dlm : Divisor Latch MSB value
* @return Nothing
* @note The Divisor Latch Access Bit (DLAB) in LCR must be set in
* order to access the USART Divisor Latches. This function
* doesn't alter the DLAB state.
*/
STATIC INLINE void Chip_UART_SetDivisorLatches(LPC_USART_T *pUART, uint8_t dll, uint8_t dlm)
{
pUART->DLL = (uint32_t) dll;
pUART->DLM = (uint32_t) dlm;
}
/**
* @brief Return modem control register/status
* @param pUART : Pointer to selected UART peripheral
* @return Modem control register (status)
* @note Mask bits of the returned status value with UART_MCR_*
* definitions for specific statuses.
*/
STATIC INLINE uint32_t Chip_UART_ReadModemControl(LPC_USART_T *pUART)
{
return pUART->MCR;
}
/**
* @brief Set modem control register/status
* @param pUART : Pointer to selected UART peripheral
* @param mcr : Modem control register flags to set
* @return Nothing
* @note Use an Or'ed value of UART_MCR_* definitions with this
* call to set specific options.
*/
STATIC INLINE void Chip_UART_SetModemControl(LPC_USART_T *pUART, uint32_t mcr)
{
pUART->MCR |= mcr;
}
/**
* @brief Clear modem control register/status
* @param pUART : Pointer to selected UART peripheral
* @param mcr : Modem control register flags to clear
* @return Nothing
* @note Use an Or'ed value of UART_MCR_* definitions with this
* call to clear specific options.
*/
STATIC INLINE void Chip_UART_ClearModemControl(LPC_USART_T *pUART, uint32_t mcr)
{
pUART->MCR &= ~mcr;
}
/**
* @brief Return Line Status register/status (LSR)
* @param pUART : Pointer to selected UART peripheral
* @return Line Status register (status)
* @note Mask bits of the returned status value with UART_LSR_*
* definitions for specific statuses.
*/
STATIC INLINE uint32_t Chip_UART_ReadLineStatus(LPC_USART_T *pUART)
{
return pUART->LSR;
}
/**
* @brief Return Modem Status register/status (MSR)
* @param pUART : Pointer to selected UART peripheral
* @return Modem Status register (status)
* @note Mask bits of the returned status value with UART_MSR_*
* definitions for specific statuses.
*/
STATIC INLINE uint32_t Chip_UART_ReadModemStatus(LPC_USART_T *pUART)
{
return pUART->MSR;
}
/**
* @brief Write a byte to the scratchpad register
* @param pUART : Pointer to selected UART peripheral
* @param data : Byte value to write
* @return Nothing
*/
STATIC INLINE void Chip_UART_SetScratch(LPC_USART_T *pUART, uint8_t data)
{
pUART->SCR = (uint32_t) data;
}
/**
* @brief Returns current byte value in the scratchpad register
* @param pUART : Pointer to selected UART peripheral
* @return Byte value read from scratchpad register
*/
STATIC INLINE uint8_t Chip_UART_ReadScratch(LPC_USART_T *pUART)
{
return (uint8_t) (pUART->SCR & 0xFF);
}
/**
* @brief Set autobaud register options
* @param pUART : Pointer to selected UART peripheral
* @param acr : Or'ed values to set for ACR register
* @return Nothing
* @note Use an Or'ed value of UART_ACR_* definitions with this
* call to set specific options.
*/
STATIC INLINE void Chip_UART_SetAutoBaudReg(LPC_USART_T *pUART, uint32_t acr)
{
pUART->ACR |= acr;
}
/**
* @brief Clear autobaud register options
* @param pUART : Pointer to selected UART peripheral
* @param acr : Or'ed values to clear for ACR register
* @return Nothing
* @note Use an Or'ed value of UART_ACR_* definitions with this
* call to clear specific options.
*/
STATIC INLINE void Chip_UART_ClearAutoBaudReg(LPC_USART_T *pUART, uint32_t acr)
{
pUART->ACR &= ~acr;
}
/**
* @brief Set RS485 control register options
* @param pUART : Pointer to selected UART peripheral
* @param ctrl : Or'ed values to set for RS485 control register
* @return Nothing
* @note Use an Or'ed value of UART_RS485CTRL_* definitions with this
* call to set specific options.
*/
STATIC INLINE void Chip_UART_SetRS485Flags(LPC_USART_T *pUART, uint32_t ctrl)
{
pUART->RS485CTRL |= ctrl;
}
/**
* @brief Clear RS485 control register options
* @param pUART : Pointer to selected UART peripheral
* @param ctrl : Or'ed values to clear for RS485 control register
* @return Nothing
* @note Use an Or'ed value of UART_RS485CTRL_* definitions with this
* call to clear specific options.
*/
STATIC INLINE void Chip_UART_ClearRS485Flags(LPC_USART_T *pUART, uint32_t ctrl)
{
pUART->RS485CTRL &= ~ctrl;
}
/**
* @brief Set RS485 address match value
* @param pUART : Pointer to selected UART peripheral
* @param addr : Address match value for RS-485/EIA-485 mode
* @return Nothing
*/
STATIC INLINE void Chip_UART_SetRS485Addr(LPC_USART_T *pUART, uint8_t addr)
{
pUART->RS485ADRMATCH = (uint32_t) addr;
}
/**
* @brief Read RS485 address match value
* @param pUART : Pointer to selected UART peripheral
* @return Address match value for RS-485/EIA-485 mode
*/
STATIC INLINE uint8_t Chip_UART_GetRS485Addr(LPC_USART_T *pUART)
{
return (uint8_t) (pUART->RS485ADRMATCH & 0xFF);
}
/**
* @brief Set RS485 direction control (RTS or DTR) delay value
* @param pUART : Pointer to selected UART peripheral
* @param dly : direction control (RTS or DTR) delay value
* @return Nothing
* @note This delay time is in periods of the baud clock. Any delay
* time from 0 to 255 bit times may be programmed.
*/
STATIC INLINE void Chip_UART_SetRS485Delay(LPC_USART_T *pUART, uint8_t dly)
{
pUART->RS485DLY = (uint32_t) dly;
}
/**
* @brief Read RS485 direction control (RTS or DTR) delay value
* @param pUART : Pointer to selected UART peripheral
* @return direction control (RTS or DTR) delay value
* @note This delay time is in periods of the baud clock. Any delay
* time from 0 to 255 bit times may be programmed.
*/
STATIC INLINE uint8_t Chip_UART_GetRS485Delay(LPC_USART_T *pUART)
{
return (uint8_t) (pUART->RS485DLY & 0xFF);
}
/**
* @brief Initializes the pUART peripheral
* @param pUART : Pointer to selected pUART peripheral
* @return Nothing
*/
void Chip_UART_Init(LPC_USART_T *pUART);
/**
* @brief De-initializes the pUART peripheral.
* @param pUART : Pointer to selected pUART peripheral
* @return Nothing
*/
void Chip_UART_DeInit(LPC_USART_T *pUART);
/**
* @brief Transmit a byte array through the UART peripheral (non-blocking)
* @param pUART : Pointer to selected UART peripheral
* @param data : Pointer to bytes to transmit
* @param numBytes : Number of bytes to transmit
* @return The actual number of bytes placed into the FIFO
* @note This function places data into the transmit FIFO until either
* all the data is in the FIFO or the FIFO is full. This function
* will not block in the FIFO is full. The actual number of bytes
* placed into the FIFO is returned. This function ignores errors.
*/
int Chip_UART_Send(LPC_USART_T *pUART, const void *data, int numBytes);
/**
* @brief Read data through the UART peripheral (non-blocking)
* @param pUART : Pointer to selected UART peripheral
* @param data : Pointer to bytes array to fill
* @param numBytes : Size of the passed data array
* @return The actual number of bytes read
* @note This function reads data from the receive FIFO until either
* all the data has been read or the passed buffer is completely full.
* This function will not block. This function ignores errors.
*/
int Chip_UART_Read(LPC_USART_T *pUART, void *data, int numBytes);
/**
* @brief Sets best dividers to get a target bit rate (without fractional divider)
* @param pUART : Pointer to selected UART peripheral
* @param baudrate : Target baud rate (baud rate = bit rate)
* @return The actual baud rate, or 0 if no rate can be found
*/
uint32_t Chip_UART_SetBaud(LPC_USART_T *pUART, uint32_t baudrate);
/**
* @brief Sets best dividers to get a target bit rate (with fractional divider)
* @param pUART : Pointer to selected UART peripheral
* @param baudrate : Target baud rate (baud rate = bit rate)
* @return The actual baud rate, or 0 if no rate can be found
*/
uint32_t Chip_UART_SetBaudFDR(LPC_USART_T *pUART, uint32_t baudrate);
/**
* @brief Transmit a byte array through the UART peripheral (blocking)
* @param pUART : Pointer to selected UART peripheral
* @param data : Pointer to data to transmit
* @param numBytes : Number of bytes to transmit
* @return The number of bytes transmitted
* @note This function will send or place all bytes into the transmit
* FIFO. This function will block until the last bytes are in the FIFO.
*/
int Chip_UART_SendBlocking(LPC_USART_T *pUART, const void *data, int numBytes);
/**
* @brief Read data through the UART peripheral (blocking)
* @param pUART : Pointer to selected UART peripheral
* @param data : Pointer to data array to fill
* @param numBytes : Size of the passed data array
* @return The size of the dat array
* @note This function reads data from the receive FIFO until the passed
* buffer is completely full. The function will block until full.
* This function ignores errors.
*/
int Chip_UART_ReadBlocking(LPC_USART_T *pUART, void *data, int numBytes);
/**
* @brief UART receive-only interrupt handler for ring buffers
* @param pUART : Pointer to selected UART peripheral
* @param pRB : Pointer to ring buffer structure to use
* @return Nothing
* @note If ring buffer support is desired for the receive side
* of data transfer, the UART interrupt should call this
* function for a receive based interrupt status.
*/
void Chip_UART_RXIntHandlerRB(LPC_USART_T *pUART, RINGBUFF_T *pRB);
/**
* @brief UART transmit-only interrupt handler for ring buffers
* @param pUART : Pointer to selected UART peripheral
* @param pRB : Pointer to ring buffer structure to use
* @return Nothing
* @note If ring buffer support is desired for the transmit side
* of data transfer, the UART interrupt should call this
* function for a transmit based interrupt status.
*/
void Chip_UART_TXIntHandlerRB(LPC_USART_T *pUART, RINGBUFF_T *pRB);
/**
* @brief Populate a transmit ring buffer and start UART transmit
* @param pUART : Pointer to selected UART peripheral
* @param pRB : Pointer to ring buffer structure to use
* @param data : Pointer to buffer to move to ring buffer
* @param bytes : Number of bytes to move
* @return The number of bytes placed into the ring buffer
* @note Will move the data into the TX ring buffer and start the
* transfer. If the number of bytes returned is less than the
* number of bytes to send, the ring buffer is considered full.
*/
uint32_t Chip_UART_SendRB(LPC_USART_T *pUART, RINGBUFF_T *pRB, const void *data, int bytes);
/**
* @brief Copy data from a receive ring buffer
* @param pUART : Pointer to selected UART peripheral
* @param pRB : Pointer to ring buffer structure to use
* @param data : Pointer to buffer to fill from ring buffer
* @param bytes : Size of the passed buffer in bytes
* @return The number of bytes placed into the ring buffer
* @note Will move the data from the RX ring buffer up to the
* the maximum passed buffer size. Returns 0 if there is
* no data in the ring buffer.
*/
int Chip_UART_ReadRB(LPC_USART_T *pUART, RINGBUFF_T *pRB, void *data, int bytes);
/**
* @brief UART receive/transmit interrupt handler for ring buffers
* @param pUART : Pointer to selected UART peripheral
* @param pRXRB : Pointer to transmit ring buffer
* @param pTXRB : Pointer to receive ring buffer
* @return Nothing
* @note This provides a basic implementation of the UART IRQ
* handler for support of a ring buffer implementation for
* transmit and receive.
*/
void Chip_UART_IRQRBHandler(LPC_USART_T *pUART, RINGBUFF_T *pRXRB, RINGBUFF_T *pTXRB);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __UART_11XX_H_ */

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/*
* @brief LPC11xx USB device register block
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __USBD_11XX_H_
#define __USBD_11XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup USBD_11XX CHIP: LPC11xx USB Device driver
* @ingroup CHIP_11XX_Drivers
* @{
*/
#if defined(CHIP_LPC11UXX)
/**
* @brief USB device register block structure
*/
typedef struct { /*!< (@ 0x40080000) USB Structure */
__IO uint32_t DEVCMDSTAT; /*!< (@ 0x40080000) USB Device Command/Status register */
__IO uint32_t INFO; /*!< (@ 0x40080004) USB Info register */
__IO uint32_t EPLISTSTART; /*!< (@ 0x40080008) USB EP Command/Status List start address */
__IO uint32_t DATABUFSTART; /*!< (@ 0x4008000C) USB Data buffer start address */
__IO uint32_t LPM; /*!< (@ 0x40080010) Link Power Management register */
__IO uint32_t EPSKIP; /*!< (@ 0x40080014) USB Endpoint skip */
__IO uint32_t EPINUSE; /*!< (@ 0x40080018) USB Endpoint Buffer in use */
__IO uint32_t EPBUFCFG; /*!< (@ 0x4008001C) USB Endpoint Buffer Configuration register */
__IO uint32_t INTSTAT; /*!< (@ 0x40080020) USB interrupt status register */
__IO uint32_t INTEN; /*!< (@ 0x40080024) USB interrupt enable register */
__IO uint32_t INTSETSTAT; /*!< (@ 0x40080028) USB set interrupt status register */
__IO uint32_t INTROUTING; /*!< (@ 0x4008002C) USB interrupt routing register */
__I uint32_t RESERVED0[1];
__I uint32_t EPTOGGLE; /*!< (@ 0x40080034) USB Endpoint toggle register */
} LPC_USB_T;
#endif /* defined(CHIP_LPC11UXX) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __USBD_11XX_H_ */

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/*
* @brief LPC11xx WWDT chip driver
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#ifndef __WWDT_11XX_H_
#define __WWDT_11XX_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup WWDT_11XX CHIP: LPC11xx Windowed Watchdog driver
* @ingroup CHIP_11XX_Drivers
* @{
*/
#if !defined(CHIP_LPC11CXX) || defined(CHIP_LPC1125)
#define WATCHDOG_WINDOW_SUPPORT
#endif
#if defined(CHIP_LPC11AXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX)
#define WATCHDOG_CLKSEL_SUPPORT
#endif
/**
* @brief Windowed Watchdog register block structure
*/
typedef struct { /*!< WWDT Structure */
__IO uint32_t MOD; /*!< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
__IO uint32_t TC; /*!< Watchdog timer constant register. This register determines the time-out value. */
__O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
__I uint32_t TV; /*!< Watchdog timer value register. This register reads out the current value of the Watchdog timer. */
#ifdef WATCHDOG_CLKSEL_SUPPORT
__IO uint32_t CLKSEL; /*!< Watchdog clock select register. */
#else
__I uint32_t RESERVED0;
#endif
#ifdef WATCHDOG_WINDOW_SUPPORT
__IO uint32_t WARNINT; /*!< Watchdog warning interrupt register. This register contains the Watchdog warning interrupt compare value. */
__IO uint32_t WINDOW; /*!< Watchdog timer window register. This register contains the Watchdog window value. */
#endif
} LPC_WWDT_T;
/**
* @brief Watchdog Mode register definitions
*/
/** Watchdog Mode Bitmask */
#define WWDT_WDMOD_BITMASK ((uint32_t) 0x1F)
/** WWDT interrupt enable bit */
#define WWDT_WDMOD_WDEN ((uint32_t) (1 << 0))
/** WWDT interrupt enable bit */
#define WWDT_WDMOD_WDRESET ((uint32_t) (1 << 1))
/** WWDT time out flag bit */
#define WWDT_WDMOD_WDTOF ((uint32_t) (1 << 2))
/** WDT Time Out flag bit */
#define WWDT_WDMOD_WDINT ((uint32_t) (1 << 3))
/** WWDT Protect flag bit */
#define WWDT_WDMOD_WDPROTECT ((uint32_t) (1 << 4))
/**
* @brief Initialize the Watchdog timer
* @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @return None
*/
void Chip_WWDT_Init(LPC_WWDT_T *pWWDT);
/**
* @brief Shutdown the Watchdog timer
* @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @return None
*/
void Chip_WWDT_DeInit(LPC_WWDT_T *pWWDT);
/**
* @brief Set WDT timeout constant value used for feed
* @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @param timeout : WDT timeout in ticks, between WWDT_TICKS_MIN and WWDT_TICKS_MAX
* @return none
*/
STATIC INLINE void Chip_WWDT_SetTimeOut(LPC_WWDT_T *pWWDT, uint32_t timeout)
{
pWWDT->TC = timeout;
}
/**
* @brief Feed watchdog timer
* @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @return None
* @note If this function isn't called, a watchdog timer warning will occur.
* After the warning, a timeout will occur if a feed has happened.
*/
STATIC INLINE void Chip_WWDT_Feed(LPC_WWDT_T *pWWDT)
{
pWWDT->FEED = 0xAA;
pWWDT->FEED = 0x55;
}
#if defined(WATCHDOG_WINDOW_SUPPORT)
/**
* @brief Set WWDT warning interrupt
* @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @param timeout : WDT warning in ticks, between 0 and 1023
* @return None
* @note This is the number of ticks after the watchdog interrupt that the
* warning interrupt will be generated.
*/
STATIC INLINE void Chip_WWDT_SetWarning(LPC_WWDT_T *pWWDT, uint32_t timeout)
{
pWWDT->WARNINT = timeout;
}
/**
* @brief Set WWDT window time
* @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @param timeout : WDT timeout in ticks, between WWDT_TICKS_MIN and WWDT_TICKS_MAX
* @return None
* @note The watchdog timer must be fed between the timeout from the Chip_WWDT_SetTimeOut()
* function and this function, with this function defining the last tick before the
* watchdog window interrupt occurs.
*/
STATIC INLINE void Chip_WWDT_SetWindow(LPC_WWDT_T *pWWDT, uint32_t timeout)
{
pWWDT->WINDOW = timeout;
}
#endif
/**
* @brief Enable watchdog timer options
* @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @param options : An or'ed set of options of values
* WWDT_WDMOD_WDEN, WWDT_WDMOD_WDRESET, and WWDT_WDMOD_WDPROTECT
* @return None
* @note You can enable more than one option at once (ie, WWDT_WDMOD_WDRESET |
* WWDT_WDMOD_WDPROTECT), but use the WWDT_WDMOD_WDEN after all other options
* are set (or unset) with no other options. If WWDT_WDMOD_LOCK is used, it cannot
* be unset.
*/
STATIC INLINE void Chip_WWDT_SetOption(LPC_WWDT_T *pWWDT, uint32_t options)
{
pWWDT->MOD |= options;
}
/**
* @brief Disable/clear watchdog timer options
* @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @param options : An or'ed set of options of values
* WWDT_WDMOD_WDEN, WWDT_WDMOD_WDRESET, and WWDT_WDMOD_WDPROTECT
* @return None
* @note You can disable more than one option at once (ie, WWDT_WDMOD_WDRESET |
* WWDT_WDMOD_WDTOF).
*/
STATIC INLINE void Chip_WWDT_UnsetOption(LPC_WWDT_T *pWWDT, uint32_t options)
{
pWWDT->MOD &= (~options) & WWDT_WDMOD_BITMASK;
}
/**
* @brief Enable WWDT activity
* @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @return None
*/
STATIC INLINE void Chip_WWDT_Start(LPC_WWDT_T *pWWDT)
{
Chip_WWDT_SetOption(pWWDT, WWDT_WDMOD_WDEN);
Chip_WWDT_Feed(pWWDT);
}
/**
* @brief Read WWDT status flag
* @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @return Watchdog status, an Or'ed value of WWDT_WDMOD_*
*/
STATIC INLINE uint32_t Chip_WWDT_GetStatus(LPC_WWDT_T *pWWDT)
{
return pWWDT->MOD;
}
/**
* @brief Clear WWDT interrupt status flags
* @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @param status : Or'ed value of status flag(s) that you want to clear, should be:
* - WWDT_WDMOD_WDTOF: Clear watchdog timeout flag
* - WWDT_WDMOD_WDINT: Clear watchdog warning flag
* @return None
*/
void Chip_WWDT_ClearStatusFlag(LPC_WWDT_T *pWWDT, uint32_t status);
/**
* @brief Get the current value of WDT
* @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @return current value of WDT
*/
STATIC INLINE uint32_t Chip_WWDT_GetCurrentCount(LPC_WWDT_T *pWWDT)
{
return pWWDT->TV;
}
#if defined(WATCHDOG_CLKSEL_SUPPORT)
/**
* @brief Watchdog Timer Clock Source Selection register definitions
*/
/** Clock source select bitmask */
#define WWDT_CLKSEL_BITMASK ((uint32_t) 0x10000003)
/** Clock source select */
#define WWDT_CLKSEL_SOURCE(n) ((uint32_t) (n & 0x03))
/** Lock the clock source selection */
#define WWDT_CLKSEL_LOCK ((uint32_t) (1 << 31))
/**
* @brief Watchdog Clock Source definitions
*/
typedef enum {
WWDT_CLKSRC_IRC = WWDT_CLKSEL_SOURCE(0), /*!< Internal RC oscillator */
WWDT_CLKSRC_WATCHDOG_WDOSC = WWDT_CLKSEL_SOURCE(1), /*!< Watchdog oscillator (WDOSC) */
} CHIP_WWDT_CLK_SRC_T;
/**
* @brief Get the current value of WDT
* @param pWWDT : The base of WatchDog Timer peripheral on the chip
* @param wdtClkSrc : Selected watchdog clock source
* @return Nothing
*/
STATIC INLINE void Chip_WWDT_SelClockSource(LPC_WWDT_T *pWWDT, CHIP_WWDT_CLK_SRC_T wdtClkSrc)
{
pWWDT->CLKSEL = wdtClkSrc & WWDT_CLKSEL_BITMASK;
}
#endif
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __WWDT_11XX_H_ */

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/*
* @brief LPC1125 ADC driver
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
#if defined(CHIP_LPC1125)
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/* Set ADC interrupt bits (safe) */
void Chip_ADC_SetIntBits(LPC_ADC_T *pADC, uint32_t intMask)
{
uint32_t temp;
/* Read and write values may not be the same, write 0 to
undefined bits */
temp = pADC->INTEN & 0x001FFFE7;
pADC->INTEN = temp | intMask;
}
/* Clear ADC interrupt bits (safe) */
void Chip_ADC_ClearIntBits(LPC_ADC_T *pADC, uint32_t intMask)
{
uint32_t temp;
/* Read and write values may not be the same, write 0 to
undefined bits */
temp = pADC->INTEN & 0x001FFFE7;
pADC->INTEN = temp & ~intMask;
}
/* Set ADC threshold selection bits (safe) */
void Chip_ADC_SetTHRSELBits(LPC_ADC_T *pADC, uint32_t mask)
{
uint32_t temp;
/* Read and write values may not be the same, write 0 to
undefined bits */
temp = pADC->CHAN_THRSEL & 0x000001FE;
pADC->CHAN_THRSEL = temp | mask;
}
/* Clear ADC threshold selection bits (safe) */
void Chip_ADC_ClearTHRSELBits(LPC_ADC_T *pADC, uint32_t mask)
{
uint32_t temp;
/* Read and write values may not be the same, write 0 to
undefined bits */
temp = pADC->CHAN_THRSEL & 0x000001FE;
pADC->CHAN_THRSEL = temp & ~mask;
}
/*****************************************************************************
* Public functions
****************************************************************************/
/* Initialize the ADC peripheral */
void Chip_ADC_Init(LPC_ADC_T *pADC, uint32_t flags)
{
/* Power up ADC and enable ADC base clock */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_ADC_PD);
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_ADC);
/* FIXME - LPC1125 UM describes ADC reset, but no ADC reset bit in SYSCTL.
It will be easier to init if ADC reset is there. */
#if 0
/* Reset ADC */
Chip_SYSCTL_PeriphReset(RESET_ADC0);
#else
/* Disable ADC interrupts */
pADC->INTEN = 0;
#endif
/* Set ADC control options */
pADC->CTRL = flags;
}
/* Shutdown ADC */
void Chip_ADC_DeInit(LPC_ADC_T *pADC)
{
pADC->INTEN = 0;
pADC->CTRL = 0;
/* Stop ADC clock and then power down ADC */
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_ADC);
Chip_SYSCTL_PowerDown(SYSCTL_POWERDOWN_ADC_PD);
}
/* Set ADC clock rate */
void Chip_ADC_SetClockRate(LPC_ADC_T *pADC, uint32_t rate)
{
Chip_ADC_SetDivider(pADC, (Chip_Clock_GetSystemClockRate() / rate) - 1);
}
/* Helper function for safely setting ADC sequencer register bits */
void Chip_ADC_SetSequencerBits(LPC_ADC_T *pADC, ADC_SEQ_IDX_T seqIndex, uint32_t bits)
{
uint32_t temp;
/* Read sequencer register and mask off bits 20..25 */
temp = pADC->SEQ_CTRL[seqIndex] & ~(0x3F << 20);
/* OR in passed bits */
pADC->SEQ_CTRL[seqIndex] = temp | bits;
}
/* Helper function for safely clearing ADC sequencer register bits */
void Chip_ADC_ClearSequencerBits(LPC_ADC_T *pADC, ADC_SEQ_IDX_T seqIndex, uint32_t bits)
{
uint32_t temp;
/* Read sequencer register and mask off bits 20..25 */
temp = pADC->SEQ_CTRL[seqIndex] & ~(0x3F << 20);
/* OR in passed bits */
pADC->SEQ_CTRL[seqIndex] = temp & ~bits;
}
/* Enable interrupts in ADC (sequencers A/B and overrun) */
void Chip_ADC_EnableInt(LPC_ADC_T *pADC, uint32_t intMask)
{
Chip_ADC_SetIntBits(pADC, intMask);
}
/* Disable interrupts in ADC (sequencers A/B and overrun) */
void Chip_ADC_DisableInt(LPC_ADC_T *pADC, uint32_t intMask)
{
Chip_ADC_ClearIntBits(pADC, intMask);
}
/* Enable a threshold event interrupt in ADC */
void Chip_ADC_SetThresholdInt(LPC_ADC_T *pADC, uint8_t ch, ADC_INTEN_THCMP_T thInt)
{
int shiftIndex = 3 + (ch * 2);
/* Clear current bits first */
Chip_ADC_ClearIntBits(pADC, (ADC_INTEN_CMP_MASK << shiftIndex));
/* Set new threshold interrupt type */
Chip_ADC_SetIntBits(pADC, ((uint32_t) thInt << shiftIndex));
}
/* Select threshold 0 values for comparison for selected channels */
void Chip_ADC_SelectTH0Channels(LPC_ADC_T *pADC, uint32_t channels)
{
Chip_ADC_ClearTHRSELBits(pADC, channels);
}
/* Select threshold 1 value for comparison for selected channels */
void Chip_ADC_SelectTH1Channels(LPC_ADC_T *pADC, uint32_t channels)
{
Chip_ADC_SetTHRSELBits(pADC, channels);
}
#endif /* defined(CHIP_LPC1125) */

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/*
* @brief LPC11xx A/D conversion driver
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
#if !defined(CHIP_LPC1125)
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/* Get the number of clock for a full conversion */
STATIC INLINE uint8_t getFullConvClk(void)
{
return 11;
}
/* Get divider value */
STATIC uint8_t getClkDiv(LPC_ADC_T *pADC, bool burstMode, uint32_t adcRate, uint8_t clks)
{
uint32_t adcBlockFreq;
uint32_t fullAdcRate;
uint8_t div;
/* The APB clock (PCLK_ADC0) is divided by (CLKDIV+1) to produce the clock for
A/D converter, which should be less than or equal to 4.5MHz.
A fully conversion requires (bits_accuracy+1) of these clocks.
ADC Clock = PCLK_ADC0 / (CLKDIV + 1);
ADC rate = ADC clock / (the number of clocks required for each conversion);
*/
adcBlockFreq = Chip_Clock_GetSystemClockRate();
if (burstMode) {
fullAdcRate = adcRate * clks;
}
else {
fullAdcRate = adcRate * getFullConvClk();
}
/* Get the round value by fomular: (2*A + B)/(2*B) */
div = ((adcBlockFreq * 2 + fullAdcRate) / (fullAdcRate * 2)) - 1;
return div;
}
/* Set start mode for ADC */
void setStartMode(LPC_ADC_T *pADC, uint8_t start_mode)
{
uint32_t temp;
temp = pADC->CR & (~ADC_CR_START_MASK);
pADC->CR = temp | (ADC_CR_START_MODE_SEL((uint32_t) start_mode));
}
/* Get the ADC value */
Status readAdcVal(LPC_ADC_T *pADC, uint8_t channel, uint16_t *data)
{
uint32_t temp;
temp = pADC->DR[channel];
if (!ADC_DR_DONE(temp)) {
return ERROR;
}
/* if(ADC_DR_OVERRUN(temp) && (pADC->CR & ADC_CR_BURST)) */
/* return ERROR; */
*data = (uint16_t) ADC_DR_RESULT(temp);
return SUCCESS;
}
/*****************************************************************************
* Public functions
****************************************************************************/
/* Initialize the ADC peripheral and the ADC setup structure to default value */
void Chip_ADC_Init(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup)
{
uint8_t div;
uint32_t cr = 0;
uint32_t clk;
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_ADC_PD);
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_ADC);
pADC->INTEN = 0; /* Disable all interrupts */
cr |= ADC_CR_PDN;
ADCSetup->adcRate = ADC_MAX_SAMPLE_RATE;
ADCSetup->bitsAccuracy = ADC_10BITS;
clk = 11;
ADCSetup->burstMode = false;
div = getClkDiv(pADC, false, ADCSetup->adcRate, clk);
cr |= ADC_CR_CLKDIV(div);
cr |= ADC_CR_BITACC(ADCSetup->bitsAccuracy);
pADC->CR = cr;
}
/* Shutdown ADC */
void Chip_ADC_DeInit(LPC_ADC_T *pADC)
{
pADC->INTEN = 0x00000100;
pADC->CR = 0;
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_ADC);
Chip_SYSCTL_PowerDown(SYSCTL_POWERDOWN_ADC_PD);
}
/* Get the ADC value */
Status Chip_ADC_ReadValue(LPC_ADC_T *pADC, uint8_t channel, uint16_t *data)
{
return readAdcVal(pADC, channel, data);
}
/* Get ADC Channel status from ADC data register */
FlagStatus Chip_ADC_ReadStatus(LPC_ADC_T *pADC, uint8_t channel, uint32_t StatusType)
{
switch (StatusType) {
case ADC_DR_DONE_STAT:
return (pADC->STAT & (1UL << channel)) ? SET : RESET;
case ADC_DR_OVERRUN_STAT:
channel += 8;
return (pADC->STAT & (1UL << channel)) ? SET : RESET;
case ADC_DR_ADINT_STAT:
return pADC->STAT >> 16 ? SET : RESET;
default:
break;
}
return RESET;
}
/* Enable/Disable interrupt for ADC channel */
void Chip_ADC_Int_SetChannelCmd(LPC_ADC_T *pADC, uint8_t channel, FunctionalState NewState)
{
if (NewState == ENABLE) {
pADC->INTEN |= (1UL << channel);
}
else {
pADC->INTEN &= (~(1UL << channel));
}
}
/* Select the mode starting the AD conversion */
void Chip_ADC_SetStartMode(LPC_ADC_T *pADC, ADC_START_MODE_T mode, ADC_EDGE_CFG_T EdgeOption)
{
if ((mode != ADC_START_NOW) && (mode != ADC_NO_START)) {
if (EdgeOption) {
pADC->CR |= ADC_CR_EDGE;
}
else {
pADC->CR &= ~ADC_CR_EDGE;
}
}
setStartMode(pADC, (uint8_t) mode);
}
/* Set the ADC Sample rate */
void Chip_ADC_SetSampleRate(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup, uint32_t rate)
{
uint8_t div;
uint32_t cr;
cr = pADC->CR & (~ADC_SAMPLE_RATE_CONFIG_MASK);
ADCSetup->adcRate = rate;
div = getClkDiv(pADC, ADCSetup->burstMode, rate, (11 - ADCSetup->bitsAccuracy));
cr |= ADC_CR_CLKDIV(div);
cr |= ADC_CR_BITACC(ADCSetup->bitsAccuracy);
pADC->CR = cr;
}
/* Set the ADC accuracy bits */
void Chip_ADC_SetResolution(LPC_ADC_T *pADC, ADC_CLOCK_SETUP_T *ADCSetup, ADC_RESOLUTION_T resolution)
{
ADCSetup->bitsAccuracy = resolution;
Chip_ADC_SetSampleRate(pADC, ADCSetup, ADCSetup->adcRate);
}
/* Enable or disable the ADC channel on ADC peripheral */
void Chip_ADC_EnableChannel(LPC_ADC_T *pADC, ADC_CHANNEL_T channel, FunctionalState NewState)
{
if (NewState == ENABLE) {
pADC->CR |= ADC_CR_CH_SEL(channel);
}
else {
pADC->CR &= ~ADC_CR_START_MASK;
pADC->CR &= ~ADC_CR_CH_SEL(channel);
}
}
/* Enable burst mode */
void Chip_ADC_SetBurstCmd(LPC_ADC_T *pADC, FunctionalState NewState)
{
setStartMode(pADC, ADC_NO_START);
if (NewState == DISABLE) {
pADC->CR &= ~ADC_CR_BURST;
}
else {
pADC->CR |= ADC_CR_BURST;
}
}
/* Read the ADC value and convert it to 8bits value */
Status Chip_ADC_ReadByte(LPC_ADC_T *pADC, ADC_CHANNEL_T channel, uint8_t *data)
{
uint16_t temp = 0;
Status rt;
rt = readAdcVal(pADC, channel, &temp);
*data = (uint8_t) temp;
return rt;
}
#endif /* !defined(CHIP_LPC1125) */

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/*
* @brief LPC11xx Miscellaneous chip specific functions
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/* System Clock Frequency (Core Clock) */
uint32_t SystemCoreClock;
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
/* Update system core clock rate, should be called if the system has
a clock rate change */
void SystemCoreClockUpdate(void)
{
/* CPU core speed */
SystemCoreClock = Chip_Clock_GetSystemClockRate();
}

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/*
* @brief LPC11XX System clock control functions
*
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/* Inprecise clock rates for the watchdog oscillator */
STATIC const uint32_t wdtOSCRate[WDTLFO_OSC_4_60 + 1] = {
0, /* WDT_OSC_ILLEGAL */
600000, /* WDT_OSC_0_60 */
1050000, /* WDT_OSC_1_05 */
1400000, /* WDT_OSC_1_40 */
1750000, /* WDT_OSC_1_75 */
2100000, /* WDT_OSC_2_10 */
2400000, /* WDT_OSC_2_40 */
2700000, /* WDT_OSC_2_70 */
3000000, /* WDT_OSC_3_00 */
3250000, /* WDT_OSC_3_25 */
3500000, /* WDT_OSC_3_50 */
3750000, /* WDT_OSC_3_75 */
4000000, /* WDT_OSC_4_00 */
4200000, /* WDT_OSC_4_20 */
4400000, /* WDT_OSC_4_40 */
4600000 /* WDT_OSC_4_60 */
};
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/* Compute a WDT or LFO rate */
STATIC uint32_t Chip_Clock_GetWDTLFORate(uint32_t reg)
{
uint32_t div;
CHIP_WDTLFO_OSC_T clk;
/* Get WDT oscillator settings */
clk = (CHIP_WDTLFO_OSC_T) ((reg >> 5) & 0xF);
div = reg & 0x1F;
/* Compute clock rate and divided by divde value */
return wdtOSCRate[clk] / ((div + 1) << 1);
}
/* Compute a PLL frequency */
STATIC uint32_t Chip_Clock_GetPLLFreq(uint32_t PLLReg, uint32_t inputRate)
{
uint32_t msel = ((PLLReg & 0x1F) + 1);
return inputRate * msel;
}
/*****************************************************************************
* Public functions
****************************************************************************/
/* Set System PLL clock source */
void Chip_Clock_SetSystemPLLSource(CHIP_SYSCTL_PLLCLKSRC_T src)
{
LPC_SYSCTL->SYSPLLCLKSEL = (uint32_t) src;
LPC_SYSCTL->SYSPLLCLKUEN = 0;
LPC_SYSCTL->SYSPLLCLKUEN = 1;
}
/* Bypass System Oscillator and set oscillator frequency range */
void Chip_Clock_SetPLLBypass(bool bypass, bool highfr)
{
uint32_t ctrl = 0;
if (bypass) {
ctrl |= (1 << 0);
}
if (highfr) {
ctrl |= (1 << 1);
}
LPC_SYSCTL->SYSOSCCTRL = ctrl;
}
#if defined(CHIP_LPC11UXX)
/* Set USB PLL clock source */
void Chip_Clock_SetUSBPLLSource(CHIP_SYSCTL_PLLCLKSRC_T src)
{
LPC_SYSCTL->USBPLLCLKSEL = (uint32_t) src;
LPC_SYSCTL->USBPLLCLKUEN = 0;
LPC_SYSCTL->USBPLLCLKUEN = 1;
}
#endif
/* Set main system clock source */
void Chip_Clock_SetMainClockSource(CHIP_SYSCTL_MAINCLKSRC_T src)
{
LPC_SYSCTL->MAINCLKSEL = (uint32_t) src;
LPC_SYSCTL->MAINCLKUEN = 0;
LPC_SYSCTL->MAINCLKUEN = 1;
}
#if defined(CHIP_LPC11UXX)
/* Set USB clock source and divider */
void Chip_Clock_SetUSBClockSource(CHIP_SYSCTL_USBCLKSRC_T src, uint32_t div)
{
LPC_SYSCTL->USBCLKSEL = (uint32_t) src;
LPC_SYSCTL->USBCLKUEN = 0;
LPC_SYSCTL->USBCLKUEN = 1;
LPC_SYSCTL->USBCLKDIV = div;
}
#endif /*CHIP_LPC11UXX*/
#if defined(CHIP_LPC110X) || defined(CHIP_LPC11XXLV) || defined(CHIP_LPC11CXX) || defined(CHIP_LPC11EXX) || \
defined(CHIP_LPC1125)
/* Set WDT clock source and divider */
void Chip_Clock_SetWDTClockSource(CHIP_SYSCTL_WDTCLKSRC_T src, uint32_t div)
{
LPC_SYSCTL->WDTCLKSEL = (uint32_t) src;
LPC_SYSCTL->WDTCLKUEN = 0;
LPC_SYSCTL->WDTCLKUEN = 1;
LPC_SYSCTL->WDTCLKDIV = div;
}
#endif
#if !defined(CHIP_LPC110X)
/* Set CLKOUT clock source and divider */
void Chip_Clock_SetCLKOUTSource(CHIP_SYSCTL_CLKOUTSRC_T src, uint32_t div)
{
LPC_SYSCTL->CLKOUTSEL = (uint32_t) src;
LPC_SYSCTL->CLKOUTUEN = 0;
LPC_SYSCTL->CLKOUTUEN = 1;
LPC_SYSCTL->CLKOUTDIV = div;
}
#endif
/* Return estimated watchdog oscillator rate */
uint32_t Chip_Clock_GetWDTOSCRate(void)
{
return Chip_Clock_GetWDTLFORate(LPC_SYSCTL->WDTOSCCTRL);
}
#if defined(CHIP_LPC11AXX)
/* Return estimated low frequency oscillator rate */
uint32_t Chip_Clock_GetLFOOSCRate(void)
{
return Chip_Clock_GetWDTLFORate(LPC_SYSCTL->LFOSCCTRL);
}
#endif
/* Return System PLL input clock rate */
uint32_t Chip_Clock_GetSystemPLLInClockRate(void)
{
uint32_t clkRate;
switch ((CHIP_SYSCTL_PLLCLKSRC_T) (LPC_SYSCTL->SYSPLLCLKSEL & 0x3)) {
case SYSCTL_PLLCLKSRC_IRC:
clkRate = Chip_Clock_GetIntOscRate();
break;
case SYSCTL_PLLCLKSRC_MAINOSC:
clkRate = Chip_Clock_GetMainOscRate();
break;
#if defined(CHIP_LPC11AXX)
case SYSCTL_PLLCLKSRC_EXT_CLKIN:
clkRate = Chip_Clock_GetExtClockInRate();
break;
#endif
default:
clkRate = 0;
}
return clkRate;
}
/* Return System PLL output clock rate */
uint32_t Chip_Clock_GetSystemPLLOutClockRate(void)
{
return Chip_Clock_GetPLLFreq(LPC_SYSCTL->SYSPLLCTRL,
Chip_Clock_GetSystemPLLInClockRate());
}
#if defined(CHIP_LPC11UXX)
/* Return USB PLL input clock rate */
uint32_t Chip_Clock_GetUSBPLLInClockRate(void)
{
uint32_t clkRate;
switch ((CHIP_SYSCTL_PLLCLKSRC_T) (LPC_SYSCTL->USBPLLCLKSEL & 0x3)) {
case SYSCTL_PLLCLKSRC_IRC:
clkRate = Chip_Clock_GetIntOscRate();
break;
case SYSCTL_PLLCLKSRC_MAINOSC:
clkRate = Chip_Clock_GetMainOscRate();
break;
default:
clkRate = 0;
}
return clkRate;
}
/* Return USB PLL output clock rate */
uint32_t Chip_Clock_GetUSBPLLOutClockRate(void)
{
return Chip_Clock_GetPLLFreq(LPC_SYSCTL->USBPLLCTRL,
Chip_Clock_GetUSBPLLInClockRate());
}
#endif
/* Return main clock rate */
uint32_t Chip_Clock_GetMainClockRate(void)
{
uint32_t clkRate = 0;
switch ((CHIP_SYSCTL_MAINCLKSRC_T) (LPC_SYSCTL->MAINCLKSEL & 0x3)) {
case SYSCTL_MAINCLKSRC_IRC:
clkRate = Chip_Clock_GetIntOscRate();
break;
case SYSCTL_MAINCLKSRC_PLLIN:
clkRate = Chip_Clock_GetSystemPLLInClockRate();
break;
#if defined(CHIP_LPC11AXX)
case SYSCTL_MAINCLKSRC_LFOSC:
clkRate = Chip_Clock_GetLFOOSCRate();
break;
#else
case SYSCTL_MAINCLKSRC_WDTOSC:
clkRate = Chip_Clock_GetWDTOSCRate();
break;
#endif
case SYSCTL_MAINCLKSRC_PLLOUT:
clkRate = Chip_Clock_GetSystemPLLOutClockRate();
break;
}
return clkRate;
}
/* Return system clock rate */
uint32_t Chip_Clock_GetSystemClockRate(void)
{
/* No point in checking for divide by 0 */
return Chip_Clock_GetMainClockRate() / LPC_SYSCTL->SYSAHBCLKDIV;
}

109
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/*
* @brief LPC11xx GPIO driver for CHIP_LPC11AXX, CHIP_LPC11EXX, and
* CHIP_LPC11UXX families only.
*
* @note
* Copyright(C) NXP Semiconductors, 2013
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
#if defined(CHIP_LPC11AXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX)
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
/* Initialize GPIO block */
void Chip_GPIO_Init(LPC_GPIO_T *pGPIO)
{
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_GPIO);
}
/* De-Initialize GPIO block */
void Chip_GPIO_DeInit(LPC_GPIO_T *pGPIO)
{
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_GPIO);
}
/* Set a GPIO direction */
void Chip_GPIO_WriteDirBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t bit, bool setting)
{
if (setting) {
pGPIO->DIR[port] |= 1UL << bit;
}
else {
pGPIO->DIR[port] &= ~(1UL << bit);
}
}
/* Set Direction for a GPIO port */
void Chip_GPIO_SetDir(LPC_GPIO_T *pGPIO, uint8_t portNum, uint32_t bitValue, uint8_t out)
{
if (out) {
pGPIO->DIR[portNum] |= bitValue;
}
else {
pGPIO->DIR[portNum] &= ~bitValue;
}
}
/* Set GPIO direction for a single GPIO pin */
void Chip_GPIO_SetPinDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, bool output)
{
if (output) {
Chip_GPIO_SetPinDIROutput(pGPIO, port, pin);
}
else {
Chip_GPIO_SetPinDIRInput(pGPIO, port, pin);
}
}
/* Set GPIO direction for a all selected GPIO pins to an input or output */
void Chip_GPIO_SetPortDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pinMask, bool outSet)
{
if (outSet) {
Chip_GPIO_SetPortDIROutput(pGPIO, port, pinMask);
}
else {
Chip_GPIO_SetPortDIRInput(pGPIO, port, pinMask);
}
}
#endif /* defined(CHIP_LPC11AXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX) */

141
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/*
* @brief LPC11xx GPIO driver for CHIP_LPC11CXX, CHIP_LPC110X, CHIP_LPC11XXLV,
* and CHIP_LPC1125 families only.
*
* @note
* Copyright(C) NXP Semiconductors, 2013
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
#if defined(CHIP_LPC11CXX) || defined(CHIP_LPC110X) || defined(CHIP_LPC11XXLV) || defined(CHIP_LPC1125)
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
/* Initialize GPIO block */
void Chip_GPIO_Init(LPC_GPIO_T *pGPIO)
{
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_GPIO);
}
/* De-Initialize GPIO block */
void Chip_GPIO_DeInit(LPC_GPIO_T *pGPIO)
{
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_GPIO);
}
/* Set GPIO direction */
void Chip_GPIO_WriteDirBit(LPC_GPIO_T *pGPIO, uint32_t port, uint8_t bit, bool setting)
{
if (setting) {
pGPIO[port].DIR |= 1UL << bit;
}
else {
pGPIO[port].DIR &= ~(1UL << bit);
}
}
/* Set Direction for a GPIO port */
void Chip_GPIO_SetDir(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t bit, uint8_t out)
{
if (out) {
pGPIO[port].DIR |= bit;
}
else {
pGPIO[port].DIR &= ~bit;
}
}
/* Set GPIO direction for a single GPIO pin */
void Chip_GPIO_SetPinDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, bool output)
{
if (output) {
Chip_GPIO_SetPinDIROutput(pGPIO, port, pin);
}
else {
Chip_GPIO_SetPinDIRInput(pGPIO, port, pin);
}
}
/* Set GPIO direction for a all selected GPIO pins to an input or output */
void Chip_GPIO_SetPortDIR(LPC_GPIO_T *pGPIO, uint8_t port, uint32_t pinMask, bool outSet)
{
if (outSet) {
Chip_GPIO_SetPortDIROutput(pGPIO, port, pinMask);
}
else {
Chip_GPIO_SetPortDIRInput(pGPIO, port, pinMask);
}
}
/* Composite function for setting up a full interrupt configuration for a single pin */
void Chip_GPIO_SetupPinInt(LPC_GPIO_T *pGPIO, uint8_t port, uint8_t pin, GPIO_INT_MODE_T mode)
{
uint32_t pinMask = (1 << pin);
/* Edge mode selected? */
if ((uint32_t) mode & 0x2) {
Chip_GPIO_SetPinModeEdge(pGPIO, port, pinMask);
/* Interrupt on both edges selected? */
if ((uint32_t) mode & 0x4) {
Chip_GPIO_SetEdgeModeBoth(pGPIO, port, pinMask);
}
else {
Chip_GPIO_SetEdgeModeSingle(pGPIO, port, pinMask);
}
}
else {
/* Level mode */
Chip_GPIO_SetPinModeLevel(pGPIO, port, pinMask);
}
/* Level selections will not alter 'dual edge' mode */
if ((uint32_t) mode & 0x1) {
/* High edge or level mode selected */
Chip_GPIO_SetModeHigh(pGPIO, port, pinMask);
}
else {
Chip_GPIO_SetModeLow(pGPIO, port, pinMask);
}
}
#endif /* defined(CHIP_LPC11CXX) || defined(CHIP_LPC110X) || defined(CHIP_LPC11XXLV) || defined(CHIP_LPC1125) */

53
basic-setup/components/u8g2/sys/arm/plain/lpc_chip_11uxx_lib/src/gpiogroup_11xx.c Normal file
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/*
* @brief LPC11xx GPIO group driver for CHIP_LPC11AXX, CHIP_LPC11EXX, and
* CHIP_LPC11UXX families only.
*
* @note
* Copyright(C) NXP Semiconductors, 2013
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
#if defined(CHIP_LPC11AXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX)
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
#endif /* defined(CHIP_LPC11AXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX) */

553
basic-setup/components/u8g2/sys/arm/plain/lpc_chip_11uxx_lib/src/i2c_11xx.c Normal file
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/*
* @brief LPC11xx I2C driver
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
#if !defined(CHIP_LPC110X)
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/* Control flags */
#define I2C_CON_FLAGS (I2C_CON_AA | I2C_CON_SI | I2C_CON_STO | I2C_CON_STA)
#define LPC_I2Cx(id) ((i2c[id].ip))
#define SLAVE_ACTIVE(iic) (((iic)->flags & 0xFF00) != 0)
/* I2C common interface structure */
struct i2c_interface {
LPC_I2C_T *ip; /* IP base address of the I2C device */
CHIP_SYSCTL_CLOCK_T clk; /* Clock used by I2C */
I2C_EVENTHANDLER_T mEvent; /* Current active Master event handler */
I2C_EVENTHANDLER_T sEvent; /* Slave transfer events */
I2C_XFER_T *mXfer; /* Current active xfer pointer */
I2C_XFER_T *sXfer; /* Pointer to store xfer when bus is busy */
uint32_t flags; /* Flags used by I2C master and slave */
};
/* Slave interface structure */
struct i2c_slave_interface {
I2C_XFER_T *xfer;
I2C_EVENTHANDLER_T event;
};
/* I2C interfaces */
static struct i2c_interface i2c[I2C_NUM_INTERFACE] = {
{LPC_I2C, SYSCTL_CLOCK_I2C, Chip_I2C_EventHandler, NULL, NULL, NULL, 0}
};
static struct i2c_slave_interface i2c_slave[I2C_NUM_INTERFACE][I2C_SLAVE_NUM_INTERFACE];
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
STATIC INLINE void enableClk(I2C_ID_T id)
{
Chip_Clock_EnablePeriphClock(i2c[id].clk);
}
STATIC INLINE void disableClk(I2C_ID_T id)
{
Chip_Clock_DisablePeriphClock(i2c[id].clk);
}
/* Get the ADC Clock Rate */
STATIC INLINE uint32_t getClkRate(I2C_ID_T id)
{
return Chip_Clock_GetMainClockRate();
}
/* Enable I2C and start master transfer */
STATIC INLINE void startMasterXfer(LPC_I2C_T *pI2C)
{
/* Reset STA, STO, SI */
pI2C->CONCLR = I2C_CON_SI | I2C_CON_STO | I2C_CON_STA | I2C_CON_AA;
/* Enter to Master Transmitter mode */
pI2C->CONSET = I2C_CON_I2EN | I2C_CON_STA;
}
/* Enable I2C and enable slave transfers */
STATIC INLINE void startSlaverXfer(LPC_I2C_T *pI2C)
{
/* Reset STA, STO, SI */
pI2C->CONCLR = I2C_CON_SI | I2C_CON_STO | I2C_CON_STA;
/* Enter to Master Transmitter mode */
pI2C->CONSET = I2C_CON_I2EN | I2C_CON_AA;
}
/* Check if I2C bus is free */
STATIC INLINE int isI2CBusFree(LPC_I2C_T *pI2C)
{
return !(pI2C->CONSET & I2C_CON_STO);
}
/* Get current state of the I2C peripheral */
STATIC INLINE int getCurState(LPC_I2C_T *pI2C)
{
return (int) (pI2C->STAT & I2C_STAT_CODE_BITMASK);
}
/* Check if the active state belongs to master mode*/
STATIC INLINE int isMasterState(LPC_I2C_T *pI2C)
{
return getCurState(pI2C) < 0x60;
}
/* Set OWN slave address for specific slave ID */
STATIC void setSlaveAddr(LPC_I2C_T *pI2C, I2C_SLAVE_ID sid, uint8_t addr, uint8_t mask)
{
uint32_t index = (uint32_t) sid - 1;
pI2C->MASK[index] = mask;
if (sid == I2C_SLAVE_0) {
pI2C->ADR0 = addr;
}
else {
volatile uint32_t *abase = &pI2C->ADR1;
abase[index - 1] = addr;
}
}
/* Match the slave address */
STATIC int isSlaveAddrMatching(uint8_t addr1, uint8_t addr2, uint8_t mask)
{
mask |= 1;
return (addr1 & ~mask) == (addr2 & ~mask);
}
/* Get the index of the active slave */
STATIC I2C_SLAVE_ID lookupSlaveIndex(LPC_I2C_T *pI2C, uint8_t slaveAddr)
{
if (!(slaveAddr >> 1)) {
return I2C_SLAVE_GENERAL; /* General call address */
}
if (isSlaveAddrMatching(pI2C->ADR0, slaveAddr, pI2C->MASK[0])) {
return I2C_SLAVE_0;
}
if (isSlaveAddrMatching(pI2C->ADR1, slaveAddr, pI2C->MASK[1])) {
return I2C_SLAVE_1;
}
if (isSlaveAddrMatching(pI2C->ADR2, slaveAddr, pI2C->MASK[2])) {
return I2C_SLAVE_2;
}
if (isSlaveAddrMatching(pI2C->ADR3, slaveAddr, pI2C->MASK[3])) {
return I2C_SLAVE_3;
}
/* If everything is fine the code should never come here */
return I2C_SLAVE_GENERAL;
}
/* Master transfer state change handler handler */
int handleMasterXferState(LPC_I2C_T *pI2C, I2C_XFER_T *xfer)
{
uint32_t cclr = I2C_CON_FLAGS;
switch (getCurState(pI2C)) {
case 0x08: /* Start condition on bus */
case 0x10: /* Repeated start condition */
pI2C->DAT = (xfer->slaveAddr << 1) | (xfer->txSz == 0);
break;
/* Tx handling */
case 0x18: /* SLA+W sent and ACK received */
case 0x28: /* DATA sent and ACK received */
if (!xfer->txSz) {
cclr &= ~(xfer->rxSz ? I2C_CON_STA : I2C_CON_STO);
}
else {
pI2C->DAT = *xfer->txBuff++;
xfer->txSz--;
}
break;
/* Rx handling */
case 0x58: /* Data Received and NACK sent */
cclr &= ~I2C_CON_STO;
case 0x50: /* Data Received and ACK sent */
*xfer->rxBuff++ = pI2C->DAT;
xfer->rxSz--;
case 0x40: /* SLA+R sent and ACK received */
if (xfer->rxSz > 1) {
cclr &= ~I2C_CON_AA;
}
break;
/* NAK Handling */
case 0x20: /* SLA+W sent NAK received */
case 0x30: /* DATA sent NAK received */
case 0x48: /* SLA+R sent NAK received */
xfer->status = I2C_STATUS_NAK;
cclr &= ~I2C_CON_STO;
break;
case 0x38: /* Arbitration lost */
xfer->status = I2C_STATUS_ARBLOST;
break;
/* Bus Error */
case 0x00:
xfer->status = I2C_STATUS_BUSERR;
cclr &= ~I2C_CON_STO;
}
/* Set clear control flags */
pI2C->CONSET = cclr ^ I2C_CON_FLAGS;
pI2C->CONCLR = cclr;
/* If stopped return 0 */
if (!(cclr & I2C_CON_STO) || (xfer->status == I2C_STATUS_ARBLOST)) {
if (xfer->status == I2C_STATUS_BUSY) {
xfer->status = I2C_STATUS_DONE;
}
return 0;
}
return 1;
}
/* Find the slave address of SLA+W or SLA+R */
I2C_SLAVE_ID getSlaveIndex(LPC_I2C_T *pI2C)
{
switch (getCurState(pI2C)) {
case 0x60:
case 0x68:
case 0x70:
case 0x78:
case 0xA8:
case 0xB0:
return lookupSlaveIndex(pI2C, pI2C->DAT);
}
/* If everything is fine code should never come here */
return I2C_SLAVE_GENERAL;
}
/* Slave state machine handler */
int handleSlaveXferState(LPC_I2C_T *pI2C, I2C_XFER_T *xfer)
{
uint32_t cclr = I2C_CON_FLAGS;
int ret = RET_SLAVE_BUSY;
xfer->status = I2C_STATUS_BUSY;
switch (getCurState(pI2C)) {
case 0x80: /* SLA: Data received + ACK sent */
case 0x90: /* GC: Data received + ACK sent */
*xfer->rxBuff++ = pI2C->DAT;
xfer->rxSz--;
ret = RET_SLAVE_RX;
if (xfer->rxSz > 1) {
cclr &= ~I2C_CON_AA;
}
break;
case 0x60: /* Own SLA+W received */
case 0x68: /* Own SLA+W received after losing arbitration */
case 0x70: /* GC+W received */
case 0x78: /* GC+W received after losing arbitration */
xfer->slaveAddr = pI2C->DAT & ~1;
if (xfer->rxSz > 1) {
cclr &= ~I2C_CON_AA;
}
break;
case 0xA8: /* SLA+R received */
case 0xB0: /* SLA+R received after losing arbitration */
xfer->slaveAddr = pI2C->DAT & ~1;
case 0xB8: /* DATA sent and ACK received */
pI2C->DAT = *xfer->txBuff++;
xfer->txSz--;
if (xfer->txSz > 0) {
cclr &= ~I2C_CON_AA;
}
ret = RET_SLAVE_TX;
break;
case 0xC0: /* Data transmitted and NAK received */
case 0xC8: /* Last data transmitted and ACK received */
case 0x88: /* SLA: Data received + NAK sent */
case 0x98: /* GC: Data received + NAK sent */
case 0xA0: /* STOP/Repeated START condition received */
ret = RET_SLAVE_IDLE;
cclr &= ~I2C_CON_AA;
xfer->status = I2C_STATUS_DONE;
if (xfer->slaveAddr & 1) {
cclr &= ~I2C_CON_STA;
}
break;
}
/* Set clear control flags */
pI2C->CONSET = cclr ^ I2C_CON_FLAGS;
pI2C->CONCLR = cclr;
return ret;
}
/*****************************************************************************
* Public functions
****************************************************************************/
/* Chip event handler interrupt based */
void Chip_I2C_EventHandler(I2C_ID_T id, I2C_EVENT_T event)
{
struct i2c_interface *iic = &i2c[id];
volatile I2C_STATUS_T *stat;
/* Only WAIT event needs to be handled */
if (event != I2C_EVENT_WAIT) {
return;
}
stat = &iic->mXfer->status;
/* Wait for the status to change */
while (*stat == I2C_STATUS_BUSY) {}
}
/* Chip polling event handler */
void Chip_I2C_EventHandlerPolling(I2C_ID_T id, I2C_EVENT_T event)
{
struct i2c_interface *iic = &i2c[id];
volatile I2C_STATUS_T *stat;
/* Only WAIT event needs to be handled */
if (event != I2C_EVENT_WAIT) {
return;
}
stat = &iic->mXfer->status;
/* Call the state change handler till xfer is done */
while (*stat == I2C_STATUS_BUSY) {
if (Chip_I2C_IsStateChanged(id)) {
Chip_I2C_MasterStateHandler(id);
}
}
}
/* Initializes the LPC_I2C peripheral with specified parameter */
void Chip_I2C_Init(I2C_ID_T id)
{
enableClk(id);
/* Set I2C operation to default */
LPC_I2Cx(id)->CONCLR = (I2C_CON_AA | I2C_CON_SI | I2C_CON_STA | I2C_CON_I2EN);
}
/* De-initializes the I2C peripheral registers to their default reset values */
void Chip_I2C_DeInit(I2C_ID_T id)
{
/* Disable I2C control */
LPC_I2Cx(id)->CONCLR = I2C_CON_I2EN | I2C_CON_SI | I2C_CON_STO | I2C_CON_STA | I2C_CON_AA;
disableClk(id);
}
/* Set up clock rate for LPC_I2C peripheral */
void Chip_I2C_SetClockRate(I2C_ID_T id, uint32_t clockrate)
{
uint32_t SCLValue;
SCLValue = (getClkRate(id) / clockrate);
LPC_I2Cx(id)->SCLH = (uint32_t) (SCLValue >> 1);
LPC_I2Cx(id)->SCLL = (uint32_t) (SCLValue - LPC_I2Cx(id)->SCLH);
}
/* Get current clock rate for LPC_I2C peripheral */
uint32_t Chip_I2C_GetClockRate(I2C_ID_T id)
{
return getClkRate(id) / (LPC_I2Cx(id)->SCLH + LPC_I2Cx(id)->SCLL);
}
/* Set the master event handler */
int Chip_I2C_SetMasterEventHandler(I2C_ID_T id, I2C_EVENTHANDLER_T event)
{
struct i2c_interface *iic = &i2c[id];
if (!iic->mXfer) {
iic->mEvent = event;
}
return iic->mEvent == event;
}
/* Get the master event handler */
I2C_EVENTHANDLER_T Chip_I2C_GetMasterEventHandler(I2C_ID_T id)
{
return i2c[id].mEvent;
}
/* Transmit and Receive data in master mode */
int Chip_I2C_MasterTransfer(I2C_ID_T id, I2C_XFER_T *xfer)
{
struct i2c_interface *iic = &i2c[id];
iic->mEvent(id, I2C_EVENT_LOCK);
xfer->status = I2C_STATUS_BUSY;
iic->mXfer = xfer;
/* If slave xfer not in progress */
if (!iic->sXfer) {
startMasterXfer(iic->ip);
}
iic->mEvent(id, I2C_EVENT_WAIT);
iic->mXfer = 0;
/* Wait for stop condition to appear on bus */
while (!isI2CBusFree(iic->ip)) {}
/* Start slave if one is active */
if (SLAVE_ACTIVE(iic)) {
startSlaverXfer(iic->ip);
}
iic->mEvent(id, I2C_EVENT_UNLOCK);
return (int) xfer->status;
}
/* Master tx only */
int Chip_I2C_MasterSend(I2C_ID_T id, uint8_t slaveAddr, const uint8_t *buff, uint8_t len)
{
I2C_XFER_T xfer = {0};
xfer.slaveAddr = slaveAddr;
xfer.txBuff = buff;
xfer.txSz = len;
while (Chip_I2C_MasterTransfer(id, &xfer) == I2C_STATUS_ARBLOST) {}
return len - xfer.txSz;
}
/* Transmit one byte and receive an array of bytes after a repeated start condition is generated in Master mode.
* This function is useful for communicating with the I2C slave registers
*/
int Chip_I2C_MasterCmdRead(I2C_ID_T id, uint8_t slaveAddr, uint8_t cmd, uint8_t *buff, int len)
{
I2C_XFER_T xfer = {0};
xfer.slaveAddr = slaveAddr;
xfer.txBuff = &cmd;
xfer.txSz = 1;
xfer.rxBuff = buff;
xfer.rxSz = len;
while (Chip_I2C_MasterTransfer(id, &xfer) == I2C_STATUS_ARBLOST) {}
return len - xfer.rxSz;
}
/* Sequential master read */
int Chip_I2C_MasterRead(I2C_ID_T id, uint8_t slaveAddr, uint8_t *buff, int len)
{
I2C_XFER_T xfer = {0};
xfer.slaveAddr = slaveAddr;
xfer.rxBuff = buff;
xfer.rxSz = len;
while (Chip_I2C_MasterTransfer(id, &xfer) == I2C_STATUS_ARBLOST) {}
return len - xfer.rxSz;
}
/* Check if master state is active */
int Chip_I2C_IsMasterActive(I2C_ID_T id)
{
return isMasterState(i2c[id].ip);
}
/* State change handler for master transfer */
void Chip_I2C_MasterStateHandler(I2C_ID_T id)
{
if (!handleMasterXferState(i2c[id].ip, i2c[id].mXfer)) {
i2c[id].mEvent(id, I2C_EVENT_DONE);
}
}
/* Setup slave function */
void Chip_I2C_SlaveSetup(I2C_ID_T id,
I2C_SLAVE_ID sid,
I2C_XFER_T *xfer,
I2C_EVENTHANDLER_T event,
uint8_t addrMask)
{
struct i2c_interface *iic = &i2c[id];
struct i2c_slave_interface *si2c = &i2c_slave[id][sid];
si2c->xfer = xfer;
si2c->event = event;
/* Set up the slave address */
if (sid != I2C_SLAVE_GENERAL) {
setSlaveAddr(iic->ip, sid, xfer->slaveAddr, addrMask);
}
if (!SLAVE_ACTIVE(iic) && !iic->mXfer) {
startSlaverXfer(iic->ip);
}
iic->flags |= 1 << (sid + 8);
}
/* I2C Slave event handler */
void Chip_I2C_SlaveStateHandler(I2C_ID_T id)
{
int ret;
struct i2c_interface *iic = &i2c[id];
/* Get the currently addressed slave */
if (!iic->sXfer) {
struct i2c_slave_interface *si2c;
I2C_SLAVE_ID sid = getSlaveIndex(iic->ip);
si2c = &i2c_slave[id][sid];
iic->sXfer = si2c->xfer;
iic->sEvent = si2c->event;
}
iic->sXfer->slaveAddr |= iic->mXfer != 0;
ret = handleSlaveXferState(iic->ip, iic->sXfer);
if (ret) {
if (iic->sXfer->status == I2C_STATUS_DONE) {
iic->sXfer = 0;
}
iic->sEvent(id, (I2C_EVENT_T) ret);
}
}
/* Disable I2C device */
void Chip_I2C_Disable(I2C_ID_T id)
{
LPC_I2Cx(id)->CONCLR = I2C_I2CONCLR_I2ENC;
}
/* State change checking */
int Chip_I2C_IsStateChanged(I2C_ID_T id)
{
return (LPC_I2Cx(id)->CONSET & I2C_CON_SI) != 0;
}
#endif /* !defined(CHIP_LPC110X) */

259
basic-setup/components/u8g2/sys/arm/plain/lpc_chip_11uxx_lib/src/i2cm_11xx.c Normal file
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/*
* @brief LPC11xx I2C master driver
*
* @note
* Copyright(C) NXP Semiconductors, 2013
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/* Control flags */
#define I2C_CON_FLAGS (I2C_CON_AA | I2C_CON_SI | I2C_CON_STO | I2C_CON_STA)
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
/* Initializes the LPC_I2C peripheral with specified parameter */
void Chip_I2CM_Init(LPC_I2C_T *pI2C)
{
/* Enable I2C clock */
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_I2C);
/* Peripheral reset control to I2C */
Chip_SYSCTL_PeriphReset(RESET_I2C0);
}
/* De-initializes the I2C peripheral registers to their default reset values */
void Chip_I2CM_DeInit(LPC_I2C_T *pI2C)
{
/* Disable I2C clock */
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_I2C);
}
/* Set up bus speed for LPC_I2C interface */
void Chip_I2CM_SetBusSpeed(LPC_I2C_T *pI2C, uint32_t busSpeed)
{
uint32_t clockDiv = (Chip_Clock_GetMainClockRate() / busSpeed);
Chip_I2CM_SetDutyCycle(pI2C, (clockDiv >> 1), (clockDiv - (clockDiv >> 1)));
}
/* Master transfer state change handler handler */
uint32_t Chip_I2CM_XferHandler(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer)
{
uint32_t cclr = I2C_CON_FLAGS;
switch (Chip_I2CM_GetCurState(pI2C)) {
case 0x08: /* Start condition on bus */
case 0x10: /* Repeated start condition */
pI2C->DAT = (xfer->slaveAddr << 1) | (xfer->txSz == 0);
break;
/* Tx handling */
case 0x30: /* DATA sent NAK received */
if ((xfer->options & I2CM_XFER_OPTION_IGNORE_NACK) == 0) {
xfer->status = I2CM_STATUS_NAK;
cclr &= ~I2C_CON_STO;
break;
}
case 0x18: /* SLA+W sent and ACK received */
case 0x28: /* DATA sent and ACK received */
if (!xfer->txSz) {
if (xfer->rxSz) {
cclr &= ~I2C_CON_STA;
}
else {
xfer->status = I2CM_STATUS_OK;
cclr &= ~I2C_CON_STO;
}
}
else {
pI2C->DAT = *xfer->txBuff++;
xfer->txSz--;
}
break;
/* Rx handling */
case 0x58: /* Data Received and NACK sent */
case 0x50: /* Data Received and ACK sent */
*xfer->rxBuff++ = pI2C->DAT;
xfer->rxSz--;
case 0x40: /* SLA+R sent and ACK received */
if ((xfer->rxSz > 1) || (xfer->options & I2CM_XFER_OPTION_LAST_RX_ACK)) {
cclr &= ~I2C_CON_AA;
}
if (xfer->rxSz == 0) {
xfer->status = I2CM_STATUS_OK;
cclr &= ~I2C_CON_STO;
}
break;
/* NAK Handling */
case 0x20: /* SLA+W sent NAK received */
case 0x48: /* SLA+R sent NAK received */
xfer->status = I2CM_STATUS_SLAVE_NAK;
cclr &= ~I2C_CON_STO;
break;
case 0x38: /* Arbitration lost */
xfer->status = I2CM_STATUS_ARBLOST;
break;
case 0x00: /* Bus Error */
xfer->status = I2CM_STATUS_BUS_ERROR;
cclr &= ~I2C_CON_STO;
break;
default:
xfer->status = I2CM_STATUS_ERROR;
cclr &= ~I2C_CON_STO;
break;
}
/* Set clear control flags */
pI2C->CONSET = cclr ^ I2C_CON_FLAGS;
pI2C->CONCLR = cclr;
return xfer->status != I2CM_STATUS_BUSY;
}
/* Transmit and Receive data in master mode */
void Chip_I2CM_Xfer(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer)
{
/* set the transfer status as busy */
xfer->status = I2CM_STATUS_BUSY;
/* Clear controller state. */
Chip_I2CM_ResetControl(pI2C);
/* Enter to Master Transmitter mode */
Chip_I2CM_SendStart(pI2C);
}
/* Transmit and Receive data in master mode */
uint32_t Chip_I2CM_XferBlocking(LPC_I2C_T *pI2C, I2CM_XFER_T *xfer)
{
uint32_t ret = 0;
/* start transfer */
Chip_I2CM_Xfer(pI2C, xfer);
while (ret == 0) {
/* wait for status change interrupt */
while ( Chip_I2CM_StateChanged(pI2C) == 0) {}
/* call state change handler */
ret = Chip_I2CM_XferHandler(pI2C, xfer);
}
return ret;
}
/* Master tx only */
uint32_t Chip_I2CM_Write(LPC_I2C_T *pI2C, const uint8_t *buff, uint32_t len)
{
uint32_t txLen = 0, err = 0;
/* clear state change interrupt status */
Chip_I2CM_ClearSI(pI2C);
/* generate START condition */
Chip_I2CM_SendStart(pI2C);
while ((txLen < len) && (err == 0)) {
/* wait for status change interrupt */
while ( Chip_I2CM_StateChanged(pI2C) == 0) {}
/* check status and send data */
switch (Chip_I2CM_GetCurState(pI2C)) {
case 0x08: /* Start condition on bus */
case 0x10: /* Repeated start condition */
case 0x18: /* SLA+W sent and ACK received */
case 0x28: /* DATA sent and ACK received */
Chip_I2CM_WriteByte(pI2C, buff[txLen++]);
break;
case 0x38: /* Arbitration lost */
break;
default: /* we shouldn't be in any other state */
err = 1;
break;
}
/* clear state change interrupt status */
Chip_I2CM_ClearSI(pI2C);
}
return txLen;
}
/* Sequential master read */
uint32_t Chip_I2CM_Read(LPC_I2C_T *pI2C, uint8_t *buff, uint32_t len)
{
uint32_t rxLen = 0, err = 0;
/* clear state change interrupt status */
Chip_I2CM_ClearSI(pI2C);
/* generate START condition and auto-ack data received */
pI2C->CONSET = I2C_CON_AA | I2C_CON_STA;
while ((rxLen < len) && (err == 0)) {
/* wait for status change interrupt */
while ( Chip_I2CM_StateChanged(pI2C) == 0) {}
/* check status and send data */
switch (Chip_I2CM_GetCurState(pI2C)) {
case 0x08: /* Start condition on bus */
case 0x10: /* Repeated start condition */
case 0x40: /* SLA+R sent and ACK received */
case 0x50: /* Data Received and ACK sent */
buff[rxLen++] = Chip_I2CM_ReadByte(pI2C);
break;
case 0x38: /* Arbitration lost */
break;
default: /* we shouldn't be in any other state */
err = 1;
break;
}
/* clear state change interrupt status */
Chip_I2CM_ClearSI(pI2C);
}
return rxLen;
}

59
basic-setup/components/u8g2/sys/arm/plain/lpc_chip_11uxx_lib/src/iocon_11xx.c Normal file
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/*
* @brief LPC11xx IOCON driver
*
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
#if defined(CHIP_LPC11UXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11AXX)
/* Sets I/O Control pin mux */
void Chip_IOCON_PinMuxSet(LPC_IOCON_T *pIOCON, uint8_t port, uint8_t pin, uint32_t modefunc)
{
if (port == 0) {
pIOCON->PIO0[pin] = modefunc;
}
else {
pIOCON->PIO1[pin] = modefunc;
}
}
#endif

52
basic-setup/components/u8g2/sys/arm/plain/lpc_chip_11uxx_lib/src/pinint_11xx.c Normal file
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/*
* @brief LPC11xx Pin Interrupt and Pattern Match driver
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licenser disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
#if defined(CHIP_LPC11AXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX)
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
#endif /* defined(CHIP_LPC11AXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX) */

119
basic-setup/components/u8g2/sys/arm/plain/lpc_chip_11uxx_lib/src/pmu_11xx.c Normal file
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/*
* @brief LPC11xx PMU chip driver
*
* @note
* Copyright(C) NXP Semiconductors, 2013
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
#if defined(CHIP_LPC11AXX) || defined(CHIP_LPC11CXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX) || \
defined(CHIP_LPC1125)
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
/* Enter MCU Sleep mode */
void Chip_PMU_SleepState(LPC_PMU_T *pPMU)
{
pPMU->PCON = PMU_PCON_PM_SLEEP;
/* Enter sleep mode */
__WFI();
}
#if defined(CHIP_LPC11AXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX)
/* Enter MCU Deep Sleep mode */
void Chip_PMU_DeepSleepState(LPC_PMU_T *pPMU)
{
SCB->SCR |= (1UL << SCB_SCR_SLEEPDEEP_Pos);
pPMU->PCON = PMU_PCON_PM_DEEPSLEEP;
/* Enter sleep mode */
__WFI();
}
/* Enter MCU Power down mode */
void Chip_PMU_PowerDownState(LPC_PMU_T *pPMU)
{
SCB->SCR |= (1UL << SCB_SCR_SLEEPDEEP_Pos);
pPMU->PCON = PMU_PCON_PM_POWERDOWN;
/* Enter sleep mode */
__WFI();
}
#endif /* defined(CHIP_LPC11AXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX) */
/* Enter MCU Deep Power down mode */
void Chip_PMU_DeepPowerDownState(LPC_PMU_T *pPMU)
{
SCB->SCR |= (1UL << SCB_SCR_SLEEPDEEP_Pos);
pPMU->PCON = PMU_PCON_PM_DEEPPOWERDOWN;
/* Enter sleep mode */
__WFI();
}
/* Put some of the peripheral in sleep mode */
void Chip_PMU_Sleep(LPC_PMU_T *pPMU, CHIP_PMU_MCUPOWER_T SleepMode)
{
#if defined(CHIP_LPC11AXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX)
if (SleepMode == PMU_MCU_DEEP_SLEEP) {
Chip_PMU_DeepSleepState(pPMU);
}
else if (SleepMode == PMU_MCU_POWER_DOWN) {
Chip_PMU_PowerDownState(pPMU);
}
else if (SleepMode == PMU_MCU_DEEP_PWRDOWN) {
Chip_PMU_DeepPowerDownState(pPMU);
}
else {
/* PMU_MCU_SLEEP */
Chip_PMU_SleepState(pPMU);
}
#elif defined(CHIP_LPC11CXX)
if (SleepMode == PMU_MCU_DEEP_PWRDOWN) {
Chip_PMU_DeepPowerDownState(pPMU);
}
#endif /* defined(CHIP_LPC11AXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX) */
}
#endif /* defined(CHIP_LPC11AXX) || defined(CHIP_LPC11CXX) || ... */

167
basic-setup/components/u8g2/sys/arm/plain/lpc_chip_11uxx_lib/src/ring_buffer.c Normal file
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/*
* @brief Common ring buffer support functions
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include <string.h>
#include "ring_buffer.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
#define RB_INDH(rb) ((rb)->head & ((rb)->count - 1))
#define RB_INDT(rb) ((rb)->tail & ((rb)->count - 1))
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
/* Initialize ring buffer */
int RingBuffer_Init(RINGBUFF_T *RingBuff, void *buffer, int itemSize, int count)
{
RingBuff->data = buffer;
RingBuff->count = count;
RingBuff->itemSz = itemSize;
RingBuff->head = RingBuff->tail = 0;
return 1;
}
/* Insert a single item into Ring Buffer */
int RingBuffer_Insert(RINGBUFF_T *RingBuff, const void *data)
{
uint8_t *ptr = RingBuff->data;
/* We cannot insert when queue is full */
if (RingBuffer_IsFull(RingBuff))
return 0;
ptr += RB_INDH(RingBuff) * RingBuff->itemSz;
memcpy(ptr, data, RingBuff->itemSz);
RingBuff->head++;
return 1;
}
/* Insert multiple items into Ring Buffer */
int RingBuffer_InsertMult(RINGBUFF_T *RingBuff, const void *data, int num)
{
uint8_t *ptr = RingBuff->data;
int cnt1, cnt2;
/* We cannot insert when queue is full */
if (RingBuffer_IsFull(RingBuff))
return 0;
/* Calculate the segment lengths */
cnt1 = cnt2 = RingBuffer_GetFree(RingBuff);
if (RB_INDH(RingBuff) + cnt1 >= RingBuff->count)
cnt1 = RingBuff->count - RB_INDH(RingBuff);
cnt2 -= cnt1;
cnt1 = MIN(cnt1, num);
num -= cnt1;
cnt2 = MIN(cnt2, num);
num -= cnt2;
/* Write segment 1 */
ptr += RB_INDH(RingBuff) * RingBuff->itemSz;
memcpy(ptr, data, cnt1 * RingBuff->itemSz);
RingBuff->head += cnt1;
/* Write segment 2 */
ptr = (uint8_t *) RingBuff->data + RB_INDH(RingBuff) * RingBuff->itemSz;
data = (const uint8_t *) data + cnt1 * RingBuff->itemSz;
memcpy(ptr, data, cnt2 * RingBuff->itemSz);
RingBuff->head += cnt2;
return cnt1 + cnt2;
}
/* Pop single item from Ring Buffer */
int RingBuffer_Pop(RINGBUFF_T *RingBuff, void *data)
{
uint8_t *ptr = RingBuff->data;
/* We cannot pop when queue is empty */
if (RingBuffer_IsEmpty(RingBuff))
return 0;
ptr += RB_INDT(RingBuff) * RingBuff->itemSz;
memcpy(data, ptr, RingBuff->itemSz);
RingBuff->tail++;
return 1;
}
/* Pop multiple items from Ring buffer */
int RingBuffer_PopMult(RINGBUFF_T *RingBuff, void *data, int num)
{
uint8_t *ptr = RingBuff->data;
int cnt1, cnt2;
/* We cannot insert when queue is empty */
if (RingBuffer_IsEmpty(RingBuff))
return 0;
/* Calculate the segment lengths */
cnt1 = cnt2 = RingBuffer_GetCount(RingBuff);
if (RB_INDT(RingBuff) + cnt1 >= RingBuff->count)
cnt1 = RingBuff->count - RB_INDT(RingBuff);
cnt2 -= cnt1;
cnt1 = MIN(cnt1, num);
num -= cnt1;
cnt2 = MIN(cnt2, num);
num -= cnt2;
/* Write segment 1 */
ptr += RB_INDT(RingBuff) * RingBuff->itemSz;
memcpy(data, ptr, cnt1 * RingBuff->itemSz);
RingBuff->tail += cnt1;
/* Write segment 2 */
ptr = (uint8_t *) RingBuff->data + RB_INDT(RingBuff) * RingBuff->itemSz;
data = (uint8_t *) data + cnt1 * RingBuff->itemSz;
memcpy(data, ptr, cnt2 * RingBuff->itemSz);
RingBuff->tail += cnt2;
return cnt1 + cnt2;
}

504
basic-setup/components/u8g2/sys/arm/plain/lpc_chip_11uxx_lib/src/ssp_11xx.c Normal file
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/*
* @brief LPC11xx SSP Registers and control functions
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
STATIC void SSP_Write2BFifo(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
{
if (xf_setup->tx_data) {
Chip_SSP_SendFrame(pSSP, (*(uint16_t *) ((uint32_t) xf_setup->tx_data +
xf_setup->tx_cnt)));
}
else {
Chip_SSP_SendFrame(pSSP, 0xFFFF);
}
xf_setup->tx_cnt += 2;
}
/** SSP macro: write 1 bytes to FIFO buffer */
STATIC void SSP_Write1BFifo(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
{
if (xf_setup->tx_data) {
Chip_SSP_SendFrame(pSSP, (*(uint8_t *) ((uint32_t) xf_setup->tx_data + xf_setup->tx_cnt)));
}
else {
Chip_SSP_SendFrame(pSSP, 0xFF);
}
xf_setup->tx_cnt++;
}
/** SSP macro: read 1 bytes from FIFO buffer */
STATIC void SSP_Read2BFifo(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
{
uint16_t rDat;
while ((Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET) &&
(xf_setup->rx_cnt < xf_setup->length)) {
rDat = Chip_SSP_ReceiveFrame(pSSP);
if (xf_setup->rx_data) {
*(uint16_t *) ((uint32_t) xf_setup->rx_data + xf_setup->rx_cnt) = rDat;
}
xf_setup->rx_cnt += 2;
}
}
/** SSP macro: read 2 bytes from FIFO buffer */
STATIC void SSP_Read1BFifo(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
{
uint16_t rDat;
while ((Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET) &&
(xf_setup->rx_cnt < xf_setup->length)) {
rDat = Chip_SSP_ReceiveFrame(pSSP);
if (xf_setup->rx_data) {
*(uint8_t *) ((uint32_t) xf_setup->rx_data + xf_setup->rx_cnt) = rDat;
}
xf_setup->rx_cnt++;
}
}
/* Returns clock for the peripheral block */
STATIC CHIP_SYSCTL_CLOCK_T Chip_SSP_GetClockIndex(LPC_SSP_T *pSSP)
{
CHIP_SYSCTL_CLOCK_T clkSSP;
if (pSSP == LPC_SSP0) {
clkSSP = SYSCTL_CLOCK_SSP0;
}
#if defined(CHIP_LPC11CXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11AXX) || defined(CHIP_LPC11UXX) || \
defined(CHIP_LPC1125)
else {
clkSSP = SYSCTL_CLOCK_SSP1;
}
#endif
return clkSSP;
}
/* Returns reset ID for the peripheral block */
STATIC CHIP_SYSCTL_PERIPH_RESET_T Chip_SSP_GetResetIndex(LPC_SSP_T *pSSP)
{
CHIP_SYSCTL_PERIPH_RESET_T resetSSP;
if (pSSP == LPC_SSP0) {
resetSSP = RESET_SSP0;
}
else {
resetSSP = RESET_SSP1;
}
return resetSSP;
}
/* Returns reset ID for the peripheral block */
STATIC void Chip_SSP_SetSSPClkDivider(LPC_SSP_T *pSSP, uint32_t div)
{
if (pSSP == LPC_SSP0) {
Chip_Clock_SetSSP0ClockDiv(div);
}
#if defined(CHIP_LPC11CXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11AXX) || defined(CHIP_LPC11UXX) || \
defined(CHIP_LPC1125)
else {
Chip_Clock_SetSSP1ClockDiv(div);
}
#endif
}
/* Returns SSP peripheral clock for the peripheral block */
STATIC uint32_t Chip_SSP_GetPCLKkRate(LPC_SSP_T *pSSP)
{
uint32_t sspCLK = Chip_Clock_GetMainClockRate();
if (pSSP == LPC_SSP0) {
sspCLK /= Chip_Clock_GetSSP0ClockDiv();
}
#if defined(CHIP_LPC11CXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11AXX) || defined(CHIP_LPC11UXX) || \
defined(CHIP_LPC1125)
else {
sspCLK /= Chip_Clock_GetSSP1ClockDiv();
}
#endif
return sspCLK;
}
/*****************************************************************************
* Public functions
****************************************************************************/
/*Set up output clocks per bit for SSP bus*/
void Chip_SSP_SetClockRate(LPC_SSP_T *pSSP, uint32_t clk_rate, uint32_t prescale)
{
uint32_t temp;
temp = pSSP->CR0 & (~(SSP_CR0_SCR(0xFF)));
pSSP->CR0 = temp | (SSP_CR0_SCR(clk_rate));
pSSP->CPSR = prescale;
}
/* SSP Polling Read/Write in blocking mode */
uint32_t Chip_SSP_RWFrames_Blocking(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
{
/* Clear all remaining frames in RX FIFO */
while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE)) {
Chip_SSP_ReceiveFrame(pSSP);
}
/* Clear status */
Chip_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK);
if (Chip_SSP_GetDataSize(pSSP) > SSP_BITS_8) {
while (xf_setup->rx_cnt < xf_setup->length || xf_setup->tx_cnt < xf_setup->length) {
/* write data to buffer */
if (( Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && ( xf_setup->tx_cnt < xf_setup->length) ) {
SSP_Write2BFifo(pSSP, xf_setup);
}
/* Check overrun error */
if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
return ERROR;
}
/* Check for any data available in RX FIFO */
SSP_Read2BFifo(pSSP, xf_setup);
}
}
else {
while (xf_setup->rx_cnt < xf_setup->length || xf_setup->tx_cnt < xf_setup->length) {
/* write data to buffer */
if (( Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && ( xf_setup->tx_cnt < xf_setup->length) ) {
SSP_Write1BFifo(pSSP, xf_setup);
}
/* Check overrun error */
if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
return ERROR;
}
/* Check for any data available in RX FIFO */
SSP_Read1BFifo(pSSP, xf_setup);
}
}
if (xf_setup->tx_data) {
return xf_setup->tx_cnt;
}
else if (xf_setup->rx_data) {
return xf_setup->rx_cnt;
}
return 0;
}
/* SSP Polling Write in blocking mode */
uint32_t Chip_SSP_WriteFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len)
{
uint32_t tx_cnt = 0, rx_cnt = 0;
/* Clear all remaining frames in RX FIFO */
while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE)) {
Chip_SSP_ReceiveFrame(pSSP);
}
/* Clear status */
Chip_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK);
if (Chip_SSP_GetDataSize(pSSP) > SSP_BITS_8) {
uint16_t *wdata16;
wdata16 = (uint16_t *) buffer;
while (tx_cnt < buffer_len || rx_cnt < buffer_len) {
/* write data to buffer */
if ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) {
Chip_SSP_SendFrame(pSSP, *wdata16);
wdata16++;
tx_cnt += 2;
}
/* Check overrun error */
if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
return ERROR;
}
/* Check for any data available in RX FIFO */
while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET) {
Chip_SSP_ReceiveFrame(pSSP); /* read dummy data */
rx_cnt += 2;
}
}
}
else {
uint8_t *wdata8;
wdata8 = buffer;
while (tx_cnt < buffer_len || rx_cnt < buffer_len) {
/* write data to buffer */
if ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) {
Chip_SSP_SendFrame(pSSP, *wdata8);
wdata8++;
tx_cnt++;
}
/* Check overrun error */
if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
return ERROR;
}
/* Check for any data available in RX FIFO */
while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET && rx_cnt < buffer_len) {
Chip_SSP_ReceiveFrame(pSSP); /* read dummy data */
rx_cnt++;
}
}
}
return tx_cnt;
}
/* SSP Polling Read in blocking mode */
uint32_t Chip_SSP_ReadFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len)
{
uint32_t rx_cnt = 0, tx_cnt = 0;
/* Clear all remaining frames in RX FIFO */
while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE)) {
Chip_SSP_ReceiveFrame(pSSP);
}
/* Clear status */
Chip_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK);
if (Chip_SSP_GetDataSize(pSSP) > SSP_BITS_8) {
uint16_t *rdata16;
rdata16 = (uint16_t *) buffer;
while (tx_cnt < buffer_len || rx_cnt < buffer_len) {
/* write data to buffer */
if ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) {
Chip_SSP_SendFrame(pSSP, 0xFFFF); /* just send dummy data */
tx_cnt += 2;
}
/* Check overrun error */
if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
return ERROR;
}
/* Check for any data available in RX FIFO */
while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET && rx_cnt < buffer_len) {
*rdata16 = Chip_SSP_ReceiveFrame(pSSP);
rdata16++;
rx_cnt += 2;
}
}
}
else {
uint8_t *rdata8;
rdata8 = buffer;
while (tx_cnt < buffer_len || rx_cnt < buffer_len) {
/* write data to buffer */
if ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) {
Chip_SSP_SendFrame(pSSP, 0xFF); /* just send dummy data */
tx_cnt++;
}
/* Check overrun error */
if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
return ERROR;
}
/* Check for any data available in RX FIFO */
while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET && rx_cnt < buffer_len) {
*rdata8 = Chip_SSP_ReceiveFrame(pSSP);
rdata8++;
rx_cnt++;
}
}
}
return rx_cnt;
}
/* Clean all data in RX FIFO of SSP */
void Chip_SSP_Int_FlushData(LPC_SSP_T *pSSP)
{
if (Chip_SSP_GetStatus(pSSP, SSP_STAT_BSY)) {
while (Chip_SSP_GetStatus(pSSP, SSP_STAT_BSY)) {}
}
/* Clear all remaining frames in RX FIFO */
while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE)) {
Chip_SSP_ReceiveFrame(pSSP);
}
/* Clear status */
Chip_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK);
}
/* SSP Interrupt Read/Write with 8-bit frame width */
Status Chip_SSP_Int_RWFrames8Bits(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
{
/* Check overrun error in RIS register */
if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
return ERROR;
}
if ((xf_setup->tx_cnt != xf_setup->length) || (xf_setup->rx_cnt != xf_setup->length)) {
/* check if RX FIFO contains data */
SSP_Read1BFifo(pSSP, xf_setup);
while ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF)) && (xf_setup->tx_cnt != xf_setup->length)) {
/* Write data to buffer */
SSP_Write1BFifo(pSSP, xf_setup);
/* Check overrun error in RIS register */
if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
return ERROR;
}
/* Check for any data available in RX FIFO */
SSP_Read1BFifo(pSSP, xf_setup);
}
return SUCCESS;
}
return ERROR;
}
/* SSP Interrupt Read/Write with 16-bit frame width */
Status Chip_SSP_Int_RWFrames16Bits(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
{
/* Check overrun error in RIS register */
if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
return ERROR;
}
if ((xf_setup->tx_cnt != xf_setup->length) || (xf_setup->rx_cnt != xf_setup->length)) {
/* check if RX FIFO contains data */
SSP_Read2BFifo(pSSP, xf_setup);
while ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF)) && (xf_setup->tx_cnt != xf_setup->length)) {
/* Write data to buffer */
SSP_Write2BFifo(pSSP, xf_setup);
/* Check overrun error in RIS register */
if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
return ERROR;
}
/* Check for any data available in RX FIFO */
SSP_Read2BFifo(pSSP, xf_setup);
}
return SUCCESS;
}
return ERROR;
}
/* Set the SSP operating modes, master or slave */
void Chip_SSP_SetMaster(LPC_SSP_T *pSSP, bool master)
{
if (master) {
Chip_SSP_Set_Mode(pSSP, SSP_MODE_MASTER);
}
else {
Chip_SSP_Set_Mode(pSSP, SSP_MODE_SLAVE);
}
}
/* Set the clock frequency for SSP interface */
void Chip_SSP_SetBitRate(LPC_SSP_T *pSSP, uint32_t bitRate)
{
uint32_t ssp_clk, cr0_div, cmp_clk, prescale;
ssp_clk = Chip_SSP_GetPCLKkRate(pSSP);
cr0_div = 0;
cmp_clk = 0xFFFFFFFF;
prescale = 2;
while (cmp_clk > bitRate) {
cmp_clk = ssp_clk / ((cr0_div + 1) * prescale);
if (cmp_clk > bitRate) {
cr0_div++;
if (cr0_div > 0xFF) {
cr0_div = 0;
prescale += 2;
}
}
}
Chip_SSP_SetClockRate(pSSP, cr0_div, prescale);
}
/* Initialize the SSP */
void Chip_SSP_Init(LPC_SSP_T *pSSP)
{
Chip_Clock_EnablePeriphClock(Chip_SSP_GetClockIndex(pSSP));
Chip_SSP_SetSSPClkDivider(pSSP, 1);
Chip_SYSCTL_PeriphReset(Chip_SSP_GetResetIndex(pSSP));
Chip_SSP_Set_Mode(pSSP, SSP_MODE_MASTER);
Chip_SSP_SetFormat(pSSP, SSP_BITS_8, SSP_FRAMEFORMAT_SPI, SSP_CLOCK_CPHA0_CPOL0);
Chip_SSP_SetBitRate(pSSP, 100000);
}
/* De-initializes the SSP peripheral */
void Chip_SSP_DeInit(LPC_SSP_T *pSSP)
{
Chip_SSP_Disable(pSSP);
Chip_Clock_DisablePeriphClock(Chip_SSP_GetClockIndex(pSSP));
Chip_SSP_SetSSPClkDivider(pSSP, 0);
}

123
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/*
* @brief LPC11XX System Control functions
*
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
#if !defined(LPC11AXX)
/* PDSLEEPCFG register mask */
#define PDSLEEPUSEMASK 0x000018FF
#if defined(CHIP_LPC11XXLV)
#define PDSLEEPMASKTMP (SYSCTL_DEEPSLP_BOD_PD | SYSCTL_DEEPSLP_WDTOSC_PD | \
SYSCTL_DEEPSLP_IRCOUT_PD | SYSCTL_DEEPSLP_IRC_PD)
#else
#define PDSLEEPMASKTMP (SYSCTL_DEEPSLP_BOD_PD | SYSCTL_DEEPSLP_WDTOSC_PD)
#endif
#define PDSLEEPMASK ((PDSLEEPUSEMASK) &~(PDSLEEPMASKTMP))
/* PDWAKECFG register mask */
#if defined(CHIP_LPC11UXX)
#define PDWAKEUPUSEMASK 0x0000E800
#define PDWAKEUPMASKTMP 0x000000FF
#elif defined(CHIP_LPC1125)
#define PDWAKEUPUSEMASK 0x0000ED00
#define PDWAKEUPMASKTMP 0x000000FF
#else
#define PDWAKEUPUSEMASK 0x0000ED00
#define PDWAKEUPMASKTMP 0x000005FF
#endif
#endif /* !defined(LPC11AXX) */
/* PDRUNCFG register mask */
#if defined(CHIP_LPC11AXX)
#define PDRUNCFGUSEMASK 0x00000D08
#define PDRUNCFGMASKTMP 0x0001E0F7
#elif defined(CHIP_LPC11UXX)
#define PDRUNCFGUSEMASK 0x0000E800
#define PDRUNCFGMASKTMP 0x000005FF
#elif defined(CHIP_LPC1125)
#define PDRUNCFGUSEMASK 0x0000ED00
#define PDRUNCFGMASKTMP 0x000000FF
#else
#define PDRUNCFGUSEMASK 0x0000ED00
#define PDRUNCFGMASKTMP 0x000000FF
#endif
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
#if !defined(LPC11AXX)
/* Setup deep sleep behaviour for power down */
void Chip_SYSCTL_SetDeepSleepPD(uint32_t sleepmask)
{
/* Update new value */
LPC_SYSCTL->PDSLEEPCFG = PDSLEEPMASK | (sleepmask & PDSLEEPMASKTMP);
}
/* Setup wakeup behaviour from deep sleep */
void Chip_SYSCTL_SetWakeup(uint32_t wakeupmask)
{
/* Update new value */
LPC_SYSCTL->PDWAKECFG = PDWAKEUPUSEMASK | (wakeupmask & PDWAKEUPMASKTMP);
}
#endif
/* Power down one or more blocks or peripherals */
void Chip_SYSCTL_PowerDown(uint32_t powerdownmask)
{
uint32_t pdrun;
pdrun = LPC_SYSCTL->PDRUNCFG & PDRUNCFGMASKTMP;
pdrun |= (powerdownmask & PDRUNCFGMASKTMP);
LPC_SYSCTL->PDRUNCFG = (pdrun | PDRUNCFGUSEMASK);
}
/* Power up one or more blocks or peripherals */
void Chip_SYSCTL_PowerUp(uint32_t powerupmask)
{
uint32_t pdrun;
pdrun = LPC_SYSCTL->PDRUNCFG & PDRUNCFGMASKTMP;
pdrun &= ~(powerupmask & PDRUNCFGMASKTMP);
LPC_SYSCTL->PDRUNCFG = (pdrun | PDRUNCFGUSEMASK);
}

87
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/*
* @brief LPC11xx Chip specific SystemInit
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
/* Set up and initialize hardware prior to call to main */
void Chip_SystemInit(void)
{
/* IRC should be powered up */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_IRC_PD);
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_IRCOUT_PD);
/* Set system PLL input to main oscillator */
Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_IRC);
/* Power down PLL to change the PLL divider ratio */
Chip_SYSCTL_PowerDown(SYSCTL_POWERDOWN_SYSPLL_PD);
/* Setup PLL for main oscillator rate (FCLKIN = 12MHz) * 4 = 48MHz
MSEL = 3 (this is pre-decremented), PSEL = 1 (for P = 2)
FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 4 = 48MHz
FCCO = FCLKOUT * 2 * P = 48MHz * 2 * 2 = 192MHz (within FCCO range) */
Chip_Clock_SetupSystemPLL(3, 1);
/* Powerup system PLL */
Chip_SYSCTL_PowerUp(SYSCTL_POWERDOWN_SYSPLL_PD);
/* Wait for PLL to lock */
while (!Chip_Clock_IsSystemPLLLocked()) {}
/* Set system clock divider to 1 */
Chip_Clock_SetSysClockDiv(1);
/* Setup FLASH access to 3 clocks */
Chip_FMC_SetFLASHAccess(FLASHTIM_50MHZ_CPU);
/* Set main clock source to the system PLL. This will drive 48MHz
for the main clock and 48MHz for the system clock */
Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_PLLOUT);
/* Enable IOCON clock */
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_IOCON);
}

115
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/*
* @brief 16/32-bit Timer/PWM control functions
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/* Returns clock index for a specific timer referenced by IP block address */
STATIC CHIP_SYSCTL_CLOCK_T Chip_TIMER_GetClock(LPC_TIMER_T *pTMR)
{
CHIP_SYSCTL_CLOCK_T tmrClk;
if (pTMR == LPC_TIMER32_1) {
tmrClk = SYSCTL_CLOCK_CT32B1;
}
else if (pTMR == LPC_TIMER16_0) {
tmrClk = SYSCTL_CLOCK_CT16B0;
}
else if (pTMR == LPC_TIMER16_1) {
tmrClk = SYSCTL_CLOCK_CT16B1;
}
else {
tmrClk = SYSCTL_CLOCK_CT32B0;
}
return tmrClk;
}
/*****************************************************************************
* Public functions
****************************************************************************/
/* Initialize a timer */
void Chip_TIMER_Init(LPC_TIMER_T *pTMR)
{
Chip_Clock_EnablePeriphClock(Chip_TIMER_GetClock(pTMR));
}
/* Shutdown a timer */
void Chip_TIMER_DeInit(LPC_TIMER_T *pTMR)
{
Chip_Clock_DisablePeriphClock(Chip_TIMER_GetClock(pTMR));
}
/* Resets the timer terminal and prescale counts to 0 */
void Chip_TIMER_Reset(LPC_TIMER_T *pTMR)
{
uint32_t reg;
/* Disable timer, set terminal count to non-0 */
reg = pTMR->TCR;
pTMR->TCR = 0;
pTMR->TC = 1;
/* Reset timer counter */
pTMR->TCR = TIMER_RESET;
/* Wait for terminal count to clear */
while (pTMR->TC != 0) {}
/* Restore timer state */
pTMR->TCR = reg;
}
/* Sets external match control (MATn.matchnum) pin control */
void Chip_TIMER_ExtMatchControlSet(LPC_TIMER_T *pTMR, int8_t initial_state,
TIMER_PIN_MATCH_STATE_T matchState, int8_t matchnum)
{
uint32_t mask, reg;
/* Clear bits corresponding to selected match register */
mask = (1 << matchnum) | (0x03 << (4 + (matchnum * 2)));
reg = pTMR->EMR &= ~mask;
/* Set new configuration for selected match register */
pTMR->EMR = reg | (((uint32_t) initial_state) << matchnum) |
(((uint32_t) matchState) << (4 + (matchnum * 2)));
}

281
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/*
* @brief LPC11xx UART chip driver
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
/* Initializes the pUART peripheral */
void Chip_UART_Init(LPC_USART_T *pUART)
{
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_UART0);
Chip_Clock_SetUARTClockDiv(1);
/* Enable FIFOs by default, reset them */
Chip_UART_SetupFIFOS(pUART, (UART_FCR_FIFO_EN | UART_FCR_RX_RS | UART_FCR_TX_RS));
/* Default 8N1, with DLAB disabled */
Chip_UART_ConfigData(pUART, (UART_LCR_WLEN8 | UART_LCR_SBS_1BIT | UART_LCR_PARITY_DIS));
/* Disable fractional divider */
pUART->FDR = 0x10;
}
/* De-initializes the pUART peripheral */
void Chip_UART_DeInit(LPC_USART_T *pUART)
{
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_UART0);
}
/* Transmit a byte array through the UART peripheral (non-blocking) */
int Chip_UART_Send(LPC_USART_T *pUART, const void *data, int numBytes)
{
int sent = 0;
uint8_t *p8 = (uint8_t *) data;
/* Send until the transmit FIFO is full or out of bytes */
while ((sent < numBytes) &&
((Chip_UART_ReadLineStatus(pUART) & UART_LSR_THRE) != 0)) {
Chip_UART_SendByte(pUART, *p8);
p8++;
sent++;
}
return sent;
}
/* Transmit a byte array through the UART peripheral (blocking) */
int Chip_UART_SendBlocking(LPC_USART_T *pUART, const void *data, int numBytes)
{
int pass, sent = 0;
uint8_t *p8 = (uint8_t *) data;
while (numBytes > 0) {
pass = Chip_UART_Send(pUART, p8, numBytes);
numBytes -= pass;
sent += pass;
p8 += pass;
}
return sent;
}
/* Read data through the UART peripheral (non-blocking) */
int Chip_UART_Read(LPC_USART_T *pUART, void *data, int numBytes)
{
int readBytes = 0;
uint8_t *p8 = (uint8_t *) data;
/* Send until the transmit FIFO is full or out of bytes */
while ((readBytes < numBytes) &&
((Chip_UART_ReadLineStatus(pUART) & UART_LSR_RDR) != 0)) {
*p8 = Chip_UART_ReadByte(pUART);
p8++;
readBytes++;
}
return readBytes;
}
/* Read data through the UART peripheral (blocking) */
int Chip_UART_ReadBlocking(LPC_USART_T *pUART, void *data, int numBytes)
{
int pass, readBytes = 0;
uint8_t *p8 = (uint8_t *) data;
while (readBytes < numBytes) {
pass = Chip_UART_Read(pUART, p8, numBytes);
numBytes -= pass;
readBytes += pass;
p8 += pass;
}
return readBytes;
}
/* Determines and sets best dividers to get a target bit rate */
uint32_t Chip_UART_SetBaud(LPC_USART_T *pUART, uint32_t baudrate)
{
uint32_t div, divh, divl, clkin;
/* Determine UART clock in rate without FDR */
clkin = Chip_Clock_GetMainClockRate();
div = clkin / (baudrate * 16);
/* High and low halves of the divider */
divh = div / 256;
divl = div - (divh * 256);
Chip_UART_EnableDivisorAccess(pUART);
Chip_UART_SetDivisorLatches(pUART, divl, divh);
Chip_UART_DisableDivisorAccess(pUART);
/* Fractional FDR alreadt setup for 1 in UART init */
return clkin / div;
}
/* UART receive-only interrupt handler for ring buffers */
void Chip_UART_RXIntHandlerRB(LPC_USART_T *pUART, RINGBUFF_T *pRB)
{
/* New data will be ignored if data not popped in time */
while (Chip_UART_ReadLineStatus(pUART) & UART_LSR_RDR) {
uint8_t ch = Chip_UART_ReadByte(pUART);
RingBuffer_Insert(pRB, &ch);
}
}
/* UART transmit-only interrupt handler for ring buffers */
void Chip_UART_TXIntHandlerRB(LPC_USART_T *pUART, RINGBUFF_T *pRB)
{
uint8_t ch;
/* Fill FIFO until full or until TX ring buffer is empty */
while ((Chip_UART_ReadLineStatus(pUART) & UART_LSR_THRE) != 0 &&
RingBuffer_Pop(pRB, &ch)) {
Chip_UART_SendByte(pUART, ch);
}
}
/* Populate a transmit ring buffer and start UART transmit */
uint32_t Chip_UART_SendRB(LPC_USART_T *pUART, RINGBUFF_T *pRB, const void *data, int bytes)
{
uint32_t ret;
uint8_t *p8 = (uint8_t *) data;
/* Don't let UART transmit ring buffer change in the UART IRQ handler */
Chip_UART_IntDisable(pUART, UART_IER_THREINT);
/* Move as much data as possible into transmit ring buffer */
ret = RingBuffer_InsertMult(pRB, p8, bytes);
Chip_UART_TXIntHandlerRB(pUART, pRB);
/* Add additional data to transmit ring buffer if possible */
ret += RingBuffer_InsertMult(pRB, (p8 + ret), (bytes - ret));
/* Enable UART transmit interrupt */
Chip_UART_IntEnable(pUART, UART_IER_THREINT);
return ret;
}
/* Copy data from a receive ring buffer */
int Chip_UART_ReadRB(LPC_USART_T *pUART, RINGBUFF_T *pRB, void *data, int bytes)
{
(void) pUART;
return RingBuffer_PopMult(pRB, (uint8_t *) data, bytes);
}
/* UART receive/transmit interrupt handler for ring buffers */
void Chip_UART_IRQRBHandler(LPC_USART_T *pUART, RINGBUFF_T *pRXRB, RINGBUFF_T *pTXRB)
{
/* Handle transmit interrupt if enabled */
if (pUART->IER & UART_IER_THREINT) {
Chip_UART_TXIntHandlerRB(pUART, pTXRB);
/* Disable transmit interrupt if the ring buffer is empty */
if (RingBuffer_IsEmpty(pTXRB)) {
Chip_UART_IntDisable(pUART, UART_IER_THREINT);
}
}
/* Handle receive interrupt */
Chip_UART_RXIntHandlerRB(pUART, pRXRB);
}
/* Determines and sets best dividers to get a target baud rate */
uint32_t Chip_UART_SetBaudFDR(LPC_USART_T *pUART, uint32_t baudrate)
{
uint32_t uClk;
uint32_t dval, mval;
uint32_t dl;
uint32_t rate16 = 16 * baudrate;
uint32_t actualRate = 0;
/* Get Clock rate */
uClk = Chip_Clock_GetMainClockRate();
/* The fractional is calculated as (PCLK % (16 * Baudrate)) / (16 * Baudrate)
* Let's make it to be the ratio DivVal / MulVal
*/
dval = uClk % rate16;
/* The PCLK / (16 * Baudrate) is fractional
* => dval = pclk % rate16
* mval = rate16;
* now mormalize the ratio
* dval / mval = 1 / new_mval
* new_mval = mval / dval
* new_dval = 1
*/
if (dval > 0) {
mval = rate16 / dval;
dval = 1;
/* In case mval still bigger then 4 bits
* no adjustment require
*/
if (mval > 12) {
dval = 0;
}
}
dval &= 0xf;
mval &= 0xf;
dl = uClk / (rate16 + rate16 * dval / mval);
/* Update UART registers */
Chip_UART_EnableDivisorAccess(pUART);
Chip_UART_SetDivisorLatches(pUART, UART_LOAD_DLL(dl), UART_LOAD_DLM(dl));
Chip_UART_DisableDivisorAccess(pUART);
/* Set best fractional divider */
pUART->FDR = (UART_FDR_MULVAL(mval) | UART_FDR_DIVADDVAL(dval));
/* Return actual baud rate */
actualRate = uClk / (16 * dl + 16 * dl * dval / mval);
return actualRate;
}

80
basic-setup/components/u8g2/sys/arm/plain/lpc_chip_11uxx_lib/src/wwdt_11xx.c Normal file
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/*
* @brief LPC11xx WWDT chip driver
*
* @note
* Copyright(C) NXP Semiconductors, 2012
* All rights reserved.
*
* @par
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* LPC products. This software is supplied "AS IS" without any warranties of
* any kind, and NXP Semiconductors and its licensor disclaim any and
* all warranties, express or implied, including all implied warranties of
* merchantability, fitness for a particular purpose and non-infringement of
* intellectual property rights. NXP Semiconductors assumes no responsibility
* or liability for the use of the software, conveys no license or rights under any
* patent, copyright, mask work right, or any other intellectual property rights in
* or to any products. NXP Semiconductors reserves the right to make changes
* in the software without notification. NXP Semiconductors also makes no
* representation or warranty that such application will be suitable for the
* specified use without further testing or modification.
*
* @par
* Permission to use, copy, modify, and distribute this software and its
* documentation is hereby granted, under NXP Semiconductors' and its
* licensor's relevant copyrights in the software, without fee, provided that it
* is used in conjunction with NXP Semiconductors microcontrollers. This
* copyright, permission, and disclaimer notice must appear in all copies of
* this code.
*/
#include "chip.h"
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
/* Initialize the Watchdog timer */
void Chip_WWDT_Init(LPC_WWDT_T *pWWDT)
{
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_WDT);
/* Disable watchdog */
pWWDT->MOD = 0;
pWWDT->TC = 0xFF;
#if defined(WATCHDOG_WINDOW_SUPPORT)
pWWDT->WARNINT = 0xFFFF;
pWWDT->WINDOW = 0xFFFFFF;
#endif
}
/* Shutdown the Watchdog timer */
void Chip_WWDT_DeInit(LPC_WWDT_T *pWWDT)
{
Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_WDT);
}
/* Clear WWDT interrupt status flags */
void Chip_WWDT_ClearStatusFlag(LPC_WWDT_T *pWWDT, uint32_t status)
{
if (status & WWDT_WDMOD_WDTOF) {
pWWDT->MOD &= (~WWDT_WDMOD_WDTOF) & WWDT_WDMOD_BITMASK;
}
if (status & WWDT_WDMOD_WDINT) {
pWWDT->MOD |= WWDT_WDMOD_WDINT;
}
}

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#
# Generic and Simple GNU ARM Makefile
#
# Desinged for the gnu-arm-none-eabi tool chain
#
# Features
# - create hex file
# - create assembler listing (.dis)
#
# Limitations
# - only C-files supported
# - no automatic dependency checking (call 'make clean' if any .h files are changed)
#
# Targets:
# make
# create hex file, no upload
# make upload
# create and upload hex file
# make clean
# delete all generated files
#
# Note:
# Display list make database: make -p -f/dev/null | less
#
#================================================
# External tools
# The base directory of gcc-arm-none-eabi
# Can be empty on Ubuntu and installed gcc-arm-none-eabi
# If set, GCCBINPATH must contain a "/" at the end.
GCCBINPATH:=/usr/bin/
#================================================
# Project Information
# The name for the project
TARGETNAME:=plain
# The source files of the project
SRC:=$(wildcard *.c)
# The CPU architecture (will be used for -mcpu)
MCPU:=cortex-m0
# Include directory for the system include files
SYSINC:=../lpc_chip_11uxx_lib/inc
SYSSRC:=$(wildcard ../lpc_chip_11uxx_lib/src/*.c)
# Directory for the linker script
LDSCRIPTDIR:=.
# Name of the linker script (must be the "keep" script, because the other script is not always working)
LDSCRIPT:=lpc11u35.ld
#================================================
# Main part of the Makefile starts here. Usually no changes are needed.
# Internal Variable Names
LIBNAME:=$(TARGETNAME).a
ELFNAME:=$(TARGETNAME).elf
HEXNAME:=$(TARGETNAME).hex
BINNAME:=$(TARGETNAME).bin
DISNAME:=$(TARGETNAME).dis
MAPNAME:=$(TARGETNAME).map
OBJ:=$(SRC:.c=.o) $(SYSSRC:.c=.o)
# Replace standard build tools by avr tools
CC:=$(GCCBINPATH)arm-none-eabi-gcc
AR:=$(GCCBINPATH)arm-none-eabi-ar
OBJCOPY:=$(GCCBINPATH)arm-none-eabi-objcopy
OBJDUMP:=$(GCCBINPATH)arm-none-eabi-objdump
SIZE:=$(GCCBINPATH)arm-none-eabi-size
# Common flags
COMMON_FLAGS = -mthumb -mcpu=$(MCPU)
COMMON_FLAGS += -Wall -I. -I$(SYSINC)
# define stack size (defaults to 0x0100)
# COMMON_FLAGS += -D__STACK_SIZE=0x0100
# define constant for lpcopen library
COMMON_FLAGS += -DCORE_M0
# do not make a call to SystemInit()
# COMMON_FLAGS += -Os -flto
COMMON_FLAGS += -Os
# Do not use stand libs startup code. Uncomment this for gcclib procedures
# memcpy still works, but might be required for __aeabi_uidiv
# COMMON_FLAGS += -nostdlib
# remove unused data and function
COMMON_FLAGS += -ffunction-sections -fdata-sections
# C flags
CFLAGS:=$(COMMON_FLAGS) -std=gnu99
# LD flags
# remove unreferenced procedures and variables, but keep "arm_stack_area" and __isr_vector
GC:=-Wl,--gc-sections -Wl,--undefined=arm_stack_area -Wl,--undefined=__isr_vector
MAP:=-Wl,-Map=$(MAPNAME)
LFLAGS:=$(COMMON_FLAGS) $(GC) $(MAP)
LDLIBS:=--specs=nano.specs -lc -lc -lnosys -L$(LDSCRIPTDIR) -T $(LDSCRIPT)
# Additional Suffixes
.SUFFIXES: .elf .hex .bin .dis
# Targets
.PHONY: all
all: $(DISNAME) $(HEXNAME) $(BINNAME)
$(SIZE) $(ELFNAME)
.PHONY: upload
upload: $(DISNAME) $(HEXNAME) $(ELFNAME) $(BINNAME)
dd bs=1024 conv=nocreat,notrunc if=$(BINNAME) of="/media/$(shell echo $$USER)/CRP DISABLD/firmware.bin"
cp "/media/$(shell echo $$USER)/CRP DISABLD/firmware.bin" tmp.bin
diff tmp.bin $(BINNAME)
$(SIZE) $(ELFNAME)
.PHONY: clean
clean:
$(RM) $(OBJ) $(HEXNAME) $(ELFNAME) $(LIBNAME) $(DISNAME) $(MAPNAME) $(BINNAME)
# implicit rules
.elf.hex:
$(OBJCOPY) -O ihex $< $@
# create the binary version of the new flashfile
# extend the file with 0xff to the size of the flash ROM area
.elf.bin:
$(OBJCOPY) -O binary --gap-fill 255 --pad-to 65536 $< $@
# explicit rules
$(ELFNAME): $(LIBNAME)($(OBJ))
$(LINK.o) $(LFLAGS) $(LIBNAME) $(LDLIBS) -o $@
$(DISNAME): $(ELFNAME)
$(OBJDUMP) -D -S $< > $@

168
basic-setup/components/u8g2/sys/arm/plain/src/lpc11u35.ld Normal file
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/* source: gcc-arm-none-eabi-4_7-2013q1/share/gcc-arm-none-eabi/samples/ldscripts/mem.ld */
/* Linker script to configure memory regions.
* Need modifying for a specific board.
* FLASH.ORIGIN: starting address of flash
* FLASH.LENGTH: length of flash
* RAM.ORIGIN: starting address of RAM bank 0
* RAM.LENGTH: length of RAM bank 0
*/
MEMORY
{
/* LPC11U3x User Manual Page 17 */
FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x10000 /* 64K for LPC11U35 */
RAM (rwx) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* 8K for LPC11U3x */
}
/* source: gcc-arm-none-eabi-4_7-2013q1/share/gcc-arm-none-eabi/samples/ldscripts/sections.ld */
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
/* entry point */
ENTRY(Reset_Handler)
/* extern declaration so that the value appears correctly for the LPC checksum calculation */
EXTERN(NMI_Handler)
EXTERN(HardFault_Handler)
SECTIONS
{
.text :
{
KEEP(*(.isr_vector))
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
__etext = .;
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM
.bss :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > RAM
.heap (COPY):
{
__end__ = .;
end = __end__;
*(.heap*)
__HeapLimit = .;
} > RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
*(.stack*)
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
/* http://www.lpcware.com/content/forum/lpc1788-flash-signature-generation */
/* section 20.7/page 390 of the LPC11U3x User Manual */
LPC_checksum = 0- (__StackTop + Reset_Handler + NMI_Handler + HardFault_Handler + 3 /* three entries */);
}

18
basic-setup/components/u8g2/sys/arm/plain/src/make.bat Executable file
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rem make.bat
rem
rem Create lpc810_led_driver.hex file on windows operating system.
rem Requires https://launchpad.net/gcc-arm-embedded/ <20>Win32 Installer<65>
rem
set GNUARMPATH="C:\Program Files (x86)\GNU Tools ARM Embedded"
set GCC=%GNUARMPATH%\bin\arm-none-eabi-gcc.exe
set OBJCOPY=%GNUARMPATH%\bin\arm-none-eabi-objcopy.exe
set CCFLAGS=-DCORE_M0PLUS -Os -flto -mthumb -mcpu=cortex-m0 -Wall -ffunction-sections -fdata-sections -std=gnu99
set LDFLAGS=-Wl,--gc-sections -Wl,--undefined=arm_stack_area -Wl,--undefined=__isr_vector
set LIBS=--specs=nano.specs -lc -lc -lnosys -L. -T lpc810.ld
set GCCINC=-I. -I..\lpc_chip_8xx_lib\inc
set EXTDIR=..\lpc_chip_8xx_lib\src
set EXTSRC=%EXTDIR%\acmp_8xx.c %EXTDIR%\sct_8xx.c %EXTDIR%\swm_8xx.c %EXTDIR%\gpio_8xx.c %EXTDIR%\pmu_8xx.c
set EXTSRC=%EXTSRC% %EXTDIR%\iocon_8xx.c %EXTDIR%\syscon_8xx.c
%GCC% %GCCINC% %CCFLAGS% lpc810_led_driver.c %EXTSRC% %LDFLAGS% %LIBS% -o lpc810_led_driver.elf
%OBJCOPY% -O ihex lpc810_led_driver.elf lpc810_led_driver.hex

210
basic-setup/components/u8g2/sys/arm/plain/src/plain.c Normal file
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/*
Include LPC11U3x Chip Library
The chip library can be downloaded from LPCOpen
and is included in the file
lpcopen_v2_03_lpcxpresso_nxp_lpcxpresso_11u37h.zip
*/
#include <chip.h>
#define SYS_CORE_CLOCK 12000000UL
#define SYS_TICK_PERIOD_IN_MS 100
/*=======================================================================*/
/* system procedures and sys tick master task */
volatile uint32_t sys_tick_irq_cnt=0;
void __attribute__ ((interrupt)) SysTick_Handler(void)
{
sys_tick_irq_cnt++;
}
/*
setup the hardware and start interrupts.
called by "Reset_Handler"
*/
int __attribute__ ((noinline)) main(void)
{
/* set systick and start systick interrupt */
SysTick_Config(SYS_CORE_CLOCK/1000UL*(unsigned long)SYS_TICK_PERIOD_IN_MS);
/* turn on GPIO */
Chip_GPIO_Init(LPC_GPIO);
/* turn on IOCON */
Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_IOCON);
Chip_GPIO_SetPinDIROutput(LPC_GPIO, 0, 7); /* port 0, pin 7: LED on eHaJo Breakout Board */
for(;;)
{
uint32_t t;
Chip_GPIO_SetPinOutHigh(LPC_GPIO, 0, 7);
t = sys_tick_irq_cnt;
while( sys_tick_irq_cnt == t )
;
Chip_GPIO_SetPinOutLow(LPC_GPIO, 0, 7);
t = sys_tick_irq_cnt;
while( sys_tick_irq_cnt == t )
;
}
/* enter sleep mode: Reduce from 1.4mA to 0.8mA with 12MHz */
while (1)
{
SCB->SCR |= (1UL << SCB_SCR_SLEEPONEXIT_Pos); /* enter sleep mode after interrupt */
Chip_PMU_SleepState(LPC_PMU); /* enter sleep mode now */
}
}
/*=======================================================================*/
/*
Reserve some space for the stack. This is used to check if global variables + stack exceed RAM size.
If -Wl,--gc-sections is used, then also define -Wl,--undefined=arm_stack_area to keep the variable in RAM.
The name of the variable (here: arm_stack_area) does not matter.
Heap (=dynamic memory allocation) is not supported
*/
#ifndef __STACK_SIZE
#define __STACK_SIZE 0x100
#endif
unsigned char arm_stack_area[__STACK_SIZE] __attribute__ ((section(".stack"))) __attribute__ ((aligned(8)));
/*=======================================================================*/
/* isr system procedures */
/* make the top of the stack known to the c compiler, value will be calculated by the linker script */
void __StackTop(void);
void __attribute__ ((interrupt)) __attribute__ ((noreturn)) Reset_Handler(void)
{
register unsigned long *ptr;
register unsigned long *start;
register unsigned long *end;
/*
Loop to copy data from read only memory to RAM. The ranges
of copy from/to are specified by following symbols evaluated in
linker script.
__etext: End of code section, i.e., begin of data sections to copy from.
__data_start__/__data_end__: RAM address range that data should be
copied to. Both must be aligned to 4 bytes boundary.
*/
extern unsigned long __data_start__[];
extern unsigned long __data_end__[];
extern unsigned long __etext[];
ptr = __etext;
start = __data_start__;
end = __data_end__;
while( start < end )
{
*start = *ptr;
start++;
ptr++;
}
/*
Loop to zero out BSS section, which uses following symbols
in linker script:
__bss_start__: start of BSS section. Must align to 4
__bss_end__: end of BSS section. Must align to 4
*/
extern unsigned long __bss_start__[];
extern unsigned long __bss_end__[];
ptr = __bss_start__;
end = __bss_end__;
while( ptr < end )
{
*ptr = 0;
ptr++;
}
/* Call main procedure */
main();
/* finished, do nothing. */
for(;;)
;
}
/* "NMI_Handler" is used in the ld script to calculate the checksum */
void __attribute__ ((interrupt)) NMI_Handler(void)
{
}
/* "HardFault_Handler" is used in the ld script to calculate the checksum */
void __attribute__ ((interrupt)) HardFault_Handler(void)
{
}
/* make the checksum known to the c compiler, value will be calculated by the linker script */
void LPC_checksum(void);
/*=======================================================================*/
/* isr vector */
/* see page 445 of the LPC11U3x user manual */
/* see also enum LPC11UXX_IRQn in isr/cmsis_11uxx.h */
typedef void (*isr_handler_t)(void);
isr_handler_t __isr_vector[48] __attribute__ ((section(".isr_vector"))) __attribute__ ((aligned(4)))=
{
__StackTop, /* 0x00: Top of Stack, calculated by the linker script */
Reset_Handler, /* 0x04: Reset Handler, DO NOT CHANGE THE ISR NAME (used for LPC_checksum calculation) */
NMI_Handler, /* 0x08: NMI Handler, DO NOT CHANGE THE ISR NAME (used for LPC_checksum calculation) */
HardFault_Handler, /* 0x0c: Hard Fault Handler, DO NOT CHANGE THE ISR NAME (used for LPC_checksum calculation) */
0, /* 0x10: Reserved, must be 0 */
0, /* 0x14: Reserved, must be 0 */
0, /* 0x18: Reserved, must be 0 */
LPC_checksum, /* 0x1c: Checksum, calculated by the linker script or the flash utility */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* SVCall Handler */
0, /* Reserved */
0, /* Reserved */
0, /* PendSV Handler */
SysTick_Handler, /* SysTick Handler */
0, /* PIN_INT0_IRQn = 0, Pin Interrupt 0 */
0, /* PIN_INT1_IRQn = 1, Pin Interrupt 1 */
0, /* PIN_INT2_IRQn = 2, Pin Interrupt 2 */
0, /* PIN_INT3_IRQn = 3, Pin Interrupt 3 */
0, /* PIN_INT4_IRQn = 4, Pin Interrupt 4 */
0, /* PIN_INT5_IRQn = 5, Pin Interrupt 5 */
0, /* PIN_INT6_IRQn = 6, Pin Interrupt 6 */
0, /* PIN_INT7_IRQn = 7, Pin Interrupt 7 */
0, /* GINT0_IRQn = 8, GPIO GROUP 0 interrupt */
0, /* GINT1_IRQn = 9, GPIO GROUP 1 interrupt */
0, /* Reserved10_IRQn = 10, Reserved Interrupt */
0, /* Reserved11_IRQn = 11, */
0, /* Reserved12_IRQn = 12, */
0, /* Reserved13_IRQn = 13, */
0, /* SSP1_IRQn = 14, SSP1 Interrupt */
0, /* I2C0_IRQn = 15, I2C Interrupt */
0, /* TIMER_16_0_IRQn = 16, 16-bit Timer0 Interrupt */
0, /* TIMER_16_1_IRQn = 17, 16-bit Timer1 Interrupt */
0, /* TIMER_32_0_IRQn = 18, 32-bit Timer0 Interrupt */
0, /* TIMER_32_1_IRQn = 19, 32-bit Timer1 Interrupt */
0, /* SSP0_IRQn = 20, SSP0 Interrupt */
0, /* UART0_IRQn = 21, UART Interrupt */
0, /* USB0_IRQn = 22, USB IRQ interrupt */
0, /* USB0_FIQ_IRQn = 23, USB FIQ interrupt */
0, /* ADC_IRQn = 24, A/D Converter Interrupt */
0, /* WDT_IRQn = 25, Watchdog timer Interrupt */
0, /* BOD_IRQn = 26, Brown Out Detect(BOD) Interrupt */
0, /* FMC_IRQn = 27, Flash Memory Controller Interrupt */
0, /* RESERVED28_IRQn = 28, */
0, /* RESERVED29_IRQn = 29, */
0, /* USB_WAKEUP_IRQn = 30, USB wake-up interrupt Interrupt */
0 /* IOH_IRQn = 31, I/O Handler IRQ (Only for LPC11U37) */
};