diff --git a/doc/arduino-mega-rfid-rc522-wiring.markdown b/doc/arduino-mega-rfid-rc522-wiring.markdown
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@@ -0,0 +1,25 @@
+# Arduino Mega RFID-RC522 wiring
+
+## Introduction
+
+**NB! RFID-RC522 requires only 3.3 V DC input voltage. Never connect it to 5V input.**
+
+
+
+## Wiring illustration
+
+
+
+## Wiring table
+
+| Signal | ATMega2560 port and pin | Arduino Mega 2560 pin | 5V to 3V converter | RFID-RC522 | Wire colour in illustration |
+| --- | --- | --- | --- | --- | --- |
+| Slave select | PORTB 0 | 53 | - | SDA | White |
+| SPI clock | PORTB 1 | 52 | - | SCK | Orange |
+| Master out slave in | PORTB 2 | 51 | - | MOSI | Green |
+| Master in slave out | PORTB 3 | 50 | - | MISO | Yellow |
+| RF522 reset | PORTL 0 | 49 | - | RST | Brown |
+| Ground | GND | GND | GND | GND | Black |
+| 5 V DC | - | 5V | VIN | - | Red |
+| 3,3 V DC | - | - | VOUT | 3.3 V | Red |
+
diff --git a/doc/arduino-mega-rfid-rc522-wiring.png b/doc/arduino-mega-rfid-rc522-wiring.png
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index 0000000..d3ae3c0
Binary files /dev/null and b/doc/arduino-mega-rfid-rc522-wiring.png differ
diff --git a/lib/matejx_avr_lib/README.txt b/lib/matejx_avr_lib/README.txt
new file mode 100755
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--- /dev/null
+++ b/lib/matejx_avr_lib/README.txt
@@ -0,0 +1,2 @@
+
+Library homepage is at www.randomport.com
diff --git a/lib/matejx_avr_lib/hwdefs.h b/lib/matejx_avr_lib/hwdefs.h
new file mode 100644
index 0000000..691753e
--- /dev/null
+++ b/lib/matejx_avr_lib/hwdefs.h
@@ -0,0 +1,20 @@
+#ifndef MAT_HWDEFS_H
+#define MAT_HWDEFS_H
+
+#define DDR(x) (*(&x - 1))
+#define PIN(x) (*(&x - 2))
+
+#define MFRC522_SS_PORT PORTB
+#define MFRC522_SS_BIT 0
+
+#define MFRC522_RST_PORT PORTL
+#define MFRC522_RST_BIT 0
+
+#define SCK_DDR DDRB
+#define SCK_BIT DDB1
+#define MOSI_DDR DDRB
+#define MOSI_BIT DDB2
+#define MISO_DDR DDRB
+#define MISO_BIT DDB3
+
+#endif
\ No newline at end of file
diff --git a/lib/matejx_avr_lib/hwdefs_minimal.h b/lib/matejx_avr_lib/hwdefs_minimal.h
new file mode 100755
index 0000000..6b4cce4
--- /dev/null
+++ b/lib/matejx_avr_lib/hwdefs_minimal.h
@@ -0,0 +1,7 @@
+#ifndef MAT_HWDEFS_H
+#define MAT_HWDEFS_H
+
+ #define DDR(x) (*(&x - 1))
+ #define PIN(x) (*(&x - 2))
+
+#endif
diff --git a/lib/matejx_avr_lib/mfrc522.c b/lib/matejx_avr_lib/mfrc522.c
new file mode 100755
index 0000000..5171a63
--- /dev/null
+++ b/lib/matejx_avr_lib/mfrc522.c
@@ -0,0 +1,1390 @@
+/**
+@file mfrc522.c
+@brief MFRC522 Mifare routines
+@author Matej Kogovsek (matej@hamradio.si)
+@copyright LGPL 2.1
+@note This file is part of mat-avr-lib
+@note This file was not written by me from scratch. It was adapted from code by Miguel Balboa at https://github.com/miguelbalboa/rfid
+*/
+
+#include
+#include
+#include
+
+#include "mfrc522.h"
+#include "spi.h"
+#include "hwdefs.h"
+
+#define SPI_CS_LOW MFRC522_SS_PORT &= ~_BV(MFRC522_SS_BIT)
+#define SPI_CS_HIGH MFRC522_SS_PORT |= _BV(MFRC522_SS_BIT)
+
+static const byte FIFO_SIZE = 64; // The FIFO is 64 bytes.
+
+void MFRC522_init() {
+ // Set the chipSelectPin as digital output, do not select the slave yet
+ DDR(MFRC522_SS_PORT) |= _BV(MFRC522_SS_BIT);
+ SPI_CS_HIGH;
+
+ // Set the resetPowerDownPin as digital output, do not reset or power down.
+ DDR(MFRC522_RST_PORT) |= _BV(MFRC522_RST_BIT);
+ MFRC522_RST_PORT |= _BV(MFRC522_RST_BIT);
+
+ // Set SPI bus to work with MFRC522 chip.
+ spi_init(1);
+}
+
+
+//-----------------------------------------------------------------------------------
+// Basic interface functions for communicating with the MFRC522
+//-----------------------------------------------------------------------------------
+
+/**
+ * Writes a byte to the specified register in the MFRC522 chip.
+ * The interface is described in the datasheet section 8.1.2.
+ */
+void PCD_WriteRegister( byte reg, ///< The register to write to. One of the PCD_Register enums.
+ byte value ///< The value to write.
+) {
+ SPI_CS_LOW; // Select slave
+ spi_rw(reg & 0x7E); // MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3.
+ spi_rw(value);
+ SPI_CS_HIGH; // Release slave again
+}
+
+/**
+ * Writes a number of bytes to the specified register in the MFRC522 chip.
+ * The interface is described in the datasheet section 8.1.2.
+ */
+void PCD_WriteRegister2(byte reg, ///< The register to write to. One of the PCD_Register enums.
+ byte count, ///< The number of bytes to write to the register
+ byte *values ///< The values to write. Byte array.
+) {
+ SPI_CS_LOW; // Select slave
+ spi_rw(reg & 0x7E); // MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3.
+ for (byte index = 0; index < count; index++) {
+ spi_rw(values[index]);
+ }
+ SPI_CS_HIGH; // Release slave again
+}
+
+/**
+ * Reads a byte from the specified register in the MFRC522 chip.
+ * The interface is described in the datasheet section 8.1.2.
+ */
+byte PCD_ReadRegister(byte reg ///< The register to read from. One of the PCD_Register enums.
+) {
+ byte value;
+ SPI_CS_LOW; // Select slave
+ spi_rw(0x80 | (reg & 0x7E)); // MSB == 1 is for reading. LSB is not used in address. Datasheet section 8.1.2.3.
+ value = spi_rw(0); // Read the value back. Send 0 to stop reading.
+ SPI_CS_HIGH; // Release slave again
+ return value;
+}
+
+/**
+ * Reads a number of bytes from the specified register in the MFRC522 chip.
+ * The interface is described in the datasheet section 8.1.2.
+ */
+void PCD_ReadRegister2( byte reg, ///< The register to read from. One of the PCD_Register enums.
+ byte count, ///< The number of bytes to read
+ byte *values, ///< Byte array to store the values in.
+ byte rxAlign ///< Only bit positions rxAlign..7 in values[0] are updated.
+) {
+ if (count == 0) {
+ return;
+ }
+ byte address = 0x80 | (reg & 0x7E); // MSB == 1 is for reading. LSB is not used in address. Datasheet section 8.1.2.3.
+ byte index = 0; // Index in values array.
+ SPI_CS_LOW; // Select slave
+ count--; // One read is performed outside of the loop
+ spi_rw(address); // Tell MFRC522 which address we want to read
+ while (index < count) {
+ if (index == 0 && rxAlign) { // Only update bit positions rxAlign..7 in values[0]
+ // Create bit mask for bit positions rxAlign..7
+ byte mask = 0;
+ for (byte i = rxAlign; i <= 7; i++) {
+ mask |= (1 << i);
+ }
+ // Read value and tell that we want to read the same address again.
+ byte value = spi_rw(address);
+ // Apply mask to both current value of values[0] and the new data in value.
+ values[0] = (values[index] & ~mask) | (value & mask);
+ }
+ else { // Normal case
+ values[index] = spi_rw(address); // Read value and tell that we want to read the same address again.
+ }
+ index++;
+ }
+ values[index] = spi_rw(0); // Read the final byte. Send 0 to stop reading.
+ SPI_CS_HIGH; // Release slave again
+}
+
+/**
+ * Sets the bits given in mask in register reg.
+ */
+void PCD_SetRegisterBitMask(byte reg, ///< The register to update. One of the PCD_Register enums.
+ byte mask ///< The bits to set.
+) {
+ byte tmp;
+ tmp = PCD_ReadRegister(reg);
+ PCD_WriteRegister(reg, tmp | mask); // set bit mask
+}
+
+/**
+ * Clears the bits given in mask from register reg.
+ */
+void PCD_ClearRegisterBitMask( byte reg, ///< The register to update. One of the PCD_Register enums.
+ byte mask ///< The bits to clear.
+) {
+ byte tmp;
+ tmp = PCD_ReadRegister(reg);
+ PCD_WriteRegister(reg, tmp & (~mask)); // clear bit mask
+}
+
+
+/**
+ * Use the CRC coprocessor in the MFRC522 to calculate a CRC_A.
+ *
+ * @return STATUS_OK on success, STATUS_??? otherwise.
+ */
+byte PCD_CalculateCRC( byte *data, ///< In: Pointer to the data to transfer to the FIFO for CRC calculation.
+ byte length, ///< In: The number of bytes to transfer.
+ byte *result ///< Out: Pointer to result buffer. Result is written to result[0..1], low byte first.
+) {
+ PCD_WriteRegister(CommandReg, PCD_Idle); // Stop any active command.
+ PCD_WriteRegister(DivIrqReg, 0x04); // Clear the CRCIRq interrupt request bit
+ PCD_SetRegisterBitMask(FIFOLevelReg, 0x80); // FlushBuffer = 1, FIFO initialization
+ PCD_WriteRegister2(FIFODataReg, length, data); // Write data to the FIFO
+ PCD_WriteRegister(CommandReg, PCD_CalcCRC); // Start the calculation
+
+ // Wait for the CRC calculation to complete. Each iteration of the while-loop takes 17.73µs.
+ word i = 5000;
+ byte n;
+ while (1) {
+ n = PCD_ReadRegister(DivIrqReg); // DivIrqReg[7..0] bits are: Set2 reserved reserved MfinActIRq reserved CRCIRq reserved reserved
+ if (n & 0x04) { // CRCIRq bit set - calculation done
+ break;
+ }
+ if (--i == 0) { // The emergency break. We will eventually terminate on this one after 89ms. Communication with the MFRC522 might be down.
+ return STATUS_TIMEOUT;
+ }
+ }
+ PCD_WriteRegister(CommandReg, PCD_Idle); // Stop calculating CRC for new content in the FIFO.
+
+ // Transfer the result from the registers to the result buffer
+ result[0] = PCD_ReadRegister(CRCResultRegL);
+ result[1] = PCD_ReadRegister(CRCResultRegH);
+ return STATUS_OK;
+}
+
+
+//-----------------------------------------------------------------------------------
+// Functions for manipulating the MFRC522
+//-----------------------------------------------------------------------------------
+
+/**
+ * Initializes the MFRC522 chip.
+ */
+byte PCD_Init() {
+ if ( 0 == (MFRC522_RST_PORT & _BV(MFRC522_RST_BIT)) ) { //The MFRC522 chip is in power down mode.
+ MFRC522_RST_PORT |= _BV(MFRC522_RST_BIT); // Exit power down mode. This triggers a hard reset.
+ // Section 8.8.2 in the datasheet says the oscillator start-up time is the start up time of the crystal + 37,74µs. Let us be generous: 50ms.
+ _delay_ms(50);
+ }
+ else { // Perform a soft reset
+ if( STATUS_OK != PCD_Reset() ) {
+ return STATUS_TIMEOUT;
+ }
+ }
+ // When communicating with a PICC we need a timeout if something goes wrong.
+ // f_timer = 13.56 MHz / (2*TPreScaler+1) where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo].
+ // TPrescaler_Hi are the four low bits in TModeReg. TPrescaler_Lo is TPrescalerReg.
+ PCD_WriteRegister(TModeReg, 0x80); // TAuto=1; timer starts automatically at the end of the transmission in all communication modes at all speeds
+ PCD_WriteRegister(TPrescalerReg, 0xA9); // TPreScaler = TModeReg[3..0]:TPrescalerReg, ie 0x0A9 = 169 => f_timer=40kHz, ie a timer period of 25µs.
+ PCD_WriteRegister(TReloadRegH, 0x03); // Reload timer with 0x3E8 = 1000, ie 25ms before timeout.
+ PCD_WriteRegister(TReloadRegL, 0xE8);
+
+ PCD_WriteRegister(TxASKReg, 0x40); // Default 0x00. Force a 100 % ASK modulation independent of the ModGsPReg register setting
+ PCD_WriteRegister(ModeReg, 0x3D); // Default 0x3F. Set the preset value for the CRC coprocessor for the CalcCRC command to 0x6363 (ISO 14443-3 part 6.2.4)
+ PCD_AntennaOn(); // Enable the antenna driver pins TX1 and TX2 (they were disabled by the reset)
+
+ return STATUS_OK;
+}
+
+/**
+ * Performs a soft reset on the MFRC522 chip and waits for it to be ready again.
+ */
+byte PCD_Reset() {
+ PCD_WriteRegister(CommandReg, PCD_SoftReset); // Issue the SoftReset command.
+ // The datasheet does not mention how long the SoftRest command takes to complete.
+ // But the MFRC522 might have been in soft power-down mode (triggered by bit 4 of CommandReg)
+ // Section 8.8.2 in the datasheet says the oscillator start-up time is the start up time of the crystal + 37,74µs. Let us be generous: 50ms.
+ _delay_ms(50);
+ // Wait for the PowerDown bit in CommandReg to be cleared
+ word i = 5000;
+ while (PCD_ReadRegister(CommandReg) & (1<<4)) {
+ // PCD still restarting - unlikely after waiting 50ms, but better safe than sorry.
+ if( --i == 0 ) {
+ return STATUS_TIMEOUT;
+ }
+ }
+ return STATUS_OK;
+}
+
+/**
+ * Turns the antenna on by enabling pins TX1 and TX2.
+ * After a reset these pins disabled.
+ */
+void PCD_AntennaOn() {
+ byte value = PCD_ReadRegister(TxControlReg);
+ if ((value & 0x03) != 0x03) {
+ PCD_WriteRegister(TxControlReg, value | 0x03);
+ }
+}
+
+//-----------------------------------------------------------------------------------
+// Functions for communicating with PICCs
+//-----------------------------------------------------------------------------------
+
+/**
+ * Executes the Transceive command.
+ * CRC validation can only be done if backData and backLen are specified.
+ *
+ * @return STATUS_OK on success, STATUS_??? otherwise.
+ */
+byte PCD_TransceiveData( byte *sendData, ///< Pointer to the data to transfer to the FIFO.
+ byte sendLen, ///< Number of bytes to transfer to the FIFO.
+ byte *backData, ///< NULL or pointer to buffer if data should be read back after executing the command.
+ byte *backLen, ///< In: Max number of bytes to write to *backData. Out: The number of bytes returned.
+ byte *validBits, ///< In/Out: The number of valid bits in the last byte. 0 for 8 valid bits. Default NULL.
+ byte rxAlign, ///< In: Defines the bit position in backData[0] for the first bit received. Default 0.
+ bool checkCRC ///< In: True => The last two bytes of the response is assumed to be a CRC_A that must be validated.
+) {
+ byte waitIRq = 0x30; // RxIRq and IdleIRq
+ return PCD_CommunicateWithPICC(PCD_Transceive, waitIRq, sendData, sendLen, backData, backLen, validBits, rxAlign, checkCRC);
+}
+
+/**
+ * Transfers data to the MFRC522 FIFO, executes a command, waits for completion and transfers data back from the FIFO.
+ * CRC validation can only be done if backData and backLen are specified.
+ *
+ * @return STATUS_OK on success, STATUS_??? otherwise.
+ */
+byte PCD_CommunicateWithPICC( byte command, ///< The command to execute. One of the PCD_Command enums.
+ byte waitIRq, ///< The bits in the ComIrqReg register that signals successful completion of the command.
+ byte *sendData, ///< Pointer to the data to transfer to the FIFO.
+ byte sendLen, ///< Number of bytes to transfer to the FIFO.
+ byte *backData, ///< NULL or pointer to buffer if data should be read back after executing the command.
+ byte *backLen, ///< In: Max number of bytes to write to *backData. Out: The number of bytes returned.
+ byte *validBits, ///< In/Out: The number of valid bits in the last byte. 0 for 8 valid bits.
+ byte rxAlign, ///< In: Defines the bit position in backData[0] for the first bit received. Default 0.
+ bool checkCRC ///< In: True => The last two bytes of the response is assumed to be a CRC_A that must be validated.
+) {
+ byte n, _validBits = 0;
+ unsigned int i;
+
+ // Prepare values for BitFramingReg
+ byte txLastBits = validBits ? *validBits : 0;
+ byte bitFraming = (rxAlign << 4) + txLastBits; // RxAlign = BitFramingReg[6..4]. TxLastBits = BitFramingReg[2..0]
+
+ PCD_WriteRegister(CommandReg, PCD_Idle); // Stop any active command.
+ PCD_WriteRegister(ComIrqReg, 0x7F); // Clear all seven interrupt request bits
+ PCD_SetRegisterBitMask(FIFOLevelReg, 0x80); // FlushBuffer = 1, FIFO initialization
+ PCD_WriteRegister2(FIFODataReg, sendLen, sendData); // Write sendData to the FIFO
+ PCD_WriteRegister(BitFramingReg, bitFraming); // Bit adjustments
+ PCD_WriteRegister(CommandReg, command); // Execute the command
+ if (command == PCD_Transceive) {
+ PCD_SetRegisterBitMask(BitFramingReg, 0x80); // StartSend=1, transmission of data starts
+ }
+
+ // Wait for the command to complete.
+ // In PCD_Init() we set the TAuto flag in TModeReg. This means the timer automatically starts when the PCD stops transmitting.
+ // Each iteration of the do-while-loop takes 17.86µs.
+ i = 2000;
+ while (1) {
+ n = PCD_ReadRegister(ComIrqReg); // ComIrqReg[7..0] bits are: Set1 TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq TimerIRq
+ if (n & waitIRq) { // One of the interrupts that signal success has been set.
+ break;
+ }
+ if (n & 0x01) { // Timer interrupt - nothing received in 25ms
+ return STATUS_TIMEOUT;
+ }
+ if (--i == 0) { // The emergency break. If all other condions fail we will eventually terminate on this one after 35.7ms. Communication with the MFRC522 might be down.
+ return STATUS_TIMEOUT;
+ }
+ }
+
+ // Stop now if any errors except collisions were detected.
+ byte errorRegValue = PCD_ReadRegister(ErrorReg); // ErrorReg[7..0] bits are: WrErr TempErr reserved BufferOvfl CollErr CRCErr ParityErr ProtocolErr
+ if (errorRegValue & 0x13) { // BufferOvfl ParityErr ProtocolErr
+ return STATUS_ERROR;
+ }
+
+ // If the caller wants data back, get it from the MFRC522.
+ if (backData && backLen) {
+ n = PCD_ReadRegister(FIFOLevelReg); // Number of bytes in the FIFO
+ if (n > *backLen) {
+ return STATUS_NO_ROOM;
+ }
+ *backLen = n; // Number of bytes returned
+ PCD_ReadRegister2(FIFODataReg, n, backData, rxAlign); // Get received data from FIFO
+ _validBits = PCD_ReadRegister(ControlReg) & 0x07; // RxLastBits[2:0] indicates the number of valid bits in the last received byte. If this value is 000b, the whole byte is valid.
+ if (validBits) {
+ *validBits = _validBits;
+ }
+ }
+
+ // Tell about collisions
+ if (errorRegValue & 0x08) { // CollErr
+ return STATUS_COLLISION;
+ }
+
+ // Perform CRC_A validation if requested.
+ if (backData && backLen && checkCRC) {
+ // In this case a MIFARE Classic NAK is not OK.
+ if (*backLen == 1 && _validBits == 4) {
+ return STATUS_MIFARE_NACK;
+ }
+ // We need at least the CRC_A value and all 8 bits of the last byte must be received.
+ if (*backLen < 2 || _validBits != 0) {
+ return STATUS_CRC_WRONG;
+ }
+ // Verify CRC_A - do our own calculation and store the control in controlBuffer.
+ byte controlBuffer[2];
+ n = PCD_CalculateCRC(&backData[0], *backLen - 2, &controlBuffer[0]);
+ if (n != STATUS_OK) {
+ return n;
+ }
+ if ((backData[*backLen - 2] != controlBuffer[0]) || (backData[*backLen - 1] != controlBuffer[1])) {
+ return STATUS_CRC_WRONG;
+ }
+ }
+
+ return STATUS_OK;
+}
+
+/**
+ * Transmits a REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
+ * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
+ *
+ * @return STATUS_OK on success, STATUS_??? otherwise.
+ */
+byte PICC_RequestA( byte *bufferATQA, ///< The buffer to store the ATQA (Answer to request) in
+ byte *bufferSize ///< Buffer size, at least two bytes. Also number of bytes returned if STATUS_OK.
+) {
+ return PICC_REQA_or_WUPA(PICC_CMD_REQA, bufferATQA, bufferSize);
+}
+
+/**
+ * Transmits a Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
+ * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
+ *
+ * @return STATUS_OK on success, STATUS_??? otherwise.
+ */
+byte PICC_WakeupA( byte *bufferATQA, ///< The buffer to store the ATQA (Answer to request) in
+ byte *bufferSize ///< Buffer size, at least two bytes. Also number of bytes returned if STATUS_OK.
+) {
+ return PICC_REQA_or_WUPA(PICC_CMD_WUPA, bufferATQA, bufferSize);
+}
+
+/**
+ * Transmits REQA or WUPA commands.
+ * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
+ *
+ * @return STATUS_OK on success, STATUS_??? otherwise.
+ */
+byte PICC_REQA_or_WUPA( byte command, ///< The command to send - PICC_CMD_REQA or PICC_CMD_WUPA
+ byte *bufferATQA, ///< The buffer to store the ATQA (Answer to request) in
+ byte *bufferSize ///< Buffer size, at least two bytes. Also number of bytes returned if STATUS_OK.
+) {
+ byte validBits;
+ byte status;
+
+ if (bufferATQA == NULL || *bufferSize < 2) { // The ATQA response is 2 bytes long.
+ return STATUS_NO_ROOM;
+ }
+ PCD_ClearRegisterBitMask(CollReg, 0x80); // ValuesAfterColl=1 => Bits received after collision are cleared.
+ validBits = 7; // For REQA and WUPA we need the short frame format - transmit only 7 bits of the last (and only) byte. TxLastBits = BitFramingReg[2..0]
+ status = PCD_TransceiveData(&command, 1, bufferATQA, bufferSize, &validBits, 0, 0);
+ if (status != STATUS_OK) {
+ return status;
+ }
+ if (*bufferSize != 2 || validBits != 0) { // ATQA must be exactly 16 bits.
+ return STATUS_ERROR;
+ }
+ return STATUS_OK;
+}
+
+/**
+ * Transmits SELECT/ANTICOLLISION commands to select a single PICC.
+ * Before calling this function the PICCs must be placed in the READY(*) state by calling PICC_RequestA() or PICC_WakeupA().
+ * On success:
+ * - The chosen PICC is in state ACTIVE(*) and all other PICCs have returned to state IDLE/HALT. (Figure 7 of the ISO/IEC 14443-3 draft.)
+ * - The UID size and value of the chosen PICC is returned in *uid along with the SAK.
+ *
+ * A PICC UID consists of 4, 7 or 10 bytes.
+ * Only 4 bytes can be specified in a SELECT command, so for the longer UIDs two or three iterations are used:
+ * UID size Number of UID bytes Cascade levels Example of PICC
+ * ======== =================== ============== ===============
+ * single 4 1 MIFARE Classic
+ * double 7 2 MIFARE Ultralight
+ * triple 10 3 Not currently in use?
+ *
+ * @return STATUS_OK on success, STATUS_??? otherwise.
+ */
+byte PICC_Select( Uid *uid, ///< Pointer to Uid struct. Normally output, but can also be used to supply a known UID.
+ byte validBits ///< The number of known UID bits supplied in *uid. Normally 0. If set you must also supply uid->size.
+) {
+ bool uidComplete;
+ bool selectDone;
+ bool useCascadeTag;
+ byte cascadeLevel = 1;
+ byte result;
+ byte count;
+ byte index;
+ byte uidIndex; // The first index in uid->uidByte[] that is used in the current Cascade Level.
+ char currentLevelKnownBits; // The number of known UID bits in the current Cascade Level.
+ byte buffer[9]; // The SELECT/ANTICOLLISION commands uses a 7 byte standard frame + 2 bytes CRC_A
+ byte bufferUsed; // The number of bytes used in the buffer, ie the number of bytes to transfer to the FIFO.
+ byte rxAlign; // Used in BitFramingReg. Defines the bit position for the first bit received.
+ byte txLastBits; // Used in BitFramingReg. The number of valid bits in the last transmitted byte.
+ byte *responseBuffer;
+ byte responseLength;
+
+ // Description of buffer structure:
+ // Byte 0: SEL Indicates the Cascade Level: PICC_CMD_SEL_CL1, PICC_CMD_SEL_CL2 or PICC_CMD_SEL_CL3
+ // Byte 1: NVB Number of Valid Bits (in complete command, not just the UID): High nibble: complete bytes, Low nibble: Extra bits.
+ // Byte 2: UID-data or CT See explanation below. CT means Cascade Tag.
+ // Byte 3: UID-data
+ // Byte 4: UID-data
+ // Byte 5: UID-data
+ // Byte 6: BCC Block Check Character - XOR of bytes 2-5
+ // Byte 7: CRC_A
+ // Byte 8: CRC_A
+ // The BCC and CRC_A is only transmitted if we know all the UID bits of the current Cascade Level.
+ //
+ // Description of bytes 2-5: (Section 6.5.4 of the ISO/IEC 14443-3 draft: UID contents and cascade levels)
+ // UID size Cascade level Byte2 Byte3 Byte4 Byte5
+ // ======== ============= ===== ===== ===== =====
+ // 4 bytes 1 uid0 uid1 uid2 uid3
+ // 7 bytes 1 CT uid0 uid1 uid2
+ // 2 uid3 uid4 uid5 uid6
+ // 10 bytes 1 CT uid0 uid1 uid2
+ // 2 CT uid3 uid4 uid5
+ // 3 uid6 uid7 uid8 uid9
+
+ // Sanity checks
+ if (validBits > 80) {
+ return STATUS_INVALID;
+ }
+
+ // Prepare MFRC522
+ PCD_ClearRegisterBitMask(CollReg, 0x80); // ValuesAfterColl=1 => Bits received after collision are cleared.
+
+ // Repeat Cascade Level loop until we have a complete UID.
+ uidComplete = 0;
+ while ( ! uidComplete) {
+ // Set the Cascade Level in the SEL byte, find out if we need to use the Cascade Tag in byte 2.
+ switch (cascadeLevel) {
+ case 1:
+ buffer[0] = PICC_CMD_SEL_CL1;
+ uidIndex = 0;
+ useCascadeTag = validBits && uid->size > 4; // When we know that the UID has more than 4 bytes
+ break;
+
+ case 2:
+ buffer[0] = PICC_CMD_SEL_CL2;
+ uidIndex = 3;
+ useCascadeTag = validBits && uid->size > 7; // When we know that the UID has more than 7 bytes
+ break;
+
+ case 3:
+ buffer[0] = PICC_CMD_SEL_CL3;
+ uidIndex = 6;
+ useCascadeTag = 0; // Never used in CL3.
+ break;
+
+ default:
+ return STATUS_INTERNAL_ERROR;
+ break;
+ }
+
+ // How many UID bits are known in this Cascade Level?
+ currentLevelKnownBits = validBits - (8 * uidIndex);
+ if (currentLevelKnownBits < 0) {
+ currentLevelKnownBits = 0;
+ }
+ // Copy the known bits from uid->uidByte[] to buffer[]
+ index = 2; // destination index in buffer[]
+ if (useCascadeTag) {
+ buffer[index++] = PICC_CMD_CT;
+ }
+ byte bytesToCopy = currentLevelKnownBits / 8 + (currentLevelKnownBits % 8 ? 1 : 0); // The number of bytes needed to represent the known bits for this level.
+ if (bytesToCopy) {
+ byte maxBytes = useCascadeTag ? 3 : 4; // Max 4 bytes in each Cascade Level. Only 3 left if we use the Cascade Tag
+ if (bytesToCopy > maxBytes) {
+ bytesToCopy = maxBytes;
+ }
+ for (count = 0; count < bytesToCopy; count++) {
+ buffer[index++] = uid->uidByte[uidIndex + count];
+ }
+ }
+ // Now that the data has been copied we need to include the 8 bits in CT in currentLevelKnownBits
+ if (useCascadeTag) {
+ currentLevelKnownBits += 8;
+ }
+
+ // Repeat anti collision loop until we can transmit all UID bits + BCC and receive a SAK - max 32 iterations.
+ selectDone = 0;
+ while ( ! selectDone) {
+ // Find out how many bits and bytes to send and receive.
+ if (currentLevelKnownBits >= 32) { // All UID bits in this Cascade Level are known. This is a SELECT.
+ //Serial.print("SELECT: currentLevelKnownBits="); Serial.println(currentLevelKnownBits, DEC);
+ buffer[1] = 0x70; // NVB - Number of Valid Bits: Seven whole bytes
+ // Calulate BCC - Block Check Character
+ buffer[6] = buffer[2] ^ buffer[3] ^ buffer[4] ^ buffer[5];
+ // Calculate CRC_A
+ result = PCD_CalculateCRC(buffer, 7, &buffer[7]);
+ if (result != STATUS_OK) {
+ return result;
+ }
+ txLastBits = 0; // 0 => All 8 bits are valid.
+ bufferUsed = 9;
+ // Store response in the last 3 bytes of buffer (BCC and CRC_A - not needed after tx)
+ responseBuffer = &buffer[6];
+ responseLength = 3;
+ }
+ else { // This is an ANTICOLLISION.
+ //Serial.print("ANTICOLLISION: currentLevelKnownBits="); Serial.println(currentLevelKnownBits, DEC);
+ txLastBits = currentLevelKnownBits % 8;
+ count = currentLevelKnownBits / 8; // Number of whole bytes in the UID part.
+ index = 2 + count; // Number of whole bytes: SEL + NVB + UIDs
+ buffer[1] = (index << 4) + txLastBits; // NVB - Number of Valid Bits
+ bufferUsed = index + (txLastBits ? 1 : 0);
+ // Store response in the unused part of buffer
+ responseBuffer = &buffer[index];
+ responseLength = sizeof(buffer) - index;
+ }
+
+ // Set bit adjustments
+ rxAlign = txLastBits; // Having a seperate variable is overkill. But it makes the next line easier to read.
+ PCD_WriteRegister(BitFramingReg, (rxAlign << 4) + txLastBits); // RxAlign = BitFramingReg[6..4]. TxLastBits = BitFramingReg[2..0]
+
+ // Transmit the buffer and receive the response.
+ result = PCD_TransceiveData(buffer, bufferUsed, responseBuffer, &responseLength, &txLastBits, rxAlign, 0);
+ if (result == STATUS_COLLISION) { // More than one PICC in the field => collision.
+ result = PCD_ReadRegister(CollReg); // CollReg[7..0] bits are: ValuesAfterColl reserved CollPosNotValid CollPos[4:0]
+ if (result & 0x20) { // CollPosNotValid
+ return STATUS_COLLISION; // Without a valid collision position we cannot continue
+ }
+ byte collisionPos = result & 0x1F; // Values 0-31, 0 means bit 32.
+ if (collisionPos == 0) {
+ collisionPos = 32;
+ }
+ if (collisionPos <= currentLevelKnownBits) { // No progress - should not happen
+ return STATUS_INTERNAL_ERROR;
+ }
+ // Choose the PICC with the bit set.
+ currentLevelKnownBits = collisionPos;
+ count = (currentLevelKnownBits - 1) % 8; // The bit to modify
+ index = 1 + (currentLevelKnownBits / 8) + (count ? 1 : 0); // First byte is index 0.
+ buffer[index] |= (1 << count);
+ }
+ else if (result != STATUS_OK) {
+ return result;
+ }
+ else { // STATUS_OK
+ if (currentLevelKnownBits >= 32) { // This was a SELECT.
+ selectDone = 1; // No more anticollision
+ // We continue below outside the while.
+ }
+ else { // This was an ANTICOLLISION.
+ // We now have all 32 bits of the UID in this Cascade Level
+ currentLevelKnownBits = 32;
+ // Run loop again to do the SELECT.
+ }
+ }
+ } // End of while ( ! selectDone)
+
+ // We do not check the CBB - it was constructed by us above.
+
+ // Copy the found UID bytes from buffer[] to uid->uidByte[]
+ index = (buffer[2] == PICC_CMD_CT) ? 3 : 2; // source index in buffer[]
+ bytesToCopy = (buffer[2] == PICC_CMD_CT) ? 3 : 4;
+ for (count = 0; count < bytesToCopy; count++) {
+ uid->uidByte[uidIndex + count] = buffer[index++];
+ }
+
+ // Check response SAK (Select Acknowledge)
+ if (responseLength != 3 || txLastBits != 0) { // SAK must be exactly 24 bits (1 byte + CRC_A).
+ return STATUS_ERROR;
+ }
+ // Verify CRC_A - do our own calculation and store the control in buffer[2..3] - those bytes are not needed anymore.
+ result = PCD_CalculateCRC(responseBuffer, 1, &buffer[2]);
+ if (result != STATUS_OK) {
+ return result;
+ }
+ if ((buffer[2] != responseBuffer[1]) || (buffer[3] != responseBuffer[2])) {
+ return STATUS_CRC_WRONG;
+ }
+ if (responseBuffer[0] & 0x04) { // Cascade bit set - UID not complete yes
+ cascadeLevel++;
+ }
+ else {
+ uidComplete = 1;
+ uid->sak = responseBuffer[0];
+ }
+ } // End of while ( ! uidComplete)
+
+ // Set correct uid->size
+ uid->size = 3 * cascadeLevel + 1;
+
+ return STATUS_OK;
+}
+
+/**
+ * Instructs a PICC in state ACTIVE(*) to go to state HALT.
+ *
+ * @return STATUS_OK on success, STATUS_??? otherwise.
+ */
+byte PICC_HaltA() {
+ byte result;
+ byte buffer[4];
+
+ // Build command buffer
+ buffer[0] = PICC_CMD_HLTA;
+ buffer[1] = 0;
+ // Calculate CRC_A
+ result = PCD_CalculateCRC(buffer, 2, &buffer[2]);
+ if (result != STATUS_OK) {
+ return result;
+ }
+
+ // Send the command.
+ // The standard says:
+ // If the PICC responds with any modulation during a period of 1 ms after the end of the frame containing the
+ // HLTA command, this response shall be interpreted as 'not acknowledge'.
+ // We interpret that this way: Only STATUS_TIMEOUT is an success.
+ result = PCD_TransceiveData(buffer, sizeof(buffer), NULL, 0, 0, 0, 0);
+ if (result == STATUS_TIMEOUT) {
+ return STATUS_OK;
+ }
+ if (result == STATUS_OK) { // That is ironically NOT ok in this case ;-)
+ return STATUS_ERROR;
+ }
+ return result;
+}
+
+
+//-----------------------------------------------------------------------------------
+// Functions for communicating with MIFARE PICCs
+//-----------------------------------------------------------------------------------
+
+/**
+ * Executes the MFRC522 MFAuthent command.
+ * This command manages MIFARE authentication to enable a secure communication to any MIFARE Mini, MIFARE 1K and MIFARE 4K card.
+ * The authentication is described in the MFRC522 datasheet section 10.3.1.9 and http://www.nxp.com/documents/data_sheet/MF1S503x.pdf section 10.1.
+ * For use with MIFARE Classic PICCs.
+ * The PICC must be selected - ie in state ACTIVE(*) - before calling this function.
+ * Remember to call PCD_StopCrypto1() after communicating with the authenticated PICC - otherwise no new communications can start.
+ *
+ * All keys are set to FFFFFFFFFFFFh at chip delivery.
+ *
+ * @return STATUS_OK on success, STATUS_??? otherwise. Probably STATUS_TIMEOUT if you supply the wrong key.
+ */
+byte PCD_Authenticate( byte command, ///< PICC_CMD_MF_AUTH_KEY_A or PICC_CMD_MF_AUTH_KEY_B
+ byte blockAddr, ///< The block number. See numbering in the comments in the .h file.
+ MIFARE_Key *key, ///< Pointer to the Crypteo1 key to use (6 bytes)
+ Uid *uid ///< Pointer to Uid struct. The first 4 bytes of the UID is used.
+) {
+ byte waitIRq = 0x10; // IdleIRq
+
+ // Build command buffer
+ byte sendData[12];
+ sendData[0] = command;
+ sendData[1] = blockAddr;
+ for (byte i = 0; i < MF_KEY_SIZE; i++) { // 6 key bytes
+ sendData[2+i] = key->keyByte[i];
+ }
+ for (byte i = 0; i < 4; i++) { // The first 4 bytes of the UID
+ sendData[8+i] = uid->uidByte[i];
+ }
+
+ // Start the authentication.
+ return PCD_CommunicateWithPICC(PCD_MFAuthent, waitIRq, &sendData[0], sizeof(sendData), 0, 0, 0, 0, 0);
+}
+
+/**
+ * Used to exit the PCD from its authenticated state.
+ * Remember to call this function after communicating with an authenticated PICC - otherwise no new communications can start.
+ */
+void PCD_StopCrypto1() {
+ // Clear MFCrypto1On bit
+ PCD_ClearRegisterBitMask(Status2Reg, 0x08); // Status2Reg[7..0] bits are: TempSensClear I2CForceHS reserved reserved MFCrypto1On ModemState[2:0]
+}
+
+/**
+ * Reads 16 bytes (+ 2 bytes CRC_A) from the active PICC.
+ *
+ * For MIFARE Classic the sector containing the block must be authenticated before calling this function.
+ *
+ * For MIFARE Ultralight only addresses 00h to 0Fh are decoded.
+ * The MF0ICU1 returns a NAK for higher addresses.
+ * The MF0ICU1 responds to the READ command by sending 16 bytes starting from the page address defined by the command argument.
+ * For example; if blockAddr is 03h then pages 03h, 04h, 05h, 06h are returned.
+ * A roll-back is implemented: If blockAddr is 0Eh, then the contents of pages 0Eh, 0Fh, 00h and 01h are returned.
+ *
+ * The buffer must be at least 18 bytes because a CRC_A is also returned.
+ * Checks the CRC_A before returning STATUS_OK.
+ *
+ * @return STATUS_OK on success, STATUS_??? otherwise.
+ */
+byte MIFARE_Read( byte blockAddr, ///< MIFARE Classic: The block (0-0xff) number. MIFARE Ultralight: The first page to return data from.
+ byte *buffer, ///< The buffer to store the data in
+ byte *bufferSize ///< Buffer size, at least 18 bytes. Also number of bytes returned if STATUS_OK.
+) {
+ byte result;
+
+ // Sanity check
+ if (buffer == NULL || *bufferSize < 18) {
+ return STATUS_NO_ROOM;
+ }
+
+ // Build command buffer
+ buffer[0] = PICC_CMD_MF_READ;
+ buffer[1] = blockAddr;
+ // Calculate CRC_A
+ result = PCD_CalculateCRC(buffer, 2, &buffer[2]);
+ if (result != STATUS_OK) {
+ return result;
+ }
+
+ // Transmit the buffer and receive the response, validate CRC_A.
+ return PCD_TransceiveData(buffer, 4, buffer, bufferSize, NULL, 0, 1);
+}
+
+/**
+ * Writes 16 bytes to the active PICC.
+ *
+ * For MIFARE Classic the sector containing the block must be authenticated before calling this function.
+ *
+ * For MIFARE Ultralight the opretaion is called "COMPATIBILITY WRITE".
+ * Even though 16 bytes are transferred to the Ultralight PICC, only the least significant 4 bytes (bytes 0 to 3)
+ * are written to the specified address. It is recommended to set the remaining bytes 04h to 0Fh to all logic 0.
+ * *
+ * @return STATUS_OK on success, STATUS_??? otherwise.
+ */
+byte MIFARE_Write( byte blockAddr, ///< MIFARE Classic: The block (0-0xff) number. MIFARE Ultralight: The page (2-15) to write to.
+ byte *buffer, ///< The 16 bytes to write to the PICC
+ byte bufferSize ///< Buffer size, must be at least 16 bytes. Exactly 16 bytes are written.
+) {
+ byte result;
+
+ // Sanity check
+ if (buffer == NULL || bufferSize < 16) {
+ return STATUS_INVALID;
+ }
+
+ // Mifare Classic protocol requires two communications to perform a write.
+ // Step 1: Tell the PICC we want to write to block blockAddr.
+ byte cmdBuffer[2];
+ cmdBuffer[0] = PICC_CMD_MF_WRITE;
+ cmdBuffer[1] = blockAddr;
+ result = PCD_MIFARE_Transceive(cmdBuffer, 2, 0); // Adds CRC_A and checks that the response is MF_ACK.
+ if (result != STATUS_OK) {
+ return result;
+ }
+
+ // Step 2: Transfer the data
+ result = PCD_MIFARE_Transceive( buffer, bufferSize, 0); // Adds CRC_A and checks that the response is MF_ACK.
+ if (result != STATUS_OK) {
+ return result;
+ }
+
+ return STATUS_OK;
+}
+
+/**
+ * Writes a 4 byte page to the active MIFARE Ultralight PICC.
+ *
+ * @return STATUS_OK on success, STATUS_??? otherwise.
+ */
+ /*
+byte MIFARE_Ultralight_Write( byte page, ///< The page (2-15) to write to.
+ byte *buffer, ///< The 4 bytes to write to the PICC
+ byte bufferSize ///< Buffer size, must be at least 4 bytes. Exactly 4 bytes are written.
+) {
+ byte result;
+
+ // Sanity check
+ if (buffer == NULL || bufferSize < 4) {
+ return STATUS_INVALID;
+ }
+
+ // Build commmand buffer
+ byte cmdBuffer[6];
+ cmdBuffer[0] = PICC_CMD_UL_WRITE;
+ cmdBuffer[1] = page;
+ memcpy(&cmdBuffer[2], buffer, 4);
+
+ // Perform the write
+ result = PCD_MIFARE_Transceive(cmdBuffer, 6, 0); // Adds CRC_A and checks that the response is MF_ACK.
+ if (result != STATUS_OK) {
+ return result;
+ }
+ return STATUS_OK;
+}
+*/
+// forward declaration
+//byte MIFARE_TwoStepHelper( byte command, byte blockAddr, long data);
+
+/**
+ * MIFARE Decrement subtracts the delta from the value of the addressed block, and stores the result in a volatile memory.
+ * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
+ * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
+ * Use MIFARE_Transfer() to store the result in a block.
+ *
+ * @return STATUS_OK on success, STATUS_??? otherwise.
+ */
+/*
+byte MIFARE_Decrement( byte blockAddr, ///< The block (0-0xff) number.
+ long delta ///< This number is subtracted from the value of block blockAddr.
+) {
+ return MIFARE_TwoStepHelper(PICC_CMD_MF_DECREMENT, blockAddr, delta);
+}
+*/
+/**
+ * MIFARE Increment adds the delta to the value of the addressed block, and stores the result in a volatile memory.
+ * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
+ * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
+ * Use MIFARE_Transfer() to store the result in a block.
+ *
+ * @return STATUS_OK on success, STATUS_??? otherwise.
+ */
+/*
+byte MIFARE_Increment( byte blockAddr, ///< The block (0-0xff) number.
+ long delta ///< This number is added to the value of block blockAddr.
+) {
+ return MIFARE_TwoStepHelper(PICC_CMD_MF_INCREMENT, blockAddr, delta);
+}
+*/
+/**
+ * MIFARE Restore copies the value of the addressed block into a volatile memory.
+ * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
+ * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
+ * Use MIFARE_Transfer() to store the result in a block.
+ *
+ * @return STATUS_OK on success, STATUS_??? otherwise.
+ */
+ /*
+byte MIFARE_Restore(byte blockAddr ///< The block (0-0xff) number.
+) {
+ // The datasheet describes Restore as a two step operation, but does not explain what data to transfer in step 2.
+ // Doing only a single step does not work, so I chose to transfer 0L in step two.
+ return MIFARE_TwoStepHelper(PICC_CMD_MF_RESTORE, blockAddr, 0L);
+}
+*/
+/**
+ * Helper function for the two-step MIFARE Classic protocol operations Decrement, Increment and Restore.
+ *
+ * @return STATUS_OK on success, STATUS_??? otherwise.
+ */
+ /*
+byte MIFARE_TwoStepHelper( byte command, ///< The command to use
+ byte blockAddr, ///< The block (0-0xff) number.
+ long data ///< The data to transfer in step 2
+) {
+ byte result;
+ byte cmdBuffer[2]; // We only need room for 2 bytes.
+
+ // Step 1: Tell the PICC the command and block address
+ cmdBuffer[0] = command;
+ cmdBuffer[1] = blockAddr;
+ result = PCD_MIFARE_Transceive( cmdBuffer, 2, 0); // Adds CRC_A and checks that the response is MF_ACK.
+ if (result != STATUS_OK) {
+ return result;
+ }
+
+ // Step 2: Transfer the data
+ result = PCD_MIFARE_Transceive( (byte *)&data, 4, 1); // Adds CRC_A and accept timeout as success.
+ if (result != STATUS_OK) {
+ return result;
+ }
+
+ return STATUS_OK;
+}
+*/
+/**
+ * MIFARE Transfer writes the value stored in the volatile memory into one MIFARE Classic block.
+ * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
+ * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
+ *
+ * @return STATUS_OK on success, STATUS_??? otherwise.
+ */
+ /*
+byte MIFARE_Transfer( byte blockAddr ///< The block (0-0xff) number.
+) {
+ byte result;
+ byte cmdBuffer[2]; // We only need room for 2 bytes.
+
+ // Tell the PICC we want to transfer the result into block blockAddr.
+ cmdBuffer[0] = PICC_CMD_MF_TRANSFER;
+ cmdBuffer[1] = blockAddr;
+ result = PCD_MIFARE_Transceive( cmdBuffer, 2, 0); // Adds CRC_A and checks that the response is MF_ACK.
+ if (result != STATUS_OK) {
+ return result;
+ }
+ return STATUS_OK;
+}
+*/
+
+//-----------------------------------------------------------------------------------
+// Support functions
+//-----------------------------------------------------------------------------------
+
+/**
+ * Wrapper for MIFARE protocol communication.
+ * Adds CRC_A, executes the Transceive command and checks that the response is MF_ACK or a timeout.
+ *
+ * @return STATUS_OK on success, STATUS_??? otherwise.
+ */
+byte PCD_MIFARE_Transceive( byte *sendData, ///< Pointer to the data to transfer to the FIFO. Do NOT include the CRC_A.
+ byte sendLen, ///< Number of bytes in sendData.
+ bool acceptTimeout ///< True => A timeout is also success
+) {
+ byte result;
+ byte cmdBuffer[18]; // We need room for 16 bytes data and 2 bytes CRC_A.
+
+ // Sanity check
+ if (sendData == NULL || sendLen > 16) {
+ return STATUS_INVALID;
+ }
+
+ // Copy sendData[] to cmdBuffer[] and add CRC_A
+ memcpy(cmdBuffer, sendData, sendLen);
+ result = PCD_CalculateCRC(cmdBuffer, sendLen, &cmdBuffer[sendLen]);
+ if (result != STATUS_OK) {
+ return result;
+ }
+ sendLen += 2;
+
+ // Transceive the data, store the reply in cmdBuffer[]
+ byte waitIRq = 0x30; // RxIRq and IdleIRq
+ byte cmdBufferSize = sizeof(cmdBuffer);
+ byte validBits = 0;
+ result = PCD_CommunicateWithPICC(PCD_Transceive, waitIRq, cmdBuffer, sendLen, cmdBuffer, &cmdBufferSize, &validBits, 0, 0);
+ if (acceptTimeout && result == STATUS_TIMEOUT) {
+ return STATUS_OK;
+ }
+ if (result != STATUS_OK) {
+ return result;
+ }
+ // The PICC must reply with a 4 bit ACK
+ if (cmdBufferSize != 1 || validBits != 4) {
+ return STATUS_ERROR;
+ }
+ if (cmdBuffer[0] != MF_ACK) {
+ return STATUS_MIFARE_NACK;
+ }
+ return STATUS_OK;
+}
+
+/**
+ * Returns a string pointer to a status code name.
+ *
+ */
+/*
+const char *GetStatusCodeName(byte code ///< One of the StatusCode enums.
+) {
+ switch (code) {
+ case STATUS_OK: return "Success."; break;
+ case STATUS_ERROR: return "Error in communication."; break;
+ case STATUS_COLLISION: return "Collission detected."; break;
+ case STATUS_TIMEOUT: return "Timeout in communication."; break;
+ case STATUS_NO_ROOM: return "A buffer is not big enough."; break;
+ case STATUS_INTERNAL_ERROR: return "Internal error in the code. Should not happen."; break;
+ case STATUS_INVALID: return "Invalid argument."; break;
+ case STATUS_CRC_WRONG: return "The CRC_A does not match."; break;
+ case STATUS_MIFARE_NACK: return "A MIFARE PICC responded with NAK."; break;
+ default:
+ return "Unknown error";
+ break;
+ }
+}
+*/
+/**
+ * Translates the SAK (Select Acknowledge) to a PICC type.
+ *
+ * @return PICC_Type
+ */
+ /*
+byte PICC_GetType(byte sak ///< The SAK byte returned from PICC_Select().
+) {
+ if (sak & 0x04) { // UID not complete
+ return PICC_TYPE_NOT_COMPLETE;
+ }
+
+ switch (sak) {
+ case 0x09: return PICC_TYPE_MIFARE_MINI; break;
+ case 0x08: return PICC_TYPE_MIFARE_1K; break;
+ case 0x18: return PICC_TYPE_MIFARE_4K; break;
+ case 0x00: return PICC_TYPE_MIFARE_UL; break;
+ case 0x10:
+ case 0x11: return PICC_TYPE_MIFARE_PLUS; break;
+ case 0x01: return PICC_TYPE_TNP3XXX; break;
+ default: break;
+ }
+
+ if (sak & 0x20) {
+ return PICC_TYPE_ISO_14443_4;
+ }
+
+ if (sak & 0x40) {
+ return PICC_TYPE_ISO_18092;
+ }
+
+ return PICC_TYPE_UNKNOWN;
+}
+*/
+/**
+ * Returns a string pointer to the PICC type name.
+ *
+ */
+ /*
+const char *PICC_GetTypeName(byte piccType ///< One of the PICC_Type enums.
+) {
+ switch (piccType) {
+ case PICC_TYPE_ISO_14443_4: return "PICC compliant with ISO/IEC 14443-4"; break;
+ case PICC_TYPE_ISO_18092: return "PICC compliant with ISO/IEC 18092 (NFC)"; break;
+ case PICC_TYPE_MIFARE_MINI: return "MIFARE Mini, 320 bytes"; break;
+ case PICC_TYPE_MIFARE_1K: return "MIFARE 1KB"; break;
+ case PICC_TYPE_MIFARE_4K: return "MIFARE 4KB"; break;
+ case PICC_TYPE_MIFARE_UL: return "MIFARE Ultralight or Ultralight C"; break;
+ case PICC_TYPE_MIFARE_PLUS: return "MIFARE Plus"; break;
+ case PICC_TYPE_TNP3XXX: return "MIFARE TNP3XXX"; break;
+ case PICC_TYPE_NOT_COMPLETE: return "SAK indicates UID is not complete."; break;
+ case PICC_TYPE_UNKNOWN:
+ default: return "Unknown type"; break;
+ }
+}
+*/
+/**
+ * Dumps debug info about the selected PICC to Serial.
+ * On success the PICC is halted after dumping the data.
+ * For MIFARE Classic the factory default key of 0xFFFFFFFFFFFF is tried.
+ */
+ /*
+void PICC_DumpToSerial(Uid *uid ///< Pointer to Uid struct returned from a successful PICC_Select().
+ ) {
+ MIFARE_Key key;
+
+ // UID
+ Serial.print("Card UID:");
+ for (byte i = 0; i < uid->size; i++) {
+ Serial.print(uid->uidByte[i] < 0x10 ? " 0" : " ");
+ Serial.print(uid->uidByte[i], HEX);
+ }
+ Serial.println();
+
+ // PICC type
+ byte piccType = PICC_GetType(uid->sak);
+ Serial.print("PICC type: ");
+ Serial.println(PICC_GetTypeName(piccType));
+
+ // Dump contents
+ switch (piccType) {
+ case PICC_TYPE_MIFARE_MINI:
+ case PICC_TYPE_MIFARE_1K:
+ case PICC_TYPE_MIFARE_4K:
+ // All keys are set to FFFFFFFFFFFFh at chip delivery from the factory.
+ for (byte i = 0; i < 6; i++) {
+ key.keyByte[i] = 0xFF;
+ }
+ PICC_DumpMifareClassicToSerial(uid, piccType, &key);
+ break;
+
+ case PICC_TYPE_MIFARE_UL:
+ PICC_DumpMifareUltralightToSerial();
+ break;
+
+ case PICC_TYPE_ISO_14443_4:
+ case PICC_TYPE_ISO_18092:
+ case PICC_TYPE_MIFARE_PLUS:
+ case PICC_TYPE_TNP3XXX:
+ Serial.println("Dumping memory contents not implemented for that PICC type.");
+ break;
+
+ case PICC_TYPE_UNKNOWN:
+ case PICC_TYPE_NOT_COMPLETE:
+ default:
+ break; // No memory dump here
+ }
+
+ Serial.println();
+ PICC_HaltA(); // Already done if it was a MIFARE Classic PICC.
+} // End PICC_DumpToSerial()
+*/
+/**
+ * Dumps memory contents of a MIFARE Classic PICC.
+ * On success the PICC is halted after dumping the data.
+ */
+ /*
+void PICC_DumpMifareClassicToSerial( Uid *uid, ///< Pointer to Uid struct returned from a successful PICC_Select().
+ byte piccType, ///< One of the PICC_Type enums.
+ MIFARE_Key *key ///< Key A used for all sectors.
+ ) {
+ byte no_of_sectors = 0;
+ switch (piccType) {
+ case PICC_TYPE_MIFARE_MINI:
+ // Has 5 sectors * 4 blocks/sector * 16 bytes/block = 320 bytes.
+ no_of_sectors = 5;
+ break;
+
+ case PICC_TYPE_MIFARE_1K:
+ // Has 16 sectors * 4 blocks/sector * 16 bytes/block = 1024 bytes.
+ no_of_sectors = 16;
+ break;
+
+ case PICC_TYPE_MIFARE_4K:
+ // Has (32 sectors * 4 blocks/sector + 8 sectors * 16 blocks/sector) * 16 bytes/block = 4096 bytes.
+ no_of_sectors = 40;
+ break;
+
+ default: // Should not happen. Ignore.
+ break;
+ }
+
+ // Dump sectors, highest address first.
+ if (no_of_sectors) {
+ Serial.println("Sector Block 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 AccessBits");
+ for (char i = no_of_sectors - 1; i >= 0; i--) {
+ PICC_DumpMifareClassicSectorToSerial(uid, key, i);
+ }
+ }
+ PICC_HaltA(); // Halt the PICC before stopping the encrypted session.
+ PCD_StopCrypto1();
+} // End PICC_DumpMifareClassicToSerial()
+*/
+/**
+ * Dumps memory contents of a sector of a MIFARE Classic PICC.
+ * Uses PCD_Authenticate(), MIFARE_Read() and PCD_StopCrypto1.
+ * Always uses PICC_CMD_MF_AUTH_KEY_A because only Key A can always read the sector trailer access bits.
+ */
+ /*
+void PICC_DumpMifareClassicSectorToSerial(Uid *uid, ///< Pointer to Uid struct returned from a successful PICC_Select().
+ MIFARE_Key *key, ///< Key A for the sector.
+ byte sector ///< The sector to dump, 0..39.
+ ) {
+ byte status;
+ byte firstBlock; // Address of lowest address to dump actually last block dumped)
+ byte no_of_blocks; // Number of blocks in sector
+ bool isSectorTrailer; // Set to true while handling the "last" (ie highest address) in the sector.
+
+ // The access bits are stored in a peculiar fashion.
+ // There are four groups:
+ // g[3] Access bits for the sector trailer, block 3 (for sectors 0-31) or block 15 (for sectors 32-39)
+ // g[2] Access bits for block 2 (for sectors 0-31) or blocks 10-14 (for sectors 32-39)
+ // g[1] Access bits for block 1 (for sectors 0-31) or blocks 5-9 (for sectors 32-39)
+ // g[0] Access bits for block 0 (for sectors 0-31) or blocks 0-4 (for sectors 32-39)
+ // Each group has access bits [C1 C2 C3]. In this code C1 is MSB and C3 is LSB.
+ // The four CX bits are stored together in a nible cx and an inverted nible cx_.
+ byte c1, c2, c3; // Nibbles
+ byte c1_, c2_, c3_; // Inverted nibbles
+ bool invertedError; // True if one of the inverted nibbles did not match
+ byte g[4]; // Access bits for each of the four groups.
+ byte group; // 0-3 - active group for access bits
+ bool firstInGroup; // True for the first block dumped in the group
+
+ // Determine position and size of sector.
+ if (sector < 32) { // Sectors 0..31 has 4 blocks each
+ no_of_blocks = 4;
+ firstBlock = sector * no_of_blocks;
+ }
+ else if (sector < 40) { // Sectors 32-39 has 16 blocks each
+ no_of_blocks = 16;
+ firstBlock = 128 + (sector - 32) * no_of_blocks;
+ }
+ else { // Illegal input, no MIFARE Classic PICC has more than 40 sectors.
+ return;
+ }
+
+ // Dump blocks, highest address first.
+ byte byteCount;
+ byte buffer[18];
+ byte blockAddr;
+ isSectorTrailer = true;
+ for (char blockOffset = no_of_blocks - 1; blockOffset >= 0; blockOffset--) {
+ blockAddr = firstBlock + blockOffset;
+ // Sector number - only on first line
+ if (isSectorTrailer) {
+ Serial.print(sector < 10 ? " " : " "); // Pad with spaces
+ Serial.print(sector);
+ Serial.print(" ");
+ }
+ else {
+ Serial.print(" ");
+ }
+ // Block number
+ Serial.print(blockAddr < 10 ? " " : (blockAddr < 100 ? " " : " ")); // Pad with spaces
+ Serial.print(blockAddr);
+ Serial.print(" ");
+ // Establish encrypted communications before reading the first block
+ if (isSectorTrailer) {
+ status = PCD_Authenticate(PICC_CMD_MF_AUTH_KEY_A, firstBlock, key, uid);
+ if (status != STATUS_OK) {
+ Serial.print("PCD_Authenticate() failed: ");
+ Serial.println(GetStatusCodeName(status));
+ return;
+ }
+ }
+ // Read block
+ byteCount = sizeof(buffer);
+ status = MIFARE_Read(blockAddr, buffer, &byteCount);
+ if (status != STATUS_OK) {
+ Serial.print("MIFARE_Read() failed: ");
+ Serial.println(GetStatusCodeName(status));
+ continue;
+ }
+ // Dump data
+ for (byte index = 0; index < 16; index++) {
+ Serial.print(buffer[index] < 0x10 ? " 0" : " ");
+ Serial.print(buffer[index], HEX);
+ if ((index % 4) == 3) {
+ Serial.print(" ");
+ }
+ }
+ // Parse sector trailer data
+ if (isSectorTrailer) {
+ c1 = buffer[7] >> 4;
+ c2 = buffer[8] & 0xF;
+ c3 = buffer[8] >> 4;
+ c1_ = buffer[6] & 0xF;
+ c2_ = buffer[6] >> 4;
+ c3_ = buffer[7] & 0xF;
+ invertedError = (c1 != (~c1_ & 0xF)) || (c2 != (~c2_ & 0xF)) || (c3 != (~c3_ & 0xF));
+ g[0] = ((c1 & 1) << 2) | ((c2 & 1) << 1) | ((c3 & 1) << 0);
+ g[1] = ((c1 & 2) << 1) | ((c2 & 2) << 0) | ((c3 & 2) >> 1);
+ g[2] = ((c1 & 4) << 0) | ((c2 & 4) >> 1) | ((c3 & 4) >> 2);
+ g[3] = ((c1 & 8) >> 1) | ((c2 & 8) >> 2) | ((c3 & 8) >> 3);
+ isSectorTrailer = false;
+ }
+
+ // Which access group is this block in?
+ if (no_of_blocks == 4) {
+ group = blockOffset;
+ firstInGroup = true;
+ }
+ else {
+ group = blockOffset / 5;
+ firstInGroup = (group == 3) || (group != (blockOffset + 1) / 5);
+ }
+
+ if (firstInGroup) {
+ // Print access bits
+ Serial.print(" [ ");
+ Serial.print((g[group] >> 2) & 1, DEC); Serial.print(" ");
+ Serial.print((g[group] >> 1) & 1, DEC); Serial.print(" ");
+ Serial.print((g[group] >> 0) & 1, DEC);
+ Serial.print(" ] ");
+ if (invertedError) {
+ Serial.print(" Inverted access bits did not match! ");
+ }
+ }
+
+ if (group != 3 && (g[group] == 1 || g[group] == 6)) { // Not a sector trailer, a value block
+ long value = (long(buffer[3])<<24) | (long(buffer[2])<<16) | (long(buffer[1])<<8) | long(buffer[0]);
+ Serial.print(" Value=0x"); Serial.print(value, HEX);
+ Serial.print(" Adr=0x"); Serial.print(buffer[12], HEX);
+ }
+ Serial.println();
+ }
+
+ return;
+} // End PICC_DumpMifareClassicSectorToSerial()
+*/
+/**
+ * Dumps memory contents of a MIFARE Ultralight PICC.
+ */
+ /*
+void PICC_DumpMifareUltralightToSerial() {
+ byte status;
+ byte byteCount;
+ byte buffer[18];
+ byte i;
+
+ Serial.println("Page 0 1 2 3");
+ // Try the mpages of the original Ultralight. Ultralight C has more pages.
+ for (byte page = 0; page < 16; page +=4) { // Read returns data for 4 pages at a time.
+ // Read pages
+ byteCount = sizeof(buffer);
+ status = MIFARE_Read(page, buffer, &byteCount);
+ if (status != STATUS_OK) {
+ Serial.print("MIFARE_Read() failed: ");
+ Serial.println(GetStatusCodeName(status));
+ break;
+ }
+ // Dump data
+ for (byte offset = 0; offset < 4; offset++) {
+ i = page + offset;
+ Serial.print(i < 10 ? " " : " "); // Pad with spaces
+ Serial.print(i);
+ Serial.print(" ");
+ for (byte index = 0; index < 4; index++) {
+ i = 4 * offset + index;
+ Serial.print(buffer[i] < 0x10 ? " 0" : " ");
+ Serial.print(buffer[i], HEX);
+ }
+ Serial.println();
+ }
+ }
+} // End PICC_DumpMifareUltralightToSerial()
+*/
+/**
+ * Calculates the bit pattern needed for the specified access bits. In the [C1 C2 C3] tupples C1 is MSB (=4) and C3 is LSB (=1).
+ */
+ /*
+void MIFARE_SetAccessBits( byte *accessBitBuffer, ///< Pointer to byte 6, 7 and 8 in the sector trailer. Bytes [0..2] will be set.
+ byte g0, ///< Access bits [C1 C2 C3] for block 0 (for sectors 0-31) or blocks 0-4 (for sectors 32-39)
+ byte g1, ///< Access bits C1 C2 C3] for block 1 (for sectors 0-31) or blocks 5-9 (for sectors 32-39)
+ byte g2, ///< Access bits C1 C2 C3] for block 2 (for sectors 0-31) or blocks 10-14 (for sectors 32-39)
+ byte g3 ///< Access bits C1 C2 C3] for the sector trailer, block 3 (for sectors 0-31) or block 15 (for sectors 32-39)
+) {
+ byte c1 = ((g3 & 4) << 1) | ((g2 & 4) << 0) | ((g1 & 4) >> 1) | ((g0 & 4) >> 2);
+ byte c2 = ((g3 & 2) << 2) | ((g2 & 2) << 1) | ((g1 & 2) << 0) | ((g0 & 2) >> 1);
+ byte c3 = ((g3 & 1) << 3) | ((g2 & 1) << 2) | ((g1 & 1) << 1) | ((g0 & 1) << 0);
+
+ accessBitBuffer[0] = (~c2 & 0xF) << 4 | (~c1 & 0xF);
+ accessBitBuffer[1] = c1 << 4 | (~c3 & 0xF);
+ accessBitBuffer[2] = c3 << 4 | c2;
+}
+*/
+
+//-----------------------------------------------------------------------------------
+// Convenience functions - does not add extra functionality
+//-----------------------------------------------------------------------------------
+
+/**
+ * Returns true if a PICC responds to PICC_CMD_REQA.
+ * Only "new" cards in state IDLE are invited. Sleeping cards in state HALT are ignored.
+ *
+ * @return bool
+ */
+bool PICC_IsNewCardPresent() {
+ byte bufferATQA[2];
+ byte bufferSize = sizeof(bufferATQA);
+ byte result = PICC_RequestA(bufferATQA, &bufferSize);
+ return (result == STATUS_OK || result == STATUS_COLLISION);
+}
+
+/**
+ * Simple wrapper around PICC_Select.
+ * Returns true if a UID could be read.
+ * Remember to call PICC_IsNewCardPresent(), PICC_RequestA() or PICC_WakeupA() first.
+ * The read UID is available in the class variable uid.
+ *
+ * @return bool
+ */
+bool PICC_ReadCardSerial(Uid* uid) {
+ byte result = PICC_Select(uid, 0);
+ return (result == STATUS_OK);
+}
diff --git a/lib/matejx_avr_lib/mfrc522.h b/lib/matejx_avr_lib/mfrc522.h
new file mode 100755
index 0000000..28fb5eb
--- /dev/null
+++ b/lib/matejx_avr_lib/mfrc522.h
@@ -0,0 +1,253 @@
+#ifndef MFRC522_h
+#define MFRC522_h
+
+ #include
+
+ typedef uint8_t bool;
+ typedef uint8_t byte;
+ typedef uint16_t word;
+
+ // MFRC522 registers. Described in chapter 9 of the datasheet.
+ // When using SPI all addresses are shifted one bit left in the "SPI address byte" (section 8.1.2.3)
+ enum PCD_Register {
+ // Page 0: Command and status
+ // 0x00 // reserved for future use
+ CommandReg = 0x01 << 1, // starts and stops command execution
+ ComIEnReg = 0x02 << 1, // enable and disable interrupt request control bits
+ DivIEnReg = 0x03 << 1, // enable and disable interrupt request control bits
+ ComIrqReg = 0x04 << 1, // interrupt request bits
+ DivIrqReg = 0x05 << 1, // interrupt request bits
+ ErrorReg = 0x06 << 1, // error bits showing the error status of the last command executed
+ Status1Reg = 0x07 << 1, // communication status bits
+ Status2Reg = 0x08 << 1, // receiver and transmitter status bits
+ FIFODataReg = 0x09 << 1, // input and output of 64 byte FIFO buffer
+ FIFOLevelReg = 0x0A << 1, // number of bytes stored in the FIFO buffer
+ WaterLevelReg = 0x0B << 1, // level for FIFO underflow and overflow warning
+ ControlReg = 0x0C << 1, // miscellaneous control registers
+ BitFramingReg = 0x0D << 1, // adjustments for bit-oriented frames
+ CollReg = 0x0E << 1, // bit position of the first bit-collision detected on the RF interface
+ // 0x0F // reserved for future use
+
+ // Page 1:Command
+ // 0x10 // reserved for future use
+ ModeReg = 0x11 << 1, // defines general modes for transmitting and receiving
+ TxModeReg = 0x12 << 1, // defines transmission data rate and framing
+ RxModeReg = 0x13 << 1, // defines reception data rate and framing
+ TxControlReg = 0x14 << 1, // controls the logical behavior of the antenna driver pins TX1 and TX2
+ TxASKReg = 0x15 << 1, // controls the setting of the transmission modulation
+ TxSelReg = 0x16 << 1, // selects the internal sources for the antenna driver
+ RxSelReg = 0x17 << 1, // selects internal receiver settings
+ RxThresholdReg = 0x18 << 1, // selects thresholds for the bit decoder
+ DemodReg = 0x19 << 1, // defines demodulator settings
+ // 0x1A // reserved for future use
+ // 0x1B // reserved for future use
+ MfTxReg = 0x1C << 1, // controls some MIFARE communication transmit parameters
+ MfRxReg = 0x1D << 1, // controls some MIFARE communication receive parameters
+ // 0x1E // reserved for future use
+ SerialSpeedReg = 0x1F << 1, // selects the speed of the serial UART interface
+
+ // Page 2: Configuration
+ // 0x20 // reserved for future use
+ CRCResultRegH = 0x21 << 1, // shows the MSB and LSB values of the CRC calculation
+ CRCResultRegL = 0x22 << 1,
+ // 0x23 // reserved for future use
+ ModWidthReg = 0x24 << 1, // controls the ModWidth setting?
+ // 0x25 // reserved for future use
+ RFCfgReg = 0x26 << 1, // configures the receiver gain
+ GsNReg = 0x27 << 1, // selects the conductance of the antenna driver pins TX1 and TX2 for modulation
+ CWGsPReg = 0x28 << 1, // defines the conductance of the p-driver output during periods of no modulation
+ ModGsPReg = 0x29 << 1, // defines the conductance of the p-driver output during periods of modulation
+ TModeReg = 0x2A << 1, // defines settings for the internal timer
+ TPrescalerReg = 0x2B << 1, // the lower 8 bits of the TPrescaler value. The 4 high bits are in TModeReg.
+ TReloadRegH = 0x2C << 1, // defines the 16-bit timer reload value
+ TReloadRegL = 0x2D << 1,
+ TCounterValueRegH = 0x2E << 1, // shows the 16-bit timer value
+ TCounterValueRegL = 0x2F << 1,
+
+ // Page 3:Test Registers
+ // 0x30 // reserved for future use
+ TestSel1Reg = 0x31 << 1, // general test signal configuration
+ TestSel2Reg = 0x32 << 1, // general test signal configuration
+ TestPinEnReg = 0x33 << 1, // enables pin output driver on pins D1 to D7
+ TestPinValueReg = 0x34 << 1, // defines the values for D1 to D7 when it is used as an I/O bus
+ TestBusReg = 0x35 << 1, // shows the status of the internal test bus
+ AutoTestReg = 0x36 << 1, // controls the digital self test
+ VersionReg = 0x37 << 1, // shows the software version
+ AnalogTestReg = 0x38 << 1, // controls the pins AUX1 and AUX2
+ TestDAC1Reg = 0x39 << 1, // defines the test value for TestDAC1
+ TestDAC2Reg = 0x3A << 1, // defines the test value for TestDAC2
+ TestADCReg = 0x3B << 1 // shows the value of ADC I and Q channels
+ // 0x3C // reserved for production tests
+ // 0x3D // reserved for production tests
+ // 0x3E // reserved for production tests
+ // 0x3F // reserved for production tests
+ };
+
+ // MFRC522 comands. Described in chapter 10 of the datasheet.
+ enum PCD_Command {
+ PCD_Idle = 0x00, // no action, cancels current command execution
+ PCD_Mem = 0x01, // stores 25 bytes into the internal buffer
+ PCD_GenerateRandomID = 0x02, // generates a 10-byte random ID number
+ PCD_CalcCRC = 0x03, // activates the CRC coprocessor or performs a self test
+ PCD_Transmit = 0x04, // transmits data from the FIFO buffer
+ PCD_NoCmdChange = 0x07, // no command change, can be used to modify the CommandReg register bits without affecting the command, for example, the PowerDown bit
+ PCD_Receive = 0x08, // activates the receiver circuits
+ PCD_Transceive = 0x0C, // transmits data from FIFO buffer to antenna and automatically activates the receiver after transmission
+ PCD_MFAuthent = 0x0E, // performs the MIFARE standard authentication as a reader
+ PCD_SoftReset = 0x0F // resets the MFRC522
+ };
+
+ // Commands sent to the PICC.
+ enum PICC_Command {
+ // The commands used by the PCD to manage communication with several PICCs (ISO 14443-3, Type A, section 6.4)
+ PICC_CMD_REQA = 0x26, // REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
+ PICC_CMD_WUPA = 0x52, // Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
+ PICC_CMD_CT = 0x88, // Cascade Tag. Not really a command, but used during anti collision.
+ PICC_CMD_SEL_CL1 = 0x93, // Anti collision/Select, Cascade Level 1
+ PICC_CMD_SEL_CL2 = 0x95, // Anti collision/Select, Cascade Level 1
+ PICC_CMD_SEL_CL3 = 0x97, // Anti collision/Select, Cascade Level 1
+ PICC_CMD_HLTA = 0x50, // HaLT command, Type A. Instructs an ACTIVE PICC to go to state HALT.
+ // The commands used for MIFARE Classic (from http://www.nxp.com/documents/data_sheet/MF1S503x.pdf, Section 9)
+ // Use PCD_MFAuthent to authenticate access to a sector, then use these commands to read/write/modify the blocks on the sector.
+ // The read/write commands can also be used for MIFARE Ultralight.
+ PICC_CMD_MF_AUTH_KEY_A = 0x60, // Perform authentication with Key A
+ PICC_CMD_MF_AUTH_KEY_B = 0x61, // Perform authentication with Key B
+ PICC_CMD_MF_READ = 0x30, // Reads one 16 byte block from the authenticated sector of the PICC. Also used for MIFARE Ultralight.
+ PICC_CMD_MF_WRITE = 0xA0, // Writes one 16 byte block to the authenticated sector of the PICC. Called "COMPATIBILITY WRITE" for MIFARE Ultralight.
+ PICC_CMD_MF_DECREMENT = 0xC0, // Decrements the contents of a block and stores the result in the internal data register.
+ PICC_CMD_MF_INCREMENT = 0xC1, // Increments the contents of a block and stores the result in the internal data register.
+ PICC_CMD_MF_RESTORE = 0xC2, // Reads the contents of a block into the internal data register.
+ PICC_CMD_MF_TRANSFER = 0xB0, // Writes the contents of the internal data register to a block.
+ // The commands used for MIFARE Ultralight (from http://www.nxp.com/documents/data_sheet/MF0ICU1.pdf, Section 8.6)
+ // The PICC_CMD_MF_READ and PICC_CMD_MF_WRITE can also be used for MIFARE Ultralight.
+ PICC_CMD_UL_WRITE = 0xA2 // Writes one 4 byte page to the PICC.
+ };
+
+ // MIFARE constants that does not fit anywhere else
+ enum MIFARE_Misc {
+ MF_ACK = 0xA, // The MIFARE Classic uses a 4 bit ACK/NAK. Any other value than 0xA is NAK.
+ MF_KEY_SIZE = 6 // A Mifare Crypto1 key is 6 bytes.
+ };
+
+ // PICC types we can detect. Remember to update PICC_GetTypeName() if you add more.
+ enum PICC_Type {
+ PICC_TYPE_UNKNOWN = 0,
+ PICC_TYPE_ISO_14443_4 = 1, // PICC compliant with ISO/IEC 14443-4
+ PICC_TYPE_ISO_18092 = 2, // PICC compliant with ISO/IEC 18092 (NFC)
+ PICC_TYPE_MIFARE_MINI = 3, // MIFARE Classic protocol, 320 bytes
+ PICC_TYPE_MIFARE_1K = 4, // MIFARE Classic protocol, 1KB
+ PICC_TYPE_MIFARE_4K = 5, // MIFARE Classic protocol, 4KB
+ PICC_TYPE_MIFARE_UL = 6, // MIFARE Ultralight or Ultralight C
+ PICC_TYPE_MIFARE_PLUS = 7, // MIFARE Plus
+ PICC_TYPE_TNP3XXX = 8, // Only mentioned in NXP AN 10833 MIFARE Type Identification Procedure
+ PICC_TYPE_NOT_COMPLETE = 255 // SAK indicates UID is not complete.
+ };
+
+ // Return codes from the functions in this class. Remember to update GetStatusCodeName() if you add more.
+ enum StatusCode {
+ STATUS_OK = 1, // Success
+ STATUS_ERROR = 2, // Error in communication
+ STATUS_COLLISION = 3, // Collission detected
+ STATUS_TIMEOUT = 4, // Timeout in communication.
+ STATUS_NO_ROOM = 5, // A buffer is not big enough.
+ STATUS_INTERNAL_ERROR = 6, // Internal error in the code. Should not happen ;-)
+ STATUS_INVALID = 7, // Invalid argument.
+ STATUS_CRC_WRONG = 8, // The CRC_A does not match
+ STATUS_MIFARE_NACK = 9 // A MIFARE PICC responded with NAK.
+ };
+
+ // A struct used for passing the UID of a PICC.
+ typedef struct {
+ byte size; // Number of bytes in the UID. 4, 7 or 10.
+ byte uidByte[10];
+ byte sak; // The SAK (Select acknowledge) byte returned from the PICC after successful selection.
+ } Uid;
+
+ // A struct used for passing a MIFARE Crypto1 key
+ typedef struct {
+ byte keyByte[MF_KEY_SIZE];
+ } MIFARE_Key;
+
+ // Member variables
+ //Uid uid; // Used by PICC_ReadCardSerial().
+
+ // Size of the MFRC522 FIFO
+ //static const byte FIFO_SIZE = 64; // The FIFO is 64 bytes.
+
+ //-----------------------------------------------------------------------------------
+ // Functions for setting up the Arduino
+ //-----------------------------------------------------------------------------------
+ void MFRC522_init(void);
+ void setSPIConfig(void);
+
+ //-----------------------------------------------------------------------------------
+ // Basic interface functions for communicating with the MFRC522
+ //-----------------------------------------------------------------------------------
+ void PCD_WriteRegister(byte reg, byte value);
+ void PCD_WriteRegister2(byte reg, byte count, byte *values);
+ byte PCD_ReadRegister(byte reg);
+ void PCD_ReadRegister2(byte reg, byte count, byte *values, byte rxAlign);
+ void setBitMask(unsigned char reg, unsigned char mask);
+ void PCD_SetRegisterBitMask(byte reg, byte mask);
+ void PCD_ClearRegisterBitMask(byte reg, byte mask);
+ byte PCD_CalculateCRC(byte *data, byte length, byte *result);
+
+ //-----------------------------------------------------------------------------------
+ // Functions for manipulating the MFRC522
+ //-----------------------------------------------------------------------------------
+ byte PCD_Init(void);
+ byte PCD_Reset(void);
+ void PCD_AntennaOn(void);
+
+ //-----------------------------------------------------------------------------------
+ // Functions for communicating with PICCs
+ //-----------------------------------------------------------------------------------
+ byte PCD_TransceiveData(byte *sendData, byte sendLen, byte *backData, byte *backLen, byte *validBits, byte rxAlign, bool checkCRC);
+ byte PCD_CommunicateWithPICC(byte command, byte waitIRq, byte *sendData, byte sendLen, byte *backData, byte *backLen, byte *validBits, byte rxAlign, bool checkCRC);
+
+ byte PICC_RequestA(byte *bufferATQA, byte *bufferSize);
+ byte PICC_WakeupA(byte *bufferATQA, byte *bufferSize);
+ byte PICC_REQA_or_WUPA( byte command, byte *bufferATQA, byte *bufferSize);
+ byte PICC_Select(Uid *uid, byte validBits);
+ byte PICC_HaltA(void);
+
+ //-----------------------------------------------------------------------------------
+ // Functions for communicating with MIFARE PICCs
+ //-----------------------------------------------------------------------------------
+ byte PCD_Authenticate(byte command, byte blockAddr, MIFARE_Key *key, Uid *uid);
+ void PCD_StopCrypto1(void);
+ byte MIFARE_Read(byte blockAddr, byte *buffer, byte *bufferSize);
+ byte MIFARE_Write(byte blockAddr, byte *buffer, byte bufferSize);
+ byte MIFARE_Decrement(byte blockAddr, long delta);
+ byte MIFARE_Increment(byte blockAddr, long delta);
+ byte MIFARE_Restore(byte blockAddr);
+ byte MIFARE_Transfer(byte blockAddr);
+ byte MIFARE_Ultralight_Write(byte page, byte *buffer, byte bufferSize);
+
+ //-----------------------------------------------------------------------------------
+ // Support functions
+ //-----------------------------------------------------------------------------------
+ byte PCD_MIFARE_Transceive( byte *sendData, byte sendLen, bool acceptTimeout);
+ const char *GetStatusCodeName(byte code);
+ byte PICC_GetType(byte sak);
+ const char *PICC_GetTypeName(byte type);
+ void PICC_DumpToSerial(Uid *uid);
+ void PICC_DumpMifareClassicToSerial(Uid *uid, byte piccType, MIFARE_Key *key);
+ void PICC_DumpMifareClassicSectorToSerial(Uid *uid, MIFARE_Key *key, byte sector);
+ void PICC_DumpMifareUltralightToSerial(void);
+ void MIFARE_SetAccessBits(byte *accessBitBuffer, byte g0, byte g1, byte g2, byte g3);
+
+ //-----------------------------------------------------------------------------------
+ // Convenience functions - does not add extra functionality
+ //-----------------------------------------------------------------------------------
+ bool PICC_IsNewCardPresent(void);
+ bool PICC_ReadCardSerial(Uid* uid);
+
+/*
+private:
+ byte _chipSelectPin; // Arduino pin connected to MFRC522's SPI slave select input (Pin 24, NSS, active low)
+ byte _resetPowerDownPin; // Arduino pin connected to MFRC522's reset and power down input (Pin 6, NRSTPD, active low)
+ byte MIFARE_TwoStepHelper(byte command, byte blockAddr, long data);
+*/
+
+#endif
diff --git a/lib/matejx_avr_lib/spi.c b/lib/matejx_avr_lib/spi.c
new file mode 100755
index 0000000..c8dc998
--- /dev/null
+++ b/lib/matejx_avr_lib/spi.c
@@ -0,0 +1,98 @@
+/**
+
+SPI methods are not interrupt driven - they wait until SPI operation completes.
+If you're using CMT and would prefer switching to another task while SPI operation
+is in progress, you can define SPI_USE_CMT in swdefs.h. This requires CMT_MUTEX_FUNC.
+
+Also, SS (CS) is not controlled by these methods. It's the responsibility of the user.
+
+@file spi.c
+@brief SPI routines
+@author Matej Kogovsek (matej@hamradio.si)
+@copyright LGPL 2.1
+@note This file is part of mat-stm32f1-lib
+*/
+
+#include
+#include
+#include
+
+#include "spi.h"
+#include "hwdefs.h"
+
+#ifdef SPI_USE_CMT
+ #warning SPI using cmt
+ #include "cmt.h"
+ struct cmt_mutex spi_mutex;
+#endif
+
+#ifndef SPCR0
+ #define SPCR0 SPCR
+ #define SPE0 SPE
+ #define MSTR0 MSTR
+ #define SPSR0 SPSR
+ #define SPDR0 SPDR
+ #define SPIF0 SPIF
+#endif
+
+/**
+@brief Initialize SPI interface.
+
+Although SPI can have different clock phase and polarity, I have never ran across anything that uses other
+than low polarity and 1st edge phase. Therefore these parameters are implied and not variable. As are 8 bit
+words and MSB first.
+@param[in] fdiv Baudrate prescaler, F_CPU dependent
+*/
+void spi_init(uint8_t fdiv)
+{
+ if( SPCR0 & _BV(SPE0) ) return;
+
+ #ifdef SPI_USE_CMT
+ spi_mutex.ac = 0;
+ #endif
+
+ // make SCK, MOSI pins outputs and MISO an input
+ SCK_DDR |= _BV(SCK_BIT);
+ MOSI_DDR |= _BV(MOSI_BIT);
+ MISO_DDR &= ~_BV(MISO_BIT);
+
+ // init SPI, MSB first, SCK low when idle
+ SPCR0 = _BV(SPE0) | _BV(MSTR0) | (fdiv & 3);
+ SPSR0 = (fdiv >> 2) & 1;
+}
+
+/**
+@brief Send and receive byte (NSS not controlled)
+@param[in] d Byte to send
+@return byte received
+*/
+uint8_t spi_rw(uint8_t d)
+{
+ #ifdef SPI_USE_CMT
+ cmt_acquire(&spi_mutex);
+ #endif
+
+ SPCR0 |= _BV(MSTR0);
+ SPDR0 = d;
+ while( !(SPSR0 & _BV(SPIF0)) ) {
+ #ifdef SPI_USE_CMT
+ cmt_delay_ticks(0);
+ #endif
+ }
+ d = SPDR0;
+
+ #ifdef SPI_USE_CMT
+ cmt_release(&spi_mutex);
+ #endif
+
+ return d;
+}
+
+// ------------------------------------------------------------------
+// INTERRUPTS
+// ------------------------------------------------------------------
+
+ISR(SPI_STC_vect)
+{
+//
+}
diff --git a/lib/matejx_avr_lib/spi.h b/lib/matejx_avr_lib/spi.h
new file mode 100755
index 0000000..da95980
--- /dev/null
+++ b/lib/matejx_avr_lib/spi.h
@@ -0,0 +1,13 @@
+#ifndef MAT_SPI_H
+#define MAT_SPI_H
+
+#include
+#include
+
+// init SPI
+void spi_init(uint8_t fdiv);
+
+// send a byte over SPI
+uint8_t spi_rw(uint8_t d);
+
+#endif