/************************************************************************* Updated UART library (this one) by Andy Gock https://github.com/andygock/avr-uart Based on updated UART library (this one) by Tim Sharpe http://beaststwo.org/avr-uart/index.shtml Based on original library by Peter Fluery http://homepage.hispeed.ch/peterfleury/avr-software.html *************************************************************************/ /************************************************************************* Title: Interrupt UART library with receive/transmit circular buffers Author: Peter Fleury http://jump.to/fleury Software: AVR-GCC 4.1, AVR Libc 1.4.6 or higher Hardware: any AVR with built-in UART, License: GNU General Public License DESCRIPTION: An interrupt is generated when the UART has finished transmitting or receiving a byte. The interrupt handling routines use circular buffers for buffering received and transmitted data. The UART_RX_BUFFERn_SIZE and UART_TX_BUFFERn_SIZE variables define the buffer size in bytes. Note that these variables must be a power of 2. USAGE: Refer to the header file uart.h for a description of the routines. See also example test_uart.c. NOTES: Based on original library by Peter Fluery, Tim Sharpe, Nicholas Zambetti. Based on Atmel Application Note AVR306 LICENSE: Copyright (C) 2012 Andy Gock This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. LICENSE: Copyright (C) 2006 Peter Fleury This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. *************************************************************************/ /************************************************************************ uart_available, uart_flush, uart1_available, and uart1_flush functions were adapted from the Arduino HardwareSerial.h library by Tim Sharpe on 11 Jan 2009. The license info for HardwareSerial.h is as follows: HardwareSerial.cpp - Hardware serial library for Wiring Copyright (c) 2006 Nicholas Zambetti. All right reserved. This library is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) any later version. This library is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more details. You should have received a copy of the GNU Lesser General Public License along with this library; if not, write to the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA Modified 23 November 2006 by David A. Mellis ************************************************************************/ /************************************************************************ Changelog for modifications made by Tim Sharpe, starting with the current library version on his Web site as of 05/01/2009. Date Description ========================================================================= 05/11/2009 Changed all existing UARTx_RECEIVE_INTERRUPT and UARTx_TRANSMIT_INTERRUPT macros to use the "_vect" format introduced in AVR-Libc v1.4.0. Had to split the 3290 and 6490 out of their existing macro due to an inconsistency in the UART0_RECEIVE_INTERRUPT vector name (seems like a typo: USART_RX_vect for the 3290/6490 vice USART0_RX_vect for the others in the macro). Verified all existing macro register names against the device header files in AVR-Libc v1.6.6 to catch any inconsistencies. 05/12/2009 Added support for 48P, 88P, 168P, and 328P by adding them to the existing 48/88/168 macro. Added Arduino-style available() and flush() functions for both supported UARTs. Really wanted to keep them out of the library, so that it would be as close as possible to Peter Fleury's original library, but has scoping issues accessing internal variables from another program. Go C! 05/13/2009 Changed Interrupt Service Routine label from the old "SIGNAL" to the "ISR" format introduced in AVR-Libc v1.4.0. ************************************************************************/ /************************************************************************ Changelog for modifications made by Andy Gock, starting with the current library version by Tim Sharpe as of 05/13/2009. Date Description ========================================================================= 2013-05-19 - You can now use ring buffers over 256 bytes in size - Used "uint16_t" instead of "unsigned int" etc 2012-09-06 - Added peek functions - Updated URLs in source and README - Cleaned up some indenting to be more readable - Changed uart_functions() to uart0_functions - Added macros to allow legacy naming 2012-03-01 - Fixed errors in ISR vector names for various devices - Added USART2 and USART3 support to those devices with 4x USARTS. - Selective enabling of USART0,1,2,3 as required. (set in uart.h) ************************************************************************/ #include #include #include #include "uart.h" /* * constants and macros */ /* size of RX/TX buffers */ #define UART_RX0_BUFFER_MASK ( UART_RX0_BUFFER_SIZE - 1) #define UART_RX1_BUFFER_MASK ( UART_RX1_BUFFER_SIZE - 1) #define UART_RX2_BUFFER_MASK ( UART_RX2_BUFFER_SIZE - 1) #define UART_RX3_BUFFER_MASK ( UART_RX3_BUFFER_SIZE - 1) #define UART_TX0_BUFFER_MASK ( UART_TX0_BUFFER_SIZE - 1) #define UART_TX1_BUFFER_MASK ( UART_TX1_BUFFER_SIZE - 1) #define UART_TX2_BUFFER_MASK ( UART_TX2_BUFFER_SIZE - 1) #define UART_TX3_BUFFER_MASK ( UART_TX3_BUFFER_SIZE - 1) #if ( UART_RX0_BUFFER_SIZE & UART_RX0_BUFFER_MASK ) #error RX0 buffer size is not a power of 2 #endif #if ( UART_TX0_BUFFER_SIZE & UART_TX0_BUFFER_MASK ) #error TX0 buffer size is not a power of 2 #endif #if ( UART_RX1_BUFFER_SIZE & UART_RX1_BUFFER_MASK ) #error RX1 buffer size is not a power of 2 #endif #if ( UART_TX1_BUFFER_SIZE & UART_TX1_BUFFER_MASK ) #error TX1 buffer size is not a power of 2 #endif #if ( UART_RX2_BUFFER_SIZE & UART_RX2_BUFFER_MASK ) #error RX2 buffer size is not a power of 2 #endif #if ( UART_TX2_BUFFER_SIZE & UART_TX2_BUFFER_MASK ) #error TX2 buffer size is not a power of 2 #endif #if ( UART_RX3_BUFFER_SIZE & UART_RX3_BUFFER_MASK ) #error RX3 buffer size is not a power of 2 #endif #if ( UART_TX3_BUFFER_SIZE & UART_TX3_BUFFER_MASK ) #error TX3 buffer size is not a power of 2 #endif #if defined(__AVR_AT90S2313__) \ || defined(__AVR_AT90S4414__) || defined(__AVR_AT90S4434__) \ || defined(__AVR_AT90S8515__) || defined(__AVR_AT90S8535__) \ || defined(__AVR_ATmega103__) /* old AVR classic or ATmega103 with one UART */ #define AT90_UART #define UART0_RECEIVE_INTERRUPT UART_RX_vect #define UART0_TRANSMIT_INTERRUPT UART_UDRE_vect #define UART0_STATUS USR #define UART0_CONTROL UCR #define UART0_DATA UDR #define UART0_UDRIE UDRIE #elif defined(__AVR_AT90S2333__) || defined(__AVR_AT90S4433__) /* old AVR classic with one UART */ #define AT90_UART #define UART0_RECEIVE_INTERRUPT UART_RX_vect #define UART0_TRANSMIT_INTERRUPT UART_UDRE_vect #define UART0_STATUS UCSRA #define UART0_CONTROL UCSRB #define UART0_DATA UDR #define UART0_UDRIE UDRIE #elif defined(__AVR_ATmega8__) || defined(__AVR_ATmega16__) || defined(__AVR_ATmega32__) \ || defined(__AVR_ATmega323__) /* ATmega with one USART */ #define ATMEGA_USART #define UART0_RECEIVE_INTERRUPT USART_RXC_vect #define UART0_TRANSMIT_INTERRUPT USART_UDRE_vect #define UART0_STATUS UCSRA #define UART0_CONTROL UCSRB #define UART0_DATA UDR #define UART0_UDRIE UDRIE #elif defined(__AVR_ATmega8U2__) || defined(__AVR_ATmega16U2__) || defined(__AVR_ATmega16U4__) || \ defined(__AVR_ATmega32U2__) || defined(__AVR_ATmega32U4__) || defined(__AVR_ATmega32U6__) /* ATmega with one USART, but is called USART1 (untested) */ #define ATMEGA_USART1 #define UART1_RECEIVE_INTERRUPT USART1_RX_vect #define UART1_TRANSMIT_INTERRUPT USART1_UDRE_vect #define UART1_STATUS UCSR1A #define UART1_CONTROL UCSR1B #define UART1_DATA UDR1 #define UART1_UDRIE UDRIE1 #elif defined(__AVR_ATmega8515__) || defined(__AVR_ATmega8535__) /* ATmega with one USART */ #define ATMEGA_USART #define UART0_RECEIVE_INTERRUPT USART_RX_vect #define UART0_TRANSMIT_INTERRUPT USART_UDRE_vect #define UART0_STATUS UCSRA #define UART0_CONTROL UCSRB #define UART0_DATA UDR #define UART0_UDRIE UDRIE #elif defined(__AVR_ATmega163__) /* ATmega163 with one UART */ #define ATMEGA_UART #define UART0_RECEIVE_INTERRUPT UART_RX_vect #define UART0_TRANSMIT_INTERRUPT UART_UDRE_vect #define UART0_STATUS UCSRA #define UART0_CONTROL UCSRB #define UART0_DATA UDR #define UART0_UDRIE UDRIE #elif defined(__AVR_ATmega162__) /* ATmega with two USART */ #define ATMEGA_USART0 #define ATMEGA_USART1 #define UART0_RECEIVE_INTERRUPT USART0_RXC_vect #define UART1_RECEIVE_INTERRUPT USART1_RXC_vect #define UART0_TRANSMIT_INTERRUPT USART0_UDRE_vect #define UART1_TRANSMIT_INTERRUPT USART1_UDRE_vect #define UART0_STATUS UCSR0A #define UART0_CONTROL UCSR0B #define UART0_DATA UDR0 #define UART0_UDRIE UDRIE0 #define UART1_STATUS UCSR1A #define UART1_CONTROL UCSR1B #define UART1_DATA UDR1 #define UART1_UDRIE UDRIE1 #elif defined(__AVR_ATmega64__) || defined(__AVR_ATmega128__) /* ATmega with two USART */ #define ATMEGA_USART0 #define ATMEGA_USART1 #define UART0_RECEIVE_INTERRUPT USART0_RX_vect #define UART1_RECEIVE_INTERRUPT USART1_RX_vect #define UART0_TRANSMIT_INTERRUPT USART0_UDRE_vect #define UART1_TRANSMIT_INTERRUPT USART1_UDRE_vect #define UART0_STATUS UCSR0A #define UART0_CONTROL UCSR0B #define UART0_DATA UDR0 #define UART0_UDRIE UDRIE0 #define UART1_STATUS UCSR1A #define UART1_CONTROL UCSR1B #define UART1_DATA UDR1 #define UART1_UDRIE UDRIE1 #elif defined(__AVR_ATmega161__) /* ATmega with UART */ #error "AVR ATmega161 currently not supported by this libaray !" #elif defined(__AVR_ATmega169__) /* ATmega with one USART */ #define ATMEGA_USART #define UART0_RECEIVE_INTERRUPT USART0_RX_vect #define UART0_TRANSMIT_INTERRUPT USART0_UDRE_vect #define UART0_STATUS UCSRA #define UART0_CONTROL UCSRB #define UART0_DATA UDR #define UART0_UDRIE UDRIE #elif defined(__AVR_ATmega48__) ||defined(__AVR_ATmega88__) || defined(__AVR_ATmega168__) || \ defined(__AVR_ATmega48P__) ||defined(__AVR_ATmega88P__) || defined(__AVR_ATmega168P__) || \ defined(__AVR_ATmega328P__) /* TLS-Added 48P/88P/168P/328P */ /* ATmega with one USART */ #define ATMEGA_USART0 #define UART0_RECEIVE_INTERRUPT USART_RX_vect #define UART0_TRANSMIT_INTERRUPT USART_UDRE_vect #define UART0_STATUS UCSR0A #define UART0_CONTROL UCSR0B #define UART0_DATA UDR0 #define UART0_UDRIE UDRIE0 #elif defined(__AVR_ATtiny2313__) || defined(__AVR_ATtiny2313A__) || defined(__AVR_ATtiny4313__) #define ATMEGA_USART #define UART0_RECEIVE_INTERRUPT USART_RX_vect #define UART0_TRANSMIT_INTERRUPT USART_UDRE_vect #define UART0_STATUS UCSRA #define UART0_CONTROL UCSRB #define UART0_DATA UDR #define UART0_UDRIE UDRIE #elif defined(__AVR_ATmega329__) ||\ defined(__AVR_ATmega649__) ||\ defined(__AVR_ATmega325__) ||defined(__AVR_ATmega3250__) ||\ defined(__AVR_ATmega645__) ||defined(__AVR_ATmega6450__) /* ATmega with one USART */ #define ATMEGA_USART0 #define UART0_RECEIVE_INTERRUPT USART0_RX_vect #define UART0_TRANSMIT_INTERRUPT USART0_UDRE_vect #define UART0_STATUS UCSR0A #define UART0_CONTROL UCSR0B #define UART0_DATA UDR0 #define UART0_UDRIE UDRIE0 #elif defined(__AVR_ATmega3290__) ||\ defined(__AVR_ATmega6490__) /* TLS-Separated these two from the previous group because of inconsistency in the USART_RX */ /* ATmega with one USART */ #define ATMEGA_USART0 #define UART0_RECEIVE_INTERRUPT USART_RX_vect #define UART0_TRANSMIT_INTERRUPT USART0_UDRE_vect #define UART0_STATUS UCSR0A #define UART0_CONTROL UCSR0B #define UART0_DATA UDR0 #define UART0_UDRIE UDRIE0 #elif defined(__AVR_ATmega2560__) || defined(__AVR_ATmega1280__) || defined(__AVR_ATmega640__) /* ATmega with four USART */ #define ATMEGA_USART0 #define ATMEGA_USART1 #define ATMEGA_USART2 #define ATMEGA_USART3 #define UART0_RECEIVE_INTERRUPT USART0_RX_vect #define UART1_RECEIVE_INTERRUPT USART1_RX_vect #define UART2_RECEIVE_INTERRUPT USART2_RX_vect #define UART3_RECEIVE_INTERRUPT USART3_RX_vect #define UART0_TRANSMIT_INTERRUPT USART0_UDRE_vect #define UART1_TRANSMIT_INTERRUPT USART1_UDRE_vect #define UART2_TRANSMIT_INTERRUPT USART2_UDRE_vect #define UART3_TRANSMIT_INTERRUPT USART3_UDRE_vect #define UART0_STATUS UCSR0A #define UART0_CONTROL UCSR0B #define UART0_DATA UDR0 #define UART0_UDRIE UDRIE0 #define UART1_STATUS UCSR1A #define UART1_CONTROL UCSR1B #define UART1_DATA UDR1 #define UART1_UDRIE UDRIE1 #define UART2_STATUS UCSR2A #define UART2_CONTROL UCSR2B #define UART2_DATA UDR2 #define UART2_UDRIE UDRIE2 #define UART3_STATUS UCSR3A #define UART3_CONTROL UCSR3B #define UART3_DATA UDR3 #define UART3_UDRIE UDRIE3 #elif defined(__AVR_ATmega644__) /* ATmega with one USART */ #define ATMEGA_USART0 #define UART0_RECEIVE_INTERRUPT USART0_RX_vect #define UART0_TRANSMIT_INTERRUPT USART0_UDRE_vect #define UART0_STATUS UCSR0A #define UART0_CONTROL UCSR0B #define UART0_DATA UDR0 #define UART0_UDRIE UDRIE0 #elif defined(__AVR_ATmega164P__) || defined(__AVR_ATmega324P__) || defined(__AVR_ATmega644P__) || \ defined(__AVR_ATmega1284P__) /* ATmega with two USART */ #define ATMEGA_USART0 #define ATMEGA_USART1 #define UART0_RECEIVE_INTERRUPT USART0_RX_vect #define UART1_RECEIVE_INTERRUPT USART1_RX_vect #define UART0_TRANSMIT_INTERRUPT USART0_UDRE_vect #define UART1_TRANSMIT_INTERRUPT USART1_UDRE_vect #define UART0_STATUS UCSR0A #define UART0_CONTROL UCSR0B #define UART0_DATA UDR0 #define UART0_UDRIE UDRIE0 #define UART1_STATUS UCSR1A #define UART1_CONTROL UCSR1B #define UART1_DATA UDR1 #define UART1_UDRIE UDRIE1 #else #error "no UART definition for MCU available" #endif /* * Module global variables */ #if defined( USART0_ENABLED ) #if defined( ATMEGA_USART ) || defined( ATMEGA_USART0 ) static volatile uint8_t UART_TxBuf[UART_TX0_BUFFER_SIZE]; static volatile uint8_t UART_RxBuf[UART_RX0_BUFFER_SIZE]; #if defined( USART0_LARGE_BUFFER ) static volatile uint16_t UART_TxHead; static volatile uint16_t UART_TxTail; static volatile uint16_t UART_RxHead; static volatile uint16_t UART_RxTail; static volatile uint8_t UART_LastRxError; #else static volatile uint8_t UART_TxHead; static volatile uint8_t UART_TxTail; static volatile uint8_t UART_RxHead; static volatile uint8_t UART_RxTail; static volatile uint8_t UART_LastRxError; #endif #endif #endif #if defined( USART1_ENABLED ) #if defined( ATMEGA_USART1 ) static volatile uint8_t UART1_TxBuf[UART_TX1_BUFFER_SIZE]; static volatile uint8_t UART1_RxBuf[UART_RX1_BUFFER_SIZE]; #if defined( USART1_LARGE_BUFFER ) static volatile uint16_t UART1_TxHead; static volatile uint16_t UART1_TxTail; static volatile uint16_t UART1_RxHead; static volatile uint16_t UART1_RxTail; static volatile uint8_t UART1_LastRxError; #else static volatile uint8_t UART1_TxHead; static volatile uint8_t UART1_TxTail; static volatile uint8_t UART1_RxHead; static volatile uint8_t UART1_RxTail; static volatile uint8_t UART1_LastRxError; #endif #endif #endif #if defined( USART2_ENABLED ) #if defined( ATMEGA_USART2 ) static volatile uint8_t UART2_TxBuf[UART_TX2_BUFFER_SIZE]; static volatile uint8_t UART2_RxBuf[UART_RX2_BUFFER_SIZE]; #if defined( USART2_LARGE_BUFFER ) static volatile uint16_t UART2_TxHead; static volatile uint16_t UART2_TxTail; static volatile uint16_t UART2_RxHead; static volatile uint16_t UART2_RxTail; static volatile uint8_t UART2_LastRxError; #else static volatile uint8_t UART2_TxHead; static volatile uint8_t UART2_TxTail; static volatile uint8_t UART2_RxHead; static volatile uint8_t UART2_RxTail; static volatile uint8_t UART2_LastRxError; #endif #endif #endif #if defined( USART3_ENABLED ) #if defined( ATMEGA_USART3 ) static volatile uint8_t UART3_TxBuf[UART_TX3_BUFFER_SIZE]; static volatile uint8_t UART3_RxBuf[UART_RX3_BUFFER_SIZE]; #if defined( USART3_LARGE_BUFFER ) static volatile uint16_t UART3_TxHead; static volatile uint16_t UART3_TxTail; static volatile uint16_t UART3_RxHead; static volatile uint16_t UART3_RxTail; static volatile uint8_t UART3_LastRxError; #else static volatile uint8_t UART3_TxHead; static volatile uint8_t UART3_TxTail; static volatile uint8_t UART3_RxHead; static volatile uint8_t UART3_RxTail; static volatile uint8_t UART3_LastRxError; #endif #endif #endif #if defined(AT90_UART) || defined(ATMEGA_USART) || defined(ATMEGA_USART0) ISR(UART0_RECEIVE_INTERRUPT) /************************************************************************* Function: UART Receive Complete interrupt Purpose: called when the UART has received a character **************************************************************************/ { uint16_t tmphead; uint8_t data; uint8_t usr; uint8_t lastRxError; /* read UART status register and UART data register */ usr = UART0_STATUS; data = UART0_DATA; /* */ #if defined( AT90_UART ) lastRxError = (usr & (_BV(FE)|_BV(DOR)) ); #elif defined( ATMEGA_USART ) lastRxError = (usr & (_BV(FE)|_BV(DOR)) ); #elif defined( ATMEGA_USART0 ) lastRxError = (usr & (_BV(FE0)|_BV(DOR0)) ); #elif defined ( ATMEGA_UART ) lastRxError = (usr & (_BV(FE)|_BV(DOR)) ); #endif /* calculate buffer index */ tmphead = ( UART_RxHead + 1) & UART_RX0_BUFFER_MASK; if ( tmphead == UART_RxTail ) { /* error: receive buffer overflow */ lastRxError = UART_BUFFER_OVERFLOW >> 8; } else { /* store new index */ UART_RxHead = tmphead; /* store received data in buffer */ UART_RxBuf[tmphead] = data; } UART_LastRxError = lastRxError; } ISR(UART0_TRANSMIT_INTERRUPT) /************************************************************************* Function: UART Data Register Empty interrupt Purpose: called when the UART is ready to transmit the next byte **************************************************************************/ { uint16_t tmptail; if ( UART_TxHead != UART_TxTail) { /* calculate and store new buffer index */ tmptail = (UART_TxTail + 1) & UART_TX0_BUFFER_MASK; UART_TxTail = tmptail; /* get one byte from buffer and write it to UART */ UART0_DATA = UART_TxBuf[tmptail]; /* start transmission */ } else { /* tx buffer empty, disable UDRE interrupt */ UART0_CONTROL &= ~_BV(UART0_UDRIE); } } /************************************************************************* Function: uart0_init() Purpose: initialize UART and set baudrate Input: baudrate using macro UART_BAUD_SELECT() Returns: none **************************************************************************/ void uart0_init(uint16_t baudrate) { UART_TxHead = 0; UART_TxTail = 0; UART_RxHead = 0; UART_RxTail = 0; #if defined( AT90_UART ) /* set baud rate */ UBRR = (uint8_t)baudrate; /* enable UART receiver and transmitter and receive complete interrupt */ UART0_CONTROL = _BV(RXCIE)|_BV(RXEN)|_BV(TXEN); #elif defined (ATMEGA_USART) /* Set baud rate */ if ( baudrate & 0x8000 ) { UART0_STATUS = (1<>8); UBRRL = (uint8_t) baudrate; /* Enable USART receiver and transmitter and receive complete interrupt */ UART0_CONTROL = _BV(RXCIE)|(1<>8); UBRR0L = (uint8_t) baudrate; /* Enable USART receiver and transmitter and receive complete interrupt */ UART0_CONTROL = _BV(RXCIE0)|(1<>8); UBRR = (uint8_t) baudrate; /* Enable UART receiver and transmitter and receive complete interrupt */ UART0_CONTROL = _BV(RXCIE)|(1<> 8; } else { /* store new index */ UART1_RxHead = tmphead; /* store received data in buffer */ UART1_RxBuf[tmphead] = data; } UART1_LastRxError = lastRxError; } ISR(UART1_TRANSMIT_INTERRUPT) /************************************************************************* Function: UART1 Data Register Empty interrupt Purpose: called when the UART1 is ready to transmit the next byte **************************************************************************/ { uint16_t tmptail; if ( UART1_TxHead != UART1_TxTail) { /* calculate and store new buffer index */ tmptail = (UART1_TxTail + 1) & UART_TX1_BUFFER_MASK; UART1_TxTail = tmptail; /* get one byte from buffer and write it to UART */ UART1_DATA = UART1_TxBuf[tmptail]; /* start transmission */ } else { /* tx buffer empty, disable UDRE interrupt */ UART1_CONTROL &= ~_BV(UART1_UDRIE); } } /************************************************************************* Function: uart1_init() Purpose: initialize UART1 and set baudrate Input: baudrate using macro UART_BAUD_SELECT() Returns: none **************************************************************************/ void uart1_init(uint16_t baudrate) { UART1_TxHead = 0; UART1_TxTail = 0; UART1_RxHead = 0; UART1_RxTail = 0; /* Set baud rate */ if ( baudrate & 0x8000 ) { UART1_STATUS = (1<>8); UBRR1L = (uint8_t) baudrate; /* Enable USART receiver and transmitter and receive complete interrupt */ UART1_CONTROL = _BV(RXCIE1)|(1<> 8; } else { /* store new index */ UART2_RxHead = tmphead; /* store received data in buffer */ UART2_RxBuf[tmphead] = data; } UART2_LastRxError = lastRxError; } ISR(UART2_TRANSMIT_INTERRUPT) /************************************************************************* Function: UART2 Data Register Empty interrupt Purpose: called when the UART2 is ready to transmit the next byte **************************************************************************/ { uint16_t tmptail; if ( UART2_TxHead != UART2_TxTail) { /* calculate and store new buffer index */ tmptail = (UART2_TxTail + 1) & UART_TX2_BUFFER_MASK; UART2_TxTail = tmptail; /* get one byte from buffer and write it to UART */ UART2_DATA = UART2_TxBuf[tmptail]; /* start transmission */ } else { /* tx buffer empty, disable UDRE interrupt */ UART2_CONTROL &= ~_BV(UART2_UDRIE); } } /************************************************************************* Function: uart2_init() Purpose: initialize UART2 and set baudrate Input: baudrate using macro UART_BAUD_SELECT() Returns: none **************************************************************************/ void uart2_init(uint16_t baudrate) { UART2_TxHead = 0; UART2_TxTail = 0; UART2_RxHead = 0; UART2_RxTail = 0; /* Set baud rate */ if ( baudrate & 0x8000 ) { UART2_STATUS = (1<>8); UBRR2L = (uint8_t) baudrate; /* Enable USART receiver and transmitter and receive complete interrupt */ UART2_CONTROL = _BV(RXCIE2)|(1<> 8; } else { /* store new index */ UART3_RxHead = tmphead; /* store received data in buffer */ UART3_RxBuf[tmphead] = data; } UART3_LastRxError = lastRxError; } ISR(UART3_TRANSMIT_INTERRUPT) /************************************************************************* Function: UART3 Data Register Empty interrupt Purpose: called when the UART3 is ready to transmit the next byte **************************************************************************/ { uint16_t tmptail; if ( UART3_TxHead != UART3_TxTail) { /* calculate and store new buffer index */ tmptail = (UART3_TxTail + 1) & UART_TX3_BUFFER_MASK; UART3_TxTail = tmptail; /* get one byte from buffer and write it to UART */ UART3_DATA = UART3_TxBuf[tmptail]; /* start transmission */ } else { /* tx buffer empty, disable UDRE interrupt */ UART3_CONTROL &= ~_BV(UART3_UDRIE); } } /************************************************************************* Function: uart3_init() Purpose: initialize UART3 and set baudrate Input: baudrate using macro UART_BAUD_SELECT() Returns: none **************************************************************************/ void uart3_init(uint16_t baudrate) { UART3_TxHead = 0; UART3_TxTail = 0; UART3_RxHead = 0; UART3_RxTail = 0; /* Set baud rate */ if ( baudrate & 0x8000 ) { UART3_STATUS = (1<>8); UBRR3L = (uint8_t) baudrate; /* Enable USART receiver and transmitter and receive complete interrupt */ UART3_CONTROL = _BV(RXCIE3)|(1<