	Everest MC3 Configuration Registers
	-----------------------------------

Configuration Registers are used to read and alter the operating 
parameters of the EMM. They are accessed via Configuration Read and 
Configuration Write commands on the Everest Bus. The following table 
shows the address and function of the Configuration Registers in the 
EMM.

Table  2	Memory Board Configuration Registers

The following registers are per board, not per leaf:

Reg# 	Width	RW	Reset Value	Description / Use
-----------------------------------------------------------------------
00	8	RW	0x0		Bank Enable
01	32	R	0x2		Board Type
02	32	R	0x0		Rev. Level
03	3	RW	0x2		Access Control
04	17	RW	0x13322		Memory Error Interrupt Register
05	17	RW	0x13422		EBUS Error Interrupt Register
06	20	RW	0x0		BIST result register
07	20	RW	0xfffff		DRSC timeout register( s)
08	4	Rclear 	0x0		EBUS error register
09	0	W	-		Refresh Count Initialize
0A	4	RW	0xf		Leaf Control Enable
0F	0	W	-		Board Reset


The following registers are per leaf:

Reg#	Width	R/W	Reset Value	Description / Use
----------------------------------------------------------------------
10	3	RW	<simm 0>	Bank 0 Size
11	32	RW	-		Bank 0 Base Address
12	3	RW	-		Bank 0 Interleave Factor
13	4	RW	-		Bank 0 Interleave Position
14	3	RW	<simm 1>	Bank 1 Size
15	32	RW	-		Bank 1 Base Address
16	3	RW	-		Bank 1 Interleave Factor
17	4	RW	-		Bank 1 Interleave Position
18	3	RW	<simm 0>	Bank2 Size
19	32	RW	-		Bank 2 Base Address
1a	3	RW	-		Bank 2 Interleave Factor
1b	4	RW	-		Bank 2 Interleave Position
1c	3	RW	<simm 1>	Bank 3 Size
1d	32	RW	-		Bank 3 Base Address
1e	3	RW	-		Bank 3 Interleave Factor
1f	4	RW	-		Bank 3 Interleave Position
20	4	R	0x0		Error Status
21	4	Rclear	0x0		Error Status, clear on read
22	8	R	-		ErrorAddressHigh
23	32	R	-		ErrorAddressLow
24	24	RW	0x0		Bist status register
30	16	R	-		Syndrome slice 0
31	16	R	-		Syndrome slice 1
32	16	R	-		Syndrome slice 2
33	16	R	-		Syndrome slice 3

Notes:
	Register numbers shown are for leaf 0. 
	Add 0x40 to get register values for leaf 1

	Currently, leaf registers can only be read if
	at least one of the banks in the leaf is enabled.
	Leaf registers may be written at any time regardless
	of the state of the bank enable register.  This
	limitation is subject to change.

Per-Board Register Descriptions
-------------------------------

0x0	  Bank Enable Register			8 Bits, RW
	Enables banks 0 - 7 as shown below:
	 _______________________________________________________________
	| L1 B3	| L1 B2	| L0 B3 | L0 B2 | L1 B1 | L1 B0 | L0 B1 | L0 B0 |
	+---------------------------------------------------------------+ 
	 Bit 7	 Bit 6	 Bit 5	 Bit 4	 Bit 3 	 Bit 2	 Bit 1 	 Bit 0

	In order to read a leaf's configuration registers, at least
	one of the banks in that leaf must be enabled.


0x1	  Board Type Register 			32 Bits, RO
	Returns a value of 00000002, indicating an Everest Memory Module.


0x2	  Revision Level Register 		32 Bits, RO
	Returns a value corresponding to the boards revision level. Exact 
	format is TBD. 


0x3	  Access Control Register		3 Bits, RW
	The format of this register is shown below. Bit 0 controls the 
	endian mode of the EMM. Big endian systems write a one to this field 
	before accessing memory. Bit 1 is the subblock order bit (1=sub block 
	order) amd bit 2 is 64 bit Everest bus (1=64 bit bus). On reset, the 
	default setting is 256 bit data bus, sub-block ordering enabled and 
	little endian addressing.
	 _____________________________________
	| Ebus64 | SubBlockOrder | Endianness |
	+-------------------------------------+
	     2           1              0


0x4	  Memory Error Interrupt Register	17 Bits, RW
	Specifies the interrupt destination and priority used by the EMM 
	in reporting memory parity errors.  This interrupt is only generated
	when the memory board detects the error during a read from its own
        memory.  The format of the Error Interrupt Register is 
	shown below: 
	 _____________________________________________
	| IntEnb | Int Priority | 0 | Int Destination |
	+---------------------------------------------+
            16    15           8  7  6               0


0x5	  EBUS Error Interrupt Register		17 Bits, RW
	Specifies the interrupt destination and priority used when parity
	errors on EBUS memory transactions are detected.  Basically, this
	interrupt will be generated if the EMM detects bogus parity values
	coming in from the EBUS. The format of the Error Interrupt Register 
	is shown below. 
	 _____________________________________________
	| IntEnb | Int Priority | 0 | Int Destination |
	+---------------------------------------------+
	    16    15           8  7  6		     0


0x6	  BIST Result Register			20 Bits, RW 
	A self test of the memory board is performed by clearing the BIST 
	result register register, i.e. writing 0. The progress of the BIST can 
	be followed by polling this register and checking the BIST in 
	Progress bits. Each progress bit corresponds to one of the memory 
	leaves; when the leaf is undergoing testing its progress bit is set. 
	Once the test completes, software can read the signature values to
	determine which banks have passed or failed the BIST.

	+---------------------------------------------------------------+
	| Reserved | L1 Sig | L0 Sig | Resrvd | L1 in Prog | L0 in Prog |
	+---------------------------------------------------------------+
	 19      12 11     8 7      4 3      2      1            0

*** Need to determine whether a '1' in sig means bank passed or failed.


0x7	  DRSC Timeout Register			20 Bits, RW
	This Register contains the timeout value for the data resource
	wait hardware.  In order to prevent data resources from being
	held forever (which really shouldn't happen, but could in the
	event of partial system failure), all boards in the system provide
	a timeout which 	

0x8	  EBUS Error Register			4 Bits, R(clear)
	Records the type of error which occurred.  Writing to this 
	register resets all four of the error bits.  Since the MC3 can
	arbitrate for the EBUS's address path, it can potentially get
	address and data errors during these attempts.  If ADDR_ERR is
	asserted by any receiving board, then SenderEbusAddrErr is set
	and an interrupt is generated.  If DATA_P_ERR is asserted, this
	is recorded in the SenderEbusDataErr and no interrupt is generated.
	If the EMM detects an address or data error during a transaction
	initiated by another board, it sets the EbusAddrErr or the EbusDataErr
	register appropriately.
	 ___________________________________________________________________
	| SenderEbusAddrErr | SenderEbusDataErr | EbusAddrErr | EbusDataErr |
	+-------------------------------------------------------------------+
	          3                   2                1             0


0x9	  Refresh Count Initialize		0 Bits, WO
	By writing this register, a program can reset the memory refresh
	clock to zero.  This is done to ensure a consistent hardware testing
	environment, and really isn't needed during regular operation.  


0xA	  Leaf Control Enable			4 Bits, RW
	Enables servicing of transactions by a given leaf.  Regardless
	of the state of this bit, the leaf controllers always service
	refreshes.


0xF	  Board Reset				0 Bits, WO
	Writing a 1 to this register is equivalent to performing a system
	reset, except that only the addressed board is affected.  All 
	circuitry in the board is initialized, and any pending board
	operations are lost.



Per-Leaf Register Descriptions
------------------------------

  The following register numbers are for leaf 0.  To get the register
numbers of leaf 1, simply add 0x40

0x10	  Bank 0 Size				3 Bits, RW
	This register contains a value representing the amount of
	memory installed in the bank, if any.  The legal values for
	this register are given below:

	Code    Size                            DRAM Type
	----	-----				----------
	0       16 meg (256 K X 144 SIMMs)      256 K X 4 or 256 K X 18
	1       64 meg (1 M X 144 SIMMs)        1 M X 4 or 1 M X 18
	2       128 meg (2 M X 144 SIMMs)       2 M X 9
	3       256 meg (4 M X 144 SIMMs)       4 M X 4 or 4 M X 18
	4       256 meg (4 M X 144 SIMMs)       4 M X 4 or 4 M X 18, asymmetric
	5       1024 meg (16 M X 144 SIMMs)     16 M X 4
	6       1024 meg (16 M X 144 SIMMs)    16 M X 4, asymmetric
	7       Indicates bank not installed.

	BIST for a particular bank may be disabled by writing a 7 into 
	that bank's size register.


0x11	  Bank 0 Base Address			32 Bits, RW
	This register contains the most-significant 32 bits of the 
	of the base address of the range of memory contained within
	this bank. All of the banks in an interleave must have the same
	base address value.

 
0x12	  Bank 0 Interleave Factor		3 Bits, RW
	This register must be set by software to indicate the number of 
	banks which are interleaved with the addressed bank. The interleave 
	factor must be set before accessing the memory bank. The legal values 
	for interleave factor are shown in the table below. 

	Code    Interleave Factor       Legal Interleave Positions
	----	-----------------	--------------------------
	0       1 -way                  0
	1       2 - way                 0, 1
	2       4 - way                 0 .. 3
	3       8 - way                 0 .. 7


0x13	  Bank 0 Interleave Position		4 Bits, RW
	Indicate the interleave position of the addressed bank.            
	The interleave position must be set before accessing the memory
	bank. The legal values for interleave position range from 0 up to
	one less than the number of ways the memory is interleaved, with
	one bank assigned to each possible position.


0x14	  Bank 1 Size				3 Bits, RW
	See description of the Bank 0 Size register.

0x15	  Bank 1 Base Address 			32 Bits, RW
	See description of the Bank 0 Base Address register.

0x16	  Bank 1 Interleave Factor		3 Bits, RW
	See description of the Bank 0 Interleave Factor register.

0x17	  Bank 1 Interleave Position		4 Bits, RW
	See description of the Bank 0 Interleave Position register.

0x18      Bank 2 Size                           3 Bits, RW
	See description of the Bank 0 Size register.
        
0x19      Bank 2 Base Address                   32 Bits, RW     
	See description of the Bank 0 Base Address register.	

0x1a      Bank 2 Interleave Factor              3 Bits, RW
	See description of the Bank 0 Interleave Factor register.

0x1b      Bank 2 Interleave Position            4 Bits, RW      
	See description of the Bank 0 Interleave Position register.

0x1c      Bank 3 Size                           3 Bits, RW      
	See description of the Bank 0 Size register.

0x1d      Bank 3 Base Address                   32 Bits, RW     
	See description of the Bank 0 Base Address register.

0x1e      Bank 3 Interleave Factor              3 Bits, RW      
	See description of the Bank 0 Interleave Factor register.

0x1f      Bank 3 Interleave Position            4 Bits, RW      
	See description of the Bank 0 Interleave Position register.


0x20	  Error Status				4 Bits, RO
	Indicates whether any one of four possible error conditions
	has occurred.  The four error conditions recorded in the
	register are MultipleError, which occurs when a number of
	problems occur; ReadSingleError, which is set when a correctable
	single bit error is detected; ReadUncorrectableError, which is set
	when an uncorrectable error occurs on read; and 
	PartialWriteUncorrectableError, which (besides having an incredibly
	long and unwieldy name)	is set when an uncorrectable error is 
	encountered during a partial write attempt.  When either a 	
	ReadSingleError or a PartialWriteUncorrectableError occur,
	an interrupt is generated if the InterruptEnable bit is set in the
	Error Interrupt register.  If only one bit in this register is
	set, it is possible to use the Syndrome Slice registers to determine
	the exact bit which is causing problems.  However, if two or more
	bits are set, the data in the Syndrome Slice registers is no 
	longer valid. 
	 ____________________________________________________________
	| MultError | ReadSnglError | ReadUncError | PartWrtUncError |
	+------------------------------------------------------------+
	      3             2               1               0


0x21	  Error Status Clear 			4 Bits, R(clear)
	The contents of this register are identical to those of 
	the Error Status register.  However, this register provides
	atomic read-and-clear functionality and should be used when
	the software no longer needs the previous error states.


0x22	  ErrorAddressHigh			8 Bits, RO
	Contains the high 8 bits (bits 39-32) of the address used in the
	last memory operation to the leaf controller which resulted in 
	an error.

0x23	  ErrorAddressLow			32 Bits, RO
	Contains the low 32 bits (bits 31-0) of the address used in the
	last memory operation to the leaf controller which resulted in
	an error. 


0x24	  BIST Status Register			24 Bits, RW
	Records the status of the BIST for each bank as it executes.
	The BIST is performed in six stages.  As each stage completes,
	a bit is written into the status register. 


0x30	  Syndrome Slice 0			16 Bits, RO

0x31	  Syndrome Slice 1			16 Bits, RO

0x32	  Syndrome Slice 2			16 Bits, RO

0x33	  Syndrome Slice 3			16 Bits, RO

	The Syndrome Slice registers can be used to determine in many
	circumstances which bit generated a particular error.  The algorithm 
	for this is reasonably complicated; if you need to be able to do 
	this, see Unmesh.
