
		Processor Board Test Strategy and Schedule:
		-------------------------------------------
================================ R4K ============================
   What's done so far?
	o took R4000 class (2 days class) (prerequisite for R10000 class)
	o went thru existing cpu tests and identified the problems
	o listed the limitation of the existing tests:
	   - run under IDE ; makes fault isolation difficult
	   - the tests turn on and off the cache
	   - the tests assume that the memory is working while testing cache
	   - the coverage is limited
	   - isolation of secondary cache at the chip level is lacking
	o ported cache tests from IP22 to IP30 - to be used by emulator

   What needs to be done in the near future?
	o port TLB tests from IP22 to IP30 - to be used by emulator
		[HERVE  06/14]
	o cache diags under IP30 need to be verified by running thru emulator
		[HERVE   07/13]

================================ T5 ============================
   What's done so far?
	o took 2nd part of R10000 class from MTI
	o studied differences between R4K and R10000
	o talked to HE diag/engr for general approach (on going)
	o scanned many MTI tests (mostly assembly)  (on going)
	o talked to DVT (design verif simulation team) people (on going)

   What needs to be done in the near future?
	o talk to MIPS about T5 architecture, tests and simulator
		[HERVE  06/12]
	o talk to ISD about the processor board bringup plan and tests
		[HERVE  06/20]
	o talk to ISD diagnostics about T5 tests in the PROM
		[HERVE  06/15]
	o talk to HE diag/engr group about multiprocessing tests
		[HERVE  06/23]
	o glue all the information above and come up with a test plan
		[HERVE  06/30]   (plain ASCII, 
	o investigate the mini-kernel running environment for our diags
		[HERVE  06/20]

================================ R4K/T5 ============================
   What's done so far?
	o came up with a new cpu testing approach
	   - test basic Processor module from PROM
	   - test basic cache functionality
	   - move the tests in Primary cache.
	   - test more the cache logic within the CPU
	   - test the 2nd cache.
	   - test basic HEART registers (repackage kkn tests).
	   - test memory from CPU cache (repackage some davidl tests)
	   - test Heart UP and MP functionality (MP random tests from MTI)
	o identified additional/better tests
    	   - prom small checksum test
    	   - prom full checksum test
    	   - nvram test
    	   - CPU register tests
    	   - CPU basic instructions ( some from Mips tests).
    	   - FPU tests (mostly porting from MIPS, investigate coverage)
    	   - exceptions tests.
	   - software trap test (synch tests)
	   - interrupts tests (asynch tests)

   What needs to be done in the near future?
	o a mfg diagnostic plan needs to be developed
	  (functional as well as stress tests)
           *** check if jkwong expects this for 06/30 as well
               can come up with an outline and some ideas by
                06/30
		[HERVE  06/30 ? ]


		IP30 Board Test Strategy and Schedule:
		--------------------------------------
================================ HEART ============================
   What's done so far?
	o level 1 plan for the emulator was written and reviewed
	o a set of level 0 diags have been written for the emulator
	o we've done a code walk thru on these tests
	o the test includes basic register check-out and simple
	  functionality test

   What needs to be done in the near future?
	o diags have to be verified by running thru the emulator
		[KKN ANOUCHKA 07/14]
	o a mfg diagnostic plan needs to be developed
	  (functional as well as stress tests)
		[KKN 06/30]

================================ BRIDGE ============================
   What's done so far?
	o level 1 plan for the emulator is written and reviewed

   What needs to be done in the near future?
	o level 1 diags have to be implemented and reviewed
		[KKN ANOUCHKA 06/16]
	o level 1 diags have to be verified by running thru the emulator
		[KKN ANOUCHKA 07/21]
	o level 2 plan has to be written
		[KKN ANOUCHKA 06/23]
	o level 2 diags have to be implemented and reviewed
		[KKN ANOUCHKA 07/14]
	o level 2 diags have to be verified by running thru the emulator
		[KKN ANOUCHKA 07/28]
	o a mfg diagnostic plan needs to be developed
		(functional as well as stress tests)
		[KKN 07/14]

================================ HEART/BRIDGE SYSTEM ============================
	This is exclusively for the emulator. In the phase I of the emulator
	bringup, we are going to have R4K, Cache,  Memory, Heart, Bridge, Prom
	and Serial Port. In order to test this system, we have to develop a
	system level diags that will involve most/all of them.
   What's done so far?
	o had very informal discussions about who will do what

   What needs to be done in the near future?
	o a system level diag plan needs to be written
		[ANOUCHKA 06/23]
	o diags have to be implemented and reviewed
		[KKN ANOUCHKA 06/30]
	o diags have to be verified by running thru the emulator
		[KKN ANOUCHKA 07/28]

================================ XBOW ============================
   What's done so far?
	o no plans for the emulator yet.
	o wrote a preliminary plan for mfg
	o had a discussion with HE I/O diag group to share the effort
	  (no feedback from them yet)

   What needs to be done in the near future?
	o a mfg disgnostic plan needs to be developed
		(functional as well as stress tests)
		[KKN 07/28]

================================ IOC3 ============================
   What's done so far?
	o nothing

   What needs to be done in the near future?
	o work with HE I/O diag group and see if we can share the effort


================================ SYSTEM ISSUES ============================
   o debug prom development and it's associated disgnostics
   o additional cache tests can be emulated ONLY if time permits
   o stress test strategy
	- must involve graphics/video/compression/ethernet options
	- multiprocessing tests
   o board repair plan
	- use virtual back plane technique to debug the boot path
	- develop a stand alone processor to debug the boot path
   o simulation efforts

================================ DIAG ISSUES ============================
   o need at least one more engineer for our group


Schedule of events:
-------------------
KKN:
---
06/16	- Bridge level 1 implemented 
06/23 	- Bridge level 2 plan 
06/23 	- Heart/Bridge plan 
06/30	- Heart/Bridge implemented 
06/30	- Heart MFG Plan
07/14	- Bridge level 2 implemented
07/14	- Heart level 1 emulated
07/21	- Bridge level 1 emulated
07/28	- Bridge level 2 emulated
07/28	- Bridge MFG Plan

HERVE:
-----
06/12	- talk to MIPS about T5 architecture, tests and simulator
06/14	- port TLB tests from IP22 to IP30 - to be used by emulator
06/15	- talk to ISD diagnostics about T5 tests in the PROM
06/20	- talk to ISD about the processor board bringup plan and tests
06/20	- investigate the mini-kernel running environment for our diags
06/23	- talk to HE diag/engr group about multiprocessing tests
06/30	- glue all the information above and come up with a test plan
06/30	- a mfg diagnostic plan needs to be developed
	  *** check if jkwong expects this for 06/30 as well
	  can come up with an outline and some ideas by 06/30

