
			RADICAL IDE COMMANDS

The following is the list of commands available to use IDE 

====================================COMMANDS=========================
rad_regs		rad_dma		rad_ram	rad_all_cards	radical
shoebox_all	shoebox

Description of Commands and how to use them
================================================================================
The following individual operations can be run:

rad_regs
---------
Performs write/read/verify tests on all rad registers. 
Data flows from main memory, to heart, to xbow, to bridge, to rad chip registers
Usage: rad_regs [-s1|2|3]
Default: tests IP30 rad chip
Options: specify slot # in pci shoebox
-s1 tests radical card 1 
-s2 tests radical card 2
-s3 tests radical card 3

rad_dma
---------
Perform status dma from chip to memory, and verifies that DMA was done
Data flows from main memory, to heart, to xbow, to bridge, to rad dma registers
Usage: rad_dma [-s1|2|3]
Default and options same as in rad_regs test

rad_ram
---------
Performs write/read/verify tests on dma registers
Data flows from main memory, to heart, to xbow, to bridge, to rad ram
Usage: rad_ram [-s1|2|3]
Default and options same as in rad_regs test

rad_all_cards
-------------
Runs all radical tests on one specified card.
Usage: rad_all_cards [-s1|2|3]
Default and options same as in rad_regs test

radical
---------
Tests all cards running all rad tests. Boots unix if tests passes

shoebox_all
-----------
Runs the following bridge tests: 
	br_regs
	------
	Performs write/read/verify tests. The register contents are saved.
	Then a pattern is written. It is read back and verified. The contents
	of the register are restored on exit.
	Data flows from main memory, to heart, to xbow, to bridge registers

	br_ram
	------
	Tests built in bridge memory. Performs write/read/verify tests. A
	pattern is written to memory. It is read back and verified.
	Data flows from main memory, to heart, to xbow, to bridge ram

	br_intr
	-------
	A bridge interrupt is generated by writing the INTR bit. The test then
	verifies that the interrupt occurred
	Data flows from main memory, to heart, to xbow, to bridge intr registers

	br_err
	-------
	This test the ability of the bridge to generate errors when writing to a bad bridge 
	address. Errors are created by writing to invalid addresses. The test verifies that
	bridge caught the error.
	Data flows from main memory, to heart, to xbow, to bridge err registers

shoebox
-------
Runs all bridge tests documented above (in shoebox_all) and boots unix if they passed
