			SPEED RACER IDE COMMANDS



The following is the list of commands available to use IDE 

====================================TOOL COMMANDS=========================
help_mem 	led		wait		bufon				
ldram		lkh		memtest		ecctest
dcache1		icache1		icache2		scache1
scache2		ct		tlb		utlb
hr_regs		hr_rd		hr_wr		hr_piuacc
hr_intr		hr_misc		hr_piowcr	x_regs
x_reset		x_acc		hx_badllp	x_rd
x_wr		br_regs		br_ram		br_intr
br_rd		br_wr		br_err		hb_status
hb_badllp	hb_savreg	hb_rstreg	hb_flow
hb_chkout	hb_reset	hxb_savreg	hxb_rstreg
hxb_chkout	hxb_reset	hxb_status	duart_regs
pci_sio		pci_par		rtc_regs	pci_rtc
chg_volt	fpu		lpackd		ioc3_regs
ioc3_sram	scsi_test	rad_regs	rad_dma
rad_ram		nic_check

Description of Commands and how to use them
================================================================================
The following individual operations can be run:

			PM10 tests
help_mem
-------
The help command displays the memory map.
Usage: help_mem

led
----
Sets the led color indicator
Usage: led

wait
----
Wait for a specified message before continuing
Usage: wait

bufon
------
Turn on message buffering
Usage: bufon

ldram
--------
Memory tests are performed on low dram. Different patterns are written to memory,
read back and verified (w/r/v or write/read/verify) for correctness.
Usage: ldram

lkh
----
Knaizuk Hartmann memory test is performed on low DRAM 
Usage: lkh

memtest
-------
Performs memory write/read/verify operations in DRAM
Usage: mem test

ecctest
-------
Error data is written to memory. The heart is set to ecc single bit mode
It is verified that the error data got corrected.
The same is repeated for double  multi bit errors.
Usage: ecctest

dcache1
-------
Data cache parity test is performed on the data cache
Usage: dcache1

icache1 
-------
Data cache parity test is performed on the instruction cache
Usage: icache1


icache2 
-------
Data, address, invalidate tag, instruction fetch, and fill tests are performed 
on instruction cache
cache
Usage: icache1


scache1
-------
ECC tests are performed on secondary cache
Usage: scache1 


scache2
-------
Secondary cache address and data test
Usage: scache2

ct
--
Cache thrasher test for stress testing of cache. Test creates a lot of
cache traffic
Usage: ct

	TLB tests: from IP30/tlb.
tlb
---
The tlb test maps tlb enteries to main memory. 
Usage: tlb

utlb
-----
Tests the virtual memory capability of the machine by functionally
excercising the tlb look aside buffer by creating page faults
Usage: utlb

	HEART TESTS: from ../godzilla/heart
hr_regs
-------
Performs write/read/verify tests on heart registers
Usage: hr_regs

hr_rd
-----
A utility to read heart registers
Usage: hr_rd

hr_wr
-----
A utility to write heart registers
Usage: hr_wr

hr_piuacc
---------
PIU (Processor Interface Units) access errors are created by 
reading/writing disallowed bits
Usage: hr_piuacc

hr_intr
-------
Generates an interrupt and verifies that it occured
Usage: hr_intr

hr_misc
-------
Performs write/read/verify tests on heart misc registers
Usage: hr_misc

hr_piowcr
---------
Performs widget accesses in PIO (programmed i/o) mode
Usage: hr_piowcr

	XBOW TESTS: from ../godzilla/xbow
x_regs
------
Performs write/read/verify tests
Usage: x_regs 

x_reset
-------
Issues a status reset command
Usage: x_reset

x_acc
-----
Performs register tests on access registers
Usage: x_acc

hx_badllp
---------
Runs bad LLP (Link Level Protocol) tests between Heart and Xbow
Usage: hx_badllp

x_rd
----
Register read utility
Usage: x_rd

x_wr
----
Register write utility
Usage: x_wr

	BRIDGE TEST: from ../godzilla/bridge
br_regs
------
Performs write/read/verify tests
Usage: br_regs

br_ram
------
Tests built in bridge memory. Performs write/read/verify tests
Usage: br_ram

br_intr
-------
Genereates and interupt and verifies it occured
Usage: br_intr

br_rd
-----
Utility to perform bridge reads
Usage: br_rd

br_wr
-----
Utility to perform bridge writes
Usage: br_wr

br_err
-------
Create errors by writing to invalid addresses
Usage: br_err

	HEART/BRIDGE TEST: from ../godzilla/heart_bridge
hb_status
---------
Display status information about heart bridge
Usage: hb_status

hb_badllp
---------
Heart bridge bad LLP test
Usage: hb_badllp

hb_savreg
---------
Save registers (heart and bridge)
Usage: hb_savreg

hb_rstreg
---------
Restore registers (heart and bridge)
Usage: hb_rstreg

hb_flow
---------
Pipe head flow of control heart/bridge
Usage: hb_flow

hb_chkout
---------
Test some heart bridge registers have the right values
Usage: hb_chkout

hb_reset
---------
Issues a reset command
Usage: hb_reset

	HEART/XBOW/BRIDGE TEST: from ../godzilla/h_x_b
hxb_savreg
---------
Save register command
Usage: hxb_savreg

hxb_rstreg
---------
Restore registers
Usage: hxb_rstreg

hxb_chkout
---------
Test if registers have valid values
Usage: hxb_chkout

hxb_reset
---------
Issue reset command
Usage: hxb_reset

hxb_status
---------
Issue status command
Usage: hxb_status

	Duart Serial Port Diags
duart_regs
---------
Performs write/read/verify tests
Usage: duart_regs

pci_sio
---------
Performs external loopback test. Serial data is sent out of the
port. It works its way into the same port via the plug. Data is
verified for correctness.
Usage: pci_sio -p -b -t
OPTIONS
-p <Port Number> [0=A|1=B]
-b <Baud Rate> [6..458333]
-t <Text>
e.g pci_sio -p 1 -t abc -b 50; pci_sio -p 1 -t abc -b 2000; 
pci_sio -p 1 -t abc -b 384000
SPECIAL EQUIPMENT & TEST SETUP Requires a serial port plug to be connected to
the test port. If a dumb terminal is connected then the port should not be tested.

	Parallal Port Diags
pci_par
---------
Two FIFO tests are done. First the fifo is filled/verified. Secondly,
the the data in the fifo is checked.
Usage: pci_par

	Real Time Clock
rtc_regs
---------
Register read write tests. Tests data and address paths.
CAVEAT This test is for debugging only. It should not be run in any IDE on the 
floor. Reboot machine after test.
Usage: rtc_regs

pci_rtc
---------
Several sub tests are run
1 Verify that clock is ticking (RTC Timer Test)
2 Write/Read/Verify nvram test (RTC ram test)
3 Auxillary battery voltage check (RTC Battery Test). Checks the rtc battery
voltage
Usage: pci_rtc

	Voltage Change Utility
chg_volt
---------
This test is provided to change supply voltages and conduct tests.
Usage: chg_volt

	FPU tests
fpu
---------
Floating point arithmatic tests
Usage: fpu

lpackd
---------
The linpac floating point benchmark algorithm is used
Usage: lpackd

	IOC3 Tests (for IP30 bringup)
ioc3_regs
---------
Performs write/read/verify tests
Usage: ioc3_regs

ioc3_sram
---------
Performs write/read/verify tests
Usage: ioc3_sram

	SCSI test
scsi_test
---------
Tests scsi mailbox's by sending messages. Also performs scsi-dma, and a self test.
The default is to test controllers 0,1. The argument specifies the controller to
test.
Usage: scsi_test [0|1]


	RAD Audio Chip Diags
rad_regs
---------
Performs write/read/verify tests
Usage: rad_regs

rad_dma
---------
Perform status dma from chip to memory
Usage: rad_dma

rad_ram
---------
Performs write/read/verify tests on dma registers
Usage: rad_ram

nic_check
---------
Reads all nic's and prints the nic contents
Usage: nic_check
