# rule input file right now contains the rules corresponding
# to md,pi,ni

section: PI

register: PI_ERR_INT_PEND
condition: OR 23 17 15 13 11 9
actions:
	CPU0,90%
	HUB,80%
	end



register: PI_ERR_INT_PEND
condition: OR 22 16 14 12 10 8
actions:
	CPU1,90%
	HUB,80%
	end

    

register: PI_ERR_INT_PEND
condition: OR 4 5
actions:
	HUB,70%
	end


register: PI_ERR_INT_PEND
condition: OR 6 7
actions:
	MEM,70%
	end

section: MD

register: MD_MISC_ERR
condition: OR 9 7 5 3
actions:
	HUB,70%
	end

section: NI

#register: NI_PORT_ERR
#condition: OR 37 35 34 33 
#actions:
#	end


register: NI_PORT_ERR
condition: OR 36
actions:
	HUB,90%
	PI,60%
	MD,60%
	II,60%
	end

section: XBOW

register: XBOW_WIDGET_0_STATUS
condition: OR 5
actions:
	SOFTWARE,90%
	end

section: BRIDGE

# if any of 
#	28 BAD_XRESP_PACKET
#	27 BAD_XREQ_PACKET
# are set

register: BRIDGE_INT_STATUS
condition: OR 28 27
actions:
	BRIDGE_LINK,80%
	XBOW,60%
	end


# if any of 
#	24 INVALID_ADDRESS
#	23 UNSSUPORTED_XOP
#	22 XREQ_FIFO_OFLOW
# are set

register: BRIDGE_INT_STATUS
condition: OR 24 23 22
actions:
	SOFTWARE,90%
	end


# if any of: 
#	LLP_REC_SNERROR
#	LLP_REC_CBERROR
#	LLP_RCTY
#	LLP_TCTY
# are set.

register: BRIDGE_INT_STATUS
condition: OR 21 20 19 17
actions:
	BRIDGE_LINK,70%
	end

# if any of:
#	11 PCI_MASTER_TOUT
#	10 PCI_RETRY_CNT
# are set.

register: BRIDGE_INT_STATUS
condition: OR 11 10
actions:
	BRIDGE_PCI_MASTER,80%
	end

# if XREAD_REQ_TOUT is set

register: BRIDGE_INT_STATUS
condition: OR 9
actions:
	SOFTWARE,90%
	end


