IRIX64 k2rack 6.5-mfl-80-SN0 6.5.2m 11050508 IP27 4 300 MHZ IP27 Processors CPU: MIPS R12000 Processor Chip Revision: 2.1 FPU: MIPS R10010 Floating Point Chip Revision: 0.0 Main memory size: 1920 Mbytes Instruction cache size: 32 Kbytes Data cache size: 32 Kbytes Secondary unified instruction/data cache size: 8 Mbytes Secondary unified instruction/data cache size: 8 Mbytes Secondary unified instruction/data cache size: 8 Mbytes Secondary unified instruction/data cache size: 4 Mbytes /tmp/ecadmin_6.5.3 /tmp/ecstats_6.5.3 === FP alone === 3118034 FP ops per sec 1202391122.00 [ 0] Cycles 2.90 [21] Graduated floating point instructions 3117908 FP ops per sec 1202375113.80 [ 0] Cycles 1.60 [21] Graduated floating point instructions 3116780 FP ops per sec 1202375581.40 [ 0] Cycles 1.10 [21] Graduated floating point instructions === 1 D-cache miss alone === 2297265 1 D-cache miss per sec 35372.80 [25] Primary data cache misses 2296998 1 D-cache miss per sec 32471.00 [25] Primary data cache misses 2297373 1 D-cache miss per sec 31663.70 [25] Primary data cache misses === 2 D-cache miss alone === 1737260 2 D-cache miss per sec 68.50 [26] Secondary data cache misses 1981037 2 D-cache miss per sec 56.40 [26] Secondary data cache misses 2089144 2 D-cache miss per sec 63.90 [26] Secondary data cache misses === all together === 1344992 FP ops per sec 1344992 1 D-cache miss per sec 1344992 2 D-cache miss per sec 1201886543.80 [ 0] Cycles 1.80* [21] Graduated floating point instructions 46563.60* [25] Primary data cache misses 149.40* [26] Secondary data cache misses 1342977 FP ops per sec 1342976 1 D-cache miss per sec 1342976 2 D-cache miss per sec 1201938199.90 [ 0] Cycles 1.80* [21] Graduated floating point instructions 38015.70* [25] Primary data cache misses 128.10* [26] Secondary data cache misses 1338628 FP ops per sec 1338628 1 D-cache miss per sec 1338628 2 D-cache miss per sec 1201842939.50 [ 0] Cycles 1.80* [21] Graduated floating point instructions 36261.60* [25] Primary data cache misses 103.50* [26] Secondary data cache misses