#
# IP27 multi-processor product definitions.
#
# SN0 R10K with KONA
#
# Fundamental constants of the build tree (distinct from source tree).
# They may be different for each product.  Therefore if several products are
# built from one source tree, that source tree should contain a commondefs
# for each product.
#
SYSTEM	= SVR4
CPUBOARD= IP27
COMPLEX = MP
CPUARCH = R10000
PRODDEFS=-DSN0
GFXBOARD= KONA
SUBGR   = IP27
KMODEOPT = -DDISCONTIG_PHYSMEM -DNUMA_BASE -DNUMA_PM \
	-DNUMA_TBORROW -DNUMA_MIGRATION -DNUMA_MIGR_CONTROL \
	-DNUMA_REPLICATION -DNUMA_REPL_CONTROL -DNUMA_SCHED \
	-DPTE_64BIT -DLARGE_CPU_COUNT -DHUB1_WAR \
	-DHUB1_II_TIMEOUT_WAR -DHUB1_INTR_WAR \
	-DBRIDGE_ERROR_INTR_WAR -DIP27_NIC_WAR -DHUB_POQ_PIO_WAR \
	-DMAPPED_KERNEL -DIOC3_INTR_WAR \
	-DHUB_ERR_STS_WAR -DHUB_MIGR_WAR \
	-DSN0_INTR_BROKEN -DFRU -DFORCE_ERRORS -DT5_WB_SURPRISE_WAR \
	-DREV1_BRIDGE_SUPPORTED -DMIDPLANE_NIC_WAR -DFAKE_ROUTER_SLOT_WAR

SUBPRODUCT=H1
LARGE_CPU_COUNT=1
COMPILATION_MODEL=64
IOC3_PIO_MODE=0
include $(RELEASEDEFS)
#
# Workaround definitions
#
#	-DHUB1_WAR - Change register definitions for HUB1.  This will
#		 	be removed when we switch to Hub 2.
#	-DBRIDGE1_TIMEOUT_WAR - Adjust the arbitartion time to keep the
#			1.0 bridge chip from corrupting data.  Also disable
#			certain error interrupts.
#	-DHUB1_II_TIMEOUT_WAR - This is a nasty one.  Periodically stop
#			_all_ I/O and reset the hub timeout value.  See
#			hub_dmatimeout_kick().
#	-DHUB1_INTR_WAR - Send interrupts to the junk bus interrupt controller.
#			The II has a bug that makes non-cache-aligned writes
#			from the II corrupt DMA data.
#	-DBRIDGE_ERROR_INTR_WAR - We seem to get erroneous error interrupts
#			from the bridge.  Disable BRIDGE_IMR_PCI_MST_TIMEOUT,
#			BRIDGE_ISR_RESP_XTLK_ERR, and BRIDGE_ISR_LLP_TX_RETRY
#	-DIP27_NIC_WAR - The numer in a can doesn't work on early IP27 boards.
#	-DHUB_POQ_PIO_WAR - 64-bit writes to HUB PI registers can cause
#			the PI to become confused and issue a bogus message.
#			do 32-bit writes knowing that T5 will provide all
#			of the bits and Hub will ignore the byte enables.
#
#	-sw, 5/28/96
#
# IOC3_INTR_WAR: with the junk interrupt it is required that an interrupt
#     handler ensure that its interrupt line is deasserted before returning.
#     This is problematic in the case of the IOC3 because the status of the
#     interrupt line cannot be read atomically from the hardware, and 
#     there are no common locks between the various IOC3 sub-devices. The
#     upshot is occasionally we return from the handler without deasserting
#     the interrupt line, and all subsequent interrupts are lost. The
#     simple workaround to this is to poll for the interrupt once per 
#     second.
# -tcl
# HUB_MIGR_WAR: The hub logic to generate a migration interrupt based
#               on the difference of home and remote reference counters
#               is not right.  Probably it will be fixed in rev2.1.  
#               The workaround provides an alternative by not using 
#               the migration difference threshold register.
#
# HUB_ERR_STS_WAR: If any write errors happen when the hub error
#	registers  are clear, we start losing WRB and subsequently
#	hang the CPU. This WAR ensures that the error status registers
#	have a RRB error in them.
#
# T5_WB_SURPRISE_WAR: The T5 incorrectly acknowledges a cache line 
#	invalidate under some circumstances. It later proceeds to
#	writeback the cache line, resulting in a protocol error. This
#	will be fixed in T5 2.6, but in the meanwhile this WAR
#	attempts to detect if we ran into this problem.
#	Later, we should be able to kill user processes refrerencing
#	the page and let the system not panic.
#