'\"macro stdmacro
.TH CACHECTL 2
.SH NAME
cachectl \- mark pages cacheable or uncacheable
.SH SYNOPSIS
.B "#include <sys/cachectl.h>"
.sp
.B "int cachectl (void \(**addr, int nbytes, int op);"
.SH DESCRIPTION
The
.I cachectl
system call allows a process to make ranges of its
address space cacheable or uncacheable.
Initially,
a process's entire address space is cacheable.
.PP
The
.I op
parameter may be one of:
.TP 17
.B CACHEABLE
Make the indicated pages cacheable
.TP
.B UNCACHEABLE
Make the indicated pages uncacheable
.PP
The CACHEABLE and UNCACHEABLE \f2op\f1's affect the address range indicated
by \f2addr\f1 and \f2nbytes\f1.
.I addr
must be page aligned and nbytes must be a multiple of the page size.
.PP
Changing a page from UNCACHEABLE state to CACHEABLE state will cause both the
instruction and data caches to be flushed if necessary to avoid stale cache
information.
.PP
On Power Indigo2, Indigo2 10000 and Power Challenge M systems,
user programs are not allowed uncached access to main memory,
so requesting this will fail with
EINVAL.
.PP
On systems with hardware coherent caches,
.I cachectl
will complete successfully, but not actually allow memory to be accessed
uncached.
.SH "RETURN VALUE"
.I cachectl
returns 0 when no errors are detected.
If errors are detected,
.I cachectl
returns \-1 with the error cause indicated in \f2errno\f1.
.SH ERRORS
.TP 17
.SM [EINVAL]
The
.I op
parameter is not one of CACHEABLE or UNCACHEABLE, or is UNCACHEABLE on
a Power Indigo2, Indigo2 10000 or Power Challenge M.
.TP
.SM [EINVAL]
The
.I addr
parameter is not page aligned,
or
.I nbytes
is not a multiple of the page size.
.TP
.SM [EFAULT]
Some or all of the address range
.I addr
to (\f2addr\f1+\f2nbytes\f1-1) is not accessible.
.SH "SEE ALSO"
cacheflush(2)