# This is an ide startup file.
#
report=4 # set verbose, but not debug
$stoponerr=1
hinv -v

echo ""
echo "Ide included scripts are"
echo "	memory		ip32"

# memory and cache test
memory {
$tmp=memtest;
if ($tmp) {
        wait;
}
$tmp=memtest2 0;
if ($tmp) {
	wait;
}
$tmp=memtest2 1;
if ($tmp) {
	wait;
}
$tmp=memtest2 2;
if ($tmp) {
	wait;
}
$tmp=memtest2 3;
if ($tmp) {
	wait;
}
$tmp=memtest2 5;
if ($tmp) {
	wait;
}
$tmp=memtest2 8;
if ($tmp) {
	wait;
}
$tmp=memtest2 9;
if ($tmp) {
	wait;
}
$tmp=memtest2 10;
if ($tmp) {
	wait;
}
$tmp=memtest2 12;
if ($tmp) {
	wait;
}
$tmp=memtest2 13;
if ($tmp) {
	wait;
}
#$tmp=ldram;
#if ($tmp) {
#        wait;
#}
#$tmp=ldram -p;
#if ($tmp) {
#        wait;
#}
#$tmp=dram;
#if ($tmp) {
#        wait;
#}
#$tmp=dram -p;
#if ($tmp) {
#        wait;
#}
$tmp=dcache1;
if ($tmp) {
        wait;
}
$tmp=icache1;
if ($tmp) {
        wait;
}
$tmp=icache2;
if ($tmp) {
        wait;
}
#$tmp=scache1;
#if ($tmp) {
#        wait;
#}
}

ip32 {

# TLB test. Verify different tlb functions.
if ((tlb) && $stoponerr)
        wait;

# UTLB miss exception test. Verify the exception generating capability of the
# mips chip during a utlb miss.
#if ((utlb) && $stoponerr)
#        wait;

# UST test. Verify workings of the UST and interrupt capabilities
if ((cntrs) && $stoponerr)
        wait;

# Test floating point unit
$fpufailed=0;
if ((fpu) && $stoponerr)
        wait;

if ((memtest) && $stoponerr)
        wait;
$tmp=dcache1;
if ($tmp) {
        wait;
}
$tmp=icache1;
if ($tmp) {
        wait;
}
$tmp=icache2;
if ($tmp) {
        wait;
}
$tmp=scache2;
if ($tmp) {
        wait;
}
$tmp=scache6;
if ($tmp) {
        wait;
}
$tmp=i2c_reg;
if ($tmp) {
        wait;
}
$tmp=plploop;
if ($tmp) {
	wait;
}
$tmp=serialloop;
if ($tmp) {
	wait;
}
# END OF IP32 SCRIPT
}