#
# IP27 multi-processor product definitions.
#
# SN0 R10K with KONA
#
# Fundamental constants of the build tree (distinct from source tree).
# They may be different for each product.  Therefore if several products are
# built from one source tree, that source tree should contain a commondefs
# for each product.
#
SYSTEM	= SVR4
CPUBOARD= IP27
COMPLEX = MP
CPUARCH = R10000
PRODDEFS=-DSN0
GFXBOARD= KONA
SUBGR   = IP27
KMODEOPT = -DDISCONTIG_PHYSMEM -DNUMA_BASE -DNUMA_PM \
	-DNUMA_TBORROW -DNUMA_MIGR_CONTROL \
	-DNUMA_REPLICATION -DNUMA_REPL_CONTROL -DNUMA_SCHED \
	-DLARGE_CPU_COUNT -DHUB2_NACK_WAR \
	-DBRIDGE_ERROR_INTR_WAR -DMAPPED_KERNEL -DBHV_SYNCH \
	-DHUB_ERR_STS_WAR -DHUB_MIGR_WAR \
	-DFRU -DSN \
	-DSN0_USE_BTE -DBTE_BZERO_WAR -DREV1_BRIDGE_SUPPORTED \
	-DHUB_II_IFDR_WAR -DRTINT_WAR -DPCOUNT_WAR -DBRIDGE_B_DATACORR_WAR 
SUBPRODUCT=CELLARRAY
LARGE_CPU_COUNT=1
COMPILATION_MODEL=64
IOC3_PIO_MODE=0
CELL=1
CELL_ARRAY=1
include $(RELEASEDEFS)
#
# Workaround definitions
#
#	-DBRIDGE1_TIMEOUT_WAR - Adjust the arbitartion time to keep the
#			1.0 bridge chip from corrupting data.  Also disable
#			certain error interrupts.
#	-DBRIDGE_ERROR_INTR_WAR - We seem to get erroneous error interrupts
#			from the bridge.  Disable BRIDGE_IMR_PCI_MST_TIMEOUT,
#			BRIDGE_ISR_RESP_XTLK_ERR, and BRIDGE_ISR_LLP_TX_RETRY
#	-DIP27_NIC_WAR - The numer in a can doesn't work on early IP27 boards.
#
#	-sw, 5/28/96
#
# HUB_MIGR_WAR: The hub logic to generate a migration interrupt based
#               on the difference of home and remote reference counters
#               is not right.  Probably it will be fixed in rev2.1.  
#               The workaround provides an alternative by not using 
#               the migration difference threshold register.
#
# HUB_ERR_STS_WAR: If any write errors happen when the hub error
#	registers  are clear, we start losing WRB and subsequently
#	hang the CPU. This WAR ensures that the error status registers
#	have a RRB error in them.
#
# T5_WB_SURPRISE_WAR: The T5 incorrectly acknowledges a cache line 
#	invalidate under some circumstances. It later proceeds to
#	writeback the cache line, resulting in a protocol error. This
#	will be fixed in T5 2.6, but in the meanwhile this WAR
#	attempts to detect if we ran into this problem.
#	Later, we should be able to kill user processes refrerencing
#	the page and let the system not panic.
#	
# HUB_II_IFDR_WAR:  The hub II IFDR fifo count gets incremented once
#		    in  a while and this can cause hangs and
#		    corruption if not caught and fixed.
#
#
#
# RTINT_WAR: the realtime interrupt on IOC3 is tied to the same interrupt as serial,
#            parallel and kbd/mouse, making it impossible to isolate the interrupt.
#            This makes it useless as a realtime interrupt. As a workaround we disable
#            interrupts to these other devices and poll them instead when RT interrupts
#            are in use.
#
#
# PCOUNT_WAR: Under certain circumstances all the ICRBs can end up in DEX
#       mode. This will cause a system hang. This code will allow us to
#       spot the problem in the FRU Analyzer.
#