455 lines
15 KiB
C
455 lines
15 KiB
C
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/** @defgroup timer_file Timer peripheral API
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* @brief SWM050 Timer API.
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* @ingroup peripheral_apis
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* LGPL License Terms @ref lgpl_license
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* @author @htmlonly © @endhtmlonly 2020
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* Caleb Szalacinski <contact@skiboy.net>
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2020 Caleb Szalacinski <contact@skiboy.net>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#include <libopencm3/swm050/timer.h>
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#include <libopencm3/swm050/sysctl.h>
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#include <libopencm3/swm050/syscon.h>
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/**
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* Internal function for timer setup.
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* @param timer Select timer @ref timer_select
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* @param timer_int_en Passed to @ref timer_int_enable()
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* @param op_mode Passed to @ref timer_operation_mode()
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* @param edge_mode Passed to @ref timer_edge_mode()
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* @param loop_mode Passed to @ref timer_loop_mode()
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* @param clk_src Passed to @ref timer_clock_source()
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* @param output_mode Passed to @ref timer_output_mode()
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* @param output_level Passed to @ref timer_output_level()
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*/
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static void timer_setup_internal(uint32_t timer,
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bool timer_int_en,
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enum timer_operation_modes op_mode,
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enum timer_edge_modes edge_mode,
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enum timer_loop_modes loop_mode,
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enum timer_clk_src clk_src,
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enum timer_output_modes output_mode,
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enum timer_level output_level)
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{
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timer_enable(timer, false);
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/* Conserve power by shutting off the unneeded clock */
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timer_clock_enable(timer, (clk_src == TIMER_CLK_INTERNAL));
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timer_loop_mode(timer, loop_mode);
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timer_output_mode(timer, output_mode);
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timer_output_level(timer, output_level);
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timer_clock_source(timer, clk_src);
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timer_operation_mode(timer, op_mode);
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timer_edge_mode(timer, edge_mode);
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timer_int_enable(timer, timer_int_en);
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timer_int_mask(timer, TIMER_UNMASKED);
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}
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/**
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* Setup the timer in counter mode.
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* @note Call @ref timer_enable() when you are ready to start the timer.
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* @note Be sure to set the alternate functions of the timer pins
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* with @ref syscon_sel_af() and disable SWD on those pins
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* with @ref syscon_sel_swd() as needed.
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* @note If interrupts are enabled here, the interrupt should also be enabled
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* using the NVIC before enabling the timer.
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* @param timer Select timer @ref timer_select
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* @param timer_int_en Passed to @ref timer_int_enable()
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* @param edge_mode Passed to @ref timer_edge_mode()
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* @param loop_mode Passed to @ref timer_loop_mode()
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* @param clk_src Passed to @ref timer_clock_source()
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* @param output_mode Passed to @ref timer_output_mode()
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* @param output_level Passed to @ref timer_output_level()
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* @param target Passed to @ref timer_counter_target_value()
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*/
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void timer_counter_setup(uint32_t timer,
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bool timer_int_en,
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enum timer_edge_modes edge_mode,
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enum timer_loop_modes loop_mode,
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enum timer_clk_src clk_src,
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enum timer_output_modes output_mode,
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enum timer_level output_level,
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uint32_t target)
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{
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timer_setup_internal(timer, timer_int_en, TIMER_MODE_COUNTER, edge_mode,
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loop_mode, clk_src, output_mode, output_level);
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timer_counter_target_value(timer, target);
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}
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/**
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* Setup the timer in PWM mode.
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* @note Call @ref timer_enable() when you are ready to start the timer.
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* @note Be sure to set the alternate functions of the timer pins
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* with @ref syscon_sel_af() and disable SWD on those pins
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* with @ref syscon_sel_swd() as needed.
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* @note If interrupts are enabled here, the interrupt should also be enabled
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* using the NVIC before enabling the timer.
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* @param timer Select timer @ref timer_select
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* @param timer_int_en Passed to @ref timer_int_enable()
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* @param edge_mode Passed to @ref timer_edge_mode()
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* @param clk_src Passed to @ref timer_clock_source()
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* @param output_level Passed to @ref timer_output_level()
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* @param period0 Passed to @ref timer_pwm_target_value()
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* @param period1 Passed to @ref timer_pwm_target_value()
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*/
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void timer_pwm_setup(uint32_t timer,
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bool timer_int_en,
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enum timer_edge_modes edge_mode,
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enum timer_clk_src clk_src,
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enum timer_level output_level,
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uint16_t period0,
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uint16_t period1)
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{
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timer_setup_internal(timer, timer_int_en, TIMER_MODE_PWM, edge_mode,
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TIMER_LOOP_MODE, clk_src, TIMER_OUTPUT_NONE,
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output_level);
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timer_pwm_target_value(timer, period0, period1);
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}
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/**
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* Setup the timer in pulse capture mode.
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* @note Call @ref timer_enable() when you are ready to start the timer.
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* @note Be sure to set the alternate functions of the timer pins
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* with @ref syscon_sel_af() and disable SWD on those pins
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* with @ref syscon_sel_swd() as needed.
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* @note If interrupts are enabled here, the interrupt should also be enabled
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* using the NVIC before enabling the timer.
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* @param timer Select timer @ref timer_select
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* @param timer_int_en Passed to @ref timer_int_enable()
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* @param edge_mode Passed to @ref timer_edge_mode()
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* @param loop_mode Passed to @ref timer_loop_mode()
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*/
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void timer_pulse_capture_setup(uint32_t timer,
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bool timer_int_en,
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enum timer_edge_modes edge_mode,
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enum timer_loop_modes loop_mode)
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{
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timer_setup_internal(timer, timer_int_en, TIMER_MODE_PULSE_CAPTURE,
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edge_mode, loop_mode, TIMER_CLK_INTERNAL,
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TIMER_OUTPUT_NONE, TIMER_LEVEL_LOW);
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}
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/**
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* Setup the timer in duty cycle capture mode.
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* @note Call @ref timer_enable() when you are ready to start the timer.
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* @note Be sure to set the alternate functions of the timer pins
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* with @ref syscon_sel_af() and disable SWD on those pins
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* with @ref syscon_sel_swd() as needed.
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* @note If interrupts are enabled here, the interrupt should also be enabled
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* using the NVIC before enabling the timer.
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* @param timer Select timer @ref timer_select
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* @param timer_int_en Passed to @ref timer_int_enable()
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* @param edge_mode Passed to @ref timer_edge_mode()
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* @param loop_mode Passed to @ref timer_loop_mode()
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*/
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void timer_duty_cycle_capture_setup(uint32_t timer,
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bool timer_int_en,
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enum timer_edge_modes edge_mode,
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enum timer_loop_modes loop_mode)
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{
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timer_setup_internal(timer, timer_int_en, TIMER_MODE_DUTY_CYCLE_CAPTURE,
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edge_mode, loop_mode, TIMER_CLK_INTERNAL,
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TIMER_OUTPUT_NONE, TIMER_LEVEL_LOW);
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}
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/**
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* Set the timer clock divider, based off of the 18MHz oscillator
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* @param div Timer clock divider. Only the 6 least-significant bits are used,
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* Takes values from 0 to 63 (in reality the possible values are the even
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* numbers from 2 to 62, as well as the number 1). Anything after the 6
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* least-significant bits are stripped off of the value. If the value is 0,
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* it will be treated as a 1. All odd values other than 1 are rounded down
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* to the closest even value, due to the fact that all odd values are
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* treated by the register as a 1, which would likely be unexpected. A
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* value of 0 would also normally be treated as a 2, which would also be
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* unexpected behavior.
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*/
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void timer_clock_div(uint8_t div)
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{
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/* If the value is 0 or 1, make it odd, meaning no divide. */
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/* Otherwise, drop div to the closest even value. */
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div = (div <= 1) ? 1 : (div & ~0x1);
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SYSCTL_SYS_CFG_0 = (~TIMER_DIV_MASK & SYSCTL_SYS_CFG_0) | (div << 16);
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}
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/**
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* Enables or disables the timer.
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* @param timer Select timer @ref timer_select
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* @param en Enable or disable the timer
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*/
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void timer_enable(uint32_t timer, bool en)
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{
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if (en) {
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TIMER_CTRL(timer) |= TIMER_CTRL_EN;
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} else {
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TIMER_CTRL(timer) &= ~TIMER_CTRL_EN;
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}
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}
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/**
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* Enables or disables the timer's internal clock.
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* @param timer Select timer @ref timer_select
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* @param en Enable or disable the internal clock
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*/
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void timer_clock_enable(uint32_t timer, bool en)
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{
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if (timer == TIMER_SE1) {
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if (en) {
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SYSCTL_SYS_CFG_1 |= SYSCTL_SYS_CFG_1_TIMERSE1;
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} else {
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SYSCTL_SYS_CFG_1 &= ~SYSCTL_SYS_CFG_1_TIMERSE1;
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}
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} else {
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if (en) {
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SYSCTL_SYS_CFG_1 |= SYSCTL_SYS_CFG_1_TIMERSE0;
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} else {
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SYSCTL_SYS_CFG_1 &= ~SYSCTL_SYS_CFG_1_TIMERSE0;
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}
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}
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}
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/**
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* Selects the mode of operation.
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* @param timer Select timer @ref timer_select
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* @param mode The mode of operation @ref timer_operation_modes
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*/
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void timer_operation_mode(uint32_t timer, enum timer_operation_modes mode)
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{
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uint32_t reg = TIMER_CTRL(timer) & ~(TIMER_CTRL_OUTMOD_MASK << TIMER_CTRL_OUTMOD_SHIFT);
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TIMER_CTRL(timer) = reg | (mode << TIMER_CTRL_OUTMOD_SHIFT);
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}
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/**
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* Selects the output mode.
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* Only used in counter mode.
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* When done counting, the pin can be set to no output,
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* to invert the current pin level, to set the pin high,
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* or to set the pin low.
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* @note Be sure to set the alternate functions of the timer pins
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* with @ref syscon_sel_af() and disable SWD on those pins
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* with @ref syscon_sel_swd() as needed.
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* @param timer Select timer @ref timer_select
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* @param mode The output mode @ref timer_output_modes
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*/
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void timer_output_mode(uint32_t timer, enum timer_output_modes mode)
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{
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uint32_t reg = TIMER_CTRL(timer) & ~(TIMER_CTRL_WMOD_MASK << TIMER_CTRL_WMOD_SHIFT);
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TIMER_CTRL(timer) = reg | (mode << TIMER_CTRL_WMOD_SHIFT);
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}
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/**
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* Selects the initial output level.
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* Only used in counter and PWM modes.
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* @param timer Select timer @ref timer_select
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* @param level The initial output level @ref timer_level
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*/
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void timer_output_level(uint32_t timer, enum timer_level level)
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{
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TIMER_OUTPVAL(timer) = level;
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}
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/**
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* Selects the edge mode.
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* @param timer Select timer @ref timer_select
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* @param mode The edge mode @ref timer_edge_modes
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*/
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void timer_edge_mode(uint32_t timer, enum timer_edge_modes mode)
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{
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if (mode) {
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TIMER_CTRL(timer) |= TIMER_CTRL_TMOD;
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} else {
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TIMER_CTRL(timer) &= ~TIMER_CTRL_TMOD;
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}
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}
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/**
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* Selects the loop mode.
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* This has no use in PWM mode.
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* In loop mode with counter mode, the counter will constantly loop.
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* In loop mode with the capture modes, the values will be captured
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* again and again. In single mode, these operations happen only once.
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* @param timer Select timer @ref timer_select
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* @param mode The loop mode @ref timer_loop_modes
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*/
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void timer_loop_mode(uint32_t timer, enum timer_loop_modes mode)
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{
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if (mode) {
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TIMER_CTRL(timer) |= TIMER_CTRL_LMOD;
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} else {
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TIMER_CTRL(timer) &= ~TIMER_CTRL_LMOD;
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}
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}
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/**
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* Selects the clock source for the timer.
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* @note Be sure to set the alternate functions of the timer pins
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* with @ref syscon_sel_af() and disable SWD on those pins
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* with @ref syscon_sel_swd() as needed.
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* @note If not using the internal clock, you can disable it
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* with @ref timer_clock_enable() for power savings.
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* @param timer Select timer @ref timer_select
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* @param src Select the internal or external clock source @ref timer_clk_src
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*/
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void timer_clock_source(uint32_t timer, enum timer_clk_src src)
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{
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if (src) {
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TIMER_CTRL(timer) |= TIMER_CTRL_OSCMOD;
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} else {
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TIMER_CTRL(timer) &= ~TIMER_CTRL_OSCMOD;
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}
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}
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/**
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* Sets the target values for counter mode.
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* @param timer Select timer @ref timer_select
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* @param target The value to count up to
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*/
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void timer_counter_target_value(uint32_t timer, uint32_t target)
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{
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TIMER_TARVAL(timer) = target;
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}
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/**
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* Sets the target values for PWM mode.
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* @param timer Select timer @ref timer_select
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* @param period0 length of period 0 in clock cycles. Whether
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* it is high or low is set in @ref timer_output_level()
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* @param period1 length of period 1
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*/
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void timer_pwm_target_value(uint32_t timer, uint16_t period0, uint16_t period1)
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{
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timer_counter_target_value(timer, (period1 << 16) | period0);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* Enable or disable the interrupt.
|
||
|
|
* In counter mode, when the count has been completed,
|
||
|
|
* an interrupt is generated.
|
||
|
|
* In PWM mode, on a level change, an interupt is generated.
|
||
|
|
* In either capture mode, when a capture is complete,
|
||
|
|
* an interrupt is generated.
|
||
|
|
* @note If interrupts are enabled here, the interrupt should also be enabled
|
||
|
|
* using the NVIC before enabling the timer.
|
||
|
|
* @param timer Select timer @ref timer_select
|
||
|
|
* @param en Enable or disable the interrupt
|
||
|
|
*/
|
||
|
|
void timer_int_enable(uint32_t timer, bool en)
|
||
|
|
{
|
||
|
|
if (en) {
|
||
|
|
TIMER_INTCTL(timer) |= TIMER_INTCTL_INTEN;
|
||
|
|
} else {
|
||
|
|
TIMER_INTCTL(timer) &= ~TIMER_INTCTL_INTEN;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* Sets the interrupt mask.
|
||
|
|
* @param timer Select timer @ref timer_select
|
||
|
|
* @param masked Whether or not to mask the interrupt @ref timer_int_masked
|
||
|
|
*/
|
||
|
|
void timer_int_mask(uint32_t timer, enum timer_int_masked masked)
|
||
|
|
{
|
||
|
|
if (masked) {
|
||
|
|
TIMER_INTCTL(timer) &= ~TIMER_INTCTL_INTMSK;
|
||
|
|
} else {
|
||
|
|
TIMER_INTCTL(timer) |= TIMER_INTCTL_INTMSK;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* Gets the current counter value, and clears the interrupt/interrupt overflow.
|
||
|
|
* If in PWM mode, this is only used for clearing the interrupt.
|
||
|
|
* @param timer Select timer @ref timer_select
|
||
|
|
* @return The current counter value
|
||
|
|
*/
|
||
|
|
uint32_t timer_get_current_value(uint32_t timer)
|
||
|
|
{
|
||
|
|
return TIMER_CURVAL(timer);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* Gets the cycle width.
|
||
|
|
* Only used in duty cycle capture mode.
|
||
|
|
* @note See the datasheet for more concise diagrams.
|
||
|
|
* @param timer Select timer @ref timer_select
|
||
|
|
* @return The cycle width
|
||
|
|
*/
|
||
|
|
uint32_t timer_get_cycle_width(uint32_t timer)
|
||
|
|
{
|
||
|
|
return TIMER_CAPW(timer);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* Gets the pulse width in pulse capture mode,
|
||
|
|
* or gets the period width in duty cycle capture mode.
|
||
|
|
* @note See the datasheet for more concise diagrams.
|
||
|
|
* @param timer Select timer @ref timer_select
|
||
|
|
* @return The pulse width
|
||
|
|
*/
|
||
|
|
uint32_t timer_get_pulse_width(uint32_t timer)
|
||
|
|
{
|
||
|
|
return TIMER_CAPLH(timer);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* Gets the current output period in PWM mode.
|
||
|
|
* @param timer Select timer @ref timer_select
|
||
|
|
* @return The current output period @ref timer_pwm_period
|
||
|
|
*/
|
||
|
|
enum timer_pwm_period timer_get_pwm_period(uint32_t timer)
|
||
|
|
{
|
||
|
|
return TIMER_MOD2LF(timer) & 0x1;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* Gets the interrupt status after masking.
|
||
|
|
* @param timer Select timer @ref timer_select
|
||
|
|
* @return The interrupt status after masking
|
||
|
|
*/
|
||
|
|
bool timer_int_status(uint32_t timer)
|
||
|
|
{
|
||
|
|
return TIMER_INTMSKSTAT(timer) & 0x1;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* Gets the interrupt status before masking.
|
||
|
|
* @param timer Select timer @ref timer_select
|
||
|
|
* @return The interrupt status before masking
|
||
|
|
*/
|
||
|
|
bool timer_int_raw_status(uint32_t timer)
|
||
|
|
{
|
||
|
|
return TIMER_INTSTAT(timer) & 0x1;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* Gets the interrupt overflow status.
|
||
|
|
* Overflow will occur if the interrupt has not been cleared when a second
|
||
|
|
* interrupt happens.
|
||
|
|
* @param timer Select timer @ref timer_select
|
||
|
|
* @return The interrupt overflow status
|
||
|
|
*/
|
||
|
|
bool timer_int_overflow_status(uint32_t timer)
|
||
|
|
{
|
||
|
|
return TIMER_INTFLAG(timer) & 0x1;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**@}*/
|