Arti Zirk
054740c5de
subrepo: subdir: "libopencm3" merged: "88e91c9a7cce" upstream: origin: "https://github.com/libopencm3/libopencm3.git" branch: "master" commit: "88e91c9a7cce" git-subrepo: version: "0.4.3" origin: "???" commit: "???"
385 lines
11 KiB
C
385 lines
11 KiB
C
/** @defgroup ethernet_mac_stm32fxx7_file MAC STM32Fxx7
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*
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* @ingroup ETH
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*
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* @brief <b>Ethernet MAC STM32Fxx7 Drivers</b>
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*
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* @version 1.0.0
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* @author @htmlonly © @endhtmlonly 2013 Frantisek Burian <BuFran@seznam.cz>
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*
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* @date 1 September 2013
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*
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <string.h>
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#include <libopencm3/ethernet/mac.h>
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#include <libopencm3/ethernet/phy.h>
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#include <libopencm3/stm32/gpio.h>
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#include <libopencm3/cm3/nvic.h>
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/**@{*/
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uint32_t TxBD;
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uint32_t RxBD;
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/*---------------------------------------------------------------------------*/
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/** @brief Set MAC to the PHY
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*
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* @param[in] mac uint8_t* Desired MAC
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*/
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void eth_set_mac(const uint8_t *mac)
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{
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ETH_MACAHR(0) = ((uint32_t)mac[5] << 8) | (uint32_t)mac[4] |
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ETH_MACA0HR_MACA0H;
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ETH_MACALR(0) = ((uint32_t)mac[3] << 24) | ((uint32_t)mac[2] << 16) |
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((uint32_t)mac[1] << 8) | mac[0];
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Initialize buffers and descriptors.
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*
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* @param[in] buf uint8_t* Memory area for the descriptors and data buffers
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* @param[in] nTx uint32_t Count of transmit descriptors (equal to count of buffers)
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* @param[in] nRx uint32_t Count of receive descriptors (equal to count of buffers)
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* @param[in] cTx uint32_t Bytes in each transmit buffer, must be a
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* multiple of 4
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* @param[in] cRx uint32_t Bytes in each receive buffer, must be a
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* multiple of 4
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* @param[in] isext bool true if extended descriptors should be used
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*
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* Note, the space passed via buf pointer must be large enough to
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* hold all the buffers and one descriptor per buffer.
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*/
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void eth_desc_init(uint8_t *buf, uint32_t nTx, uint32_t nRx, uint32_t cTx,
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uint32_t cRx, bool isext)
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{
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uint32_t bd = (uint32_t)buf;
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uint32_t sz = isext ? ETH_DES_EXT_SIZE : ETH_DES_STD_SIZE;
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memset(buf, 0, nTx * (cTx + sz) + nRx * (cRx + sz));
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/* enable / disable extended frames */
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if (isext) {
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ETH_DMABMR |= ETH_DMABMR_EDFE;
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} else {
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ETH_DMABMR &= ~ETH_DMABMR_EDFE;
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}
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TxBD = bd;
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while (--nTx > 0) {
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ETH_DES0(bd) = ETH_TDES0_TCH;
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ETH_DES2(bd) = bd + sz;
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ETH_DES3(bd) = bd + sz + cTx;
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bd = ETH_DES3(bd);
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}
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ETH_DES0(bd) = ETH_TDES0_TCH;
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ETH_DES2(bd) = bd + sz;
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ETH_DES3(bd) = TxBD;
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bd += sz + cTx;
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RxBD = bd;
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while (--nRx > 0) {
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ETH_DES0(bd) = ETH_RDES0_OWN;
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ETH_DES1(bd) = ETH_RDES1_RCH | cRx;
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ETH_DES2(bd) = bd + sz;
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ETH_DES3(bd) = bd + sz + cRx;
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bd = ETH_DES3(bd);
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}
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ETH_DES0(bd) = ETH_RDES0_OWN;
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ETH_DES1(bd) = ETH_RDES1_RCH | cRx;
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ETH_DES2(bd) = bd + sz;
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ETH_DES3(bd) = RxBD;
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ETH_DMARDLAR = (uint32_t) RxBD;
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ETH_DMATDLAR = (uint32_t) TxBD;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Transmit packet
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*
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* @param[in] ppkt uint8_t* Pointer to the beginning of the packet
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* @param[in] n uint32_t Size of the packet
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* @returns bool true, if success
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*/
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bool eth_tx(uint8_t *ppkt, uint32_t n)
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{
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if (ETH_DES0(TxBD) & ETH_TDES0_OWN) {
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return false;
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}
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memcpy((void *)ETH_DES2(TxBD), ppkt, n);
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ETH_DES1(TxBD) = n & ETH_TDES1_TBS1;
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ETH_DES0(TxBD) |= ETH_TDES0_LS | ETH_TDES0_FS | ETH_TDES0_OWN;
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TxBD = ETH_DES3(TxBD);
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if (ETH_DMASR & ETH_DMASR_TBUS) {
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ETH_DMASR = ETH_DMASR_TBUS;
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ETH_DMATPDR = 0;
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}
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return true;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Receive packet
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*
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* @param[inout] ppkt uint8_t* Pointer to the data buffer where to store data
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* @param[inout] len uint32_t* Pointer to the variable with the packet length
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* @param[in] maxlen uint32_t Maximum length of the packet
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* @returns bool true, if the buffer contains readed packet data
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*/
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bool eth_rx(uint8_t *ppkt, uint32_t *len, uint32_t maxlen)
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{
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bool fs = false;
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bool ls = false;
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bool overrun = false;
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uint32_t l = 0;
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while (!(ETH_DES0(RxBD) & ETH_RDES0_OWN) && !ls) {
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l = (ETH_DES0(RxBD) & ETH_RDES0_FL) >> ETH_RDES0_FL_SHIFT;
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fs |= ETH_DES0(RxBD) & ETH_RDES0_FS;
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ls |= ETH_DES0(RxBD) & ETH_RDES0_LS;
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/* frame buffer overrun ?*/
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overrun |= fs && (maxlen < l);
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if (fs && !overrun) {
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memcpy(ppkt, (void *)ETH_DES2(RxBD), l);
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ppkt += l;
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*len += l;
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maxlen -= l;
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}
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ETH_DES0(RxBD) = ETH_RDES0_OWN;
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RxBD = ETH_DES3(RxBD);
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}
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if (ETH_DMASR & ETH_DMASR_RBUS) {
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ETH_DMASR = ETH_DMASR_RBUS;
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ETH_DMARPDR = 0;
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}
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return fs && ls && !overrun;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Start the Ethernet DMA processing
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*/
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void eth_start(void)
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{
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ETH_MACCR |= ETH_MACCR_TE;
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ETH_DMAOMR |= ETH_DMAOMR_FTF;
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ETH_MACCR |= ETH_MACCR_RE;
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ETH_DMAOMR |= ETH_DMAOMR_ST;
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ETH_DMAOMR |= ETH_DMAOMR_SR;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Initialize ethernet
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*
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* This function will initialize ethernet, set up clocks, and initialize DMA.
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*
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* @param[in] phy phy id
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* @param[in] clock enum eth_clk Core clock speed
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*/
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void eth_init(uint8_t phy, enum eth_clk clock)
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{
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ETH_MACMIIAR = clock;
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phy_reset(phy);
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ETH_MACCR = ETH_MACCR_CSTF | ETH_MACCR_FES | ETH_MACCR_DM |
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ETH_MACCR_APCS | ETH_MACCR_RD;
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ETH_MACFFR = ETH_MACFFR_RA | ETH_MACFFR_PM;
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ETH_MACHTHR = 0; /* pass all frames */
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ETH_MACHTLR = 0;
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ETH_MACFCR = (0x100 << ETH_MACFCR_PT_SHIFT);
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ETH_MACVLANTR = 0;
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ETH_DMAOMR = ETH_DMAOMR_DTCEFD | ETH_DMAOMR_RSF | ETH_DMAOMR_DFRF |
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ETH_DMAOMR_TSF | ETH_DMAOMR_FEF | ETH_DMAOMR_OSF;
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ETH_DMABMR = ETH_DMABMR_AAB | ETH_DMABMR_FB |
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(32 << ETH_DMABMR_RDP_SHIFT) | (32 << ETH_DMABMR_PBL_SHIFT) |
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ETH_DMABMR_PM_2_1 | ETH_DMABMR_USP;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Enable the Ethernet IRQ
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*
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* @param[in] reason uint32_t Which irq will be enabled
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*/
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void eth_irq_enable(uint32_t reason)
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{
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ETH_DMAIER |= reason;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Disable the Ethernet IRQ
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*
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* @param[in] reason uint32_t Which irq will be disabled
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*/
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void eth_irq_disable(uint32_t reason)
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{
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ETH_DMAIER &= ~reason;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Check if IRQ is pending
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*
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* @param[in] reason uint32_t Which irq type has to be tested
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* @returns bool true, if IRQ is pending
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*/
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bool eth_irq_is_pending(uint32_t reason)
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{
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return (ETH_DMASR & reason) != 0;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Check if IRQ is pending, and acknowledge it
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*
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* @param[in] reason uint32_t Which irq type has to be tested
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* @returns bool true, if IRQ is pending
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*/
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bool eth_irq_ack_pending(uint32_t reason)
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{
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reason &= ETH_DMASR;
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ETH_DMASR = reason;
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return reason != 0;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Enable checksum offload feature
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*
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* This function will enable the Checksum offload feature for all of the
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* transmit descriptors. Note to use this feature, descriptors must be in
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* extended format.
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*/
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void eth_enable_checksum_offload(void)
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{
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uint32_t tab = TxBD;
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do {
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ETH_DES0(tab) |= ETH_TDES0_CIC_IPPLPH;
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tab = ETH_DES3(tab);
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}
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while (tab != TxBD);
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ETH_MACCR |= ETH_MACCR_IPCO;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Process pending SMI transaction and wait to be done.
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*/
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static void eth_smi_transact(void)
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{
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/* Begin transaction. */
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ETH_MACMIIAR |= ETH_MACMIIAR_MB;
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/* Wait for not busy. */
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while (ETH_MACMIIAR & ETH_MACMIIAR_MB);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Write 16-bit register to the PHY
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*
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* @param[in] phy uint8_t ID of the PHY (defaults to 1)
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* @param[in] reg uint8_t Register address
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* @param[in] data uint16_t Data to write
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*/
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void eth_smi_write(uint8_t phy, uint8_t reg, uint16_t data)
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{
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/* Write operation MW=1*/
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ETH_MACMIIAR = (ETH_MACMIIAR & ETH_MACMIIAR_CR) | /* save clocks */
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(phy << ETH_MACMIIAR_PA_SHIFT) |
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(reg << ETH_MACMIIAR_MR_SHIFT) |
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ETH_MACMIIAR_MW;
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ETH_MACMIIDR = data & ETH_MACMIIDR_MD;
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eth_smi_transact();
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Read the 16-bit register from the PHY
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*
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* @param[in] phy uint8_t ID of the PHY (defaults to 1)
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* @param[in] reg uint8_t Register address
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* @returns uint16_t Readed data
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*/
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uint16_t eth_smi_read(uint8_t phy, uint8_t reg)
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{
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/* Read operation MW=0*/
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ETH_MACMIIAR = (ETH_MACMIIAR & ETH_MACMIIAR_CR) | /* save clocks */
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(phy << ETH_MACMIIAR_PA_SHIFT) |
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(reg << ETH_MACMIIAR_MR_SHIFT);
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eth_smi_transact();
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return (uint16_t)(ETH_MACMIIDR & ETH_MACMIIDR_MD);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Process the bit-operation on PHY register
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*
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* @param[in] phy uint8_t ID of the PHY (defaults to 1)
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* @param[in] reg uint8_t Register address
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* @param[in] bits uint16_t Bits that have to be set (or'ed)
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* @param[in] mask uint16_t Bits that have to be clear (and'ed)
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*/
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void eth_smi_bit_op(uint8_t phy, uint8_t reg, uint16_t bits, uint16_t mask)
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{
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uint16_t val = eth_smi_read(phy, reg);
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eth_smi_write(phy, reg, (val & mask) | bits);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Clear bits in the register
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*
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* @param[in] phy uint8_t ID of the PHY (defaults to 1)
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* @param[in] reg uint8_t Register address
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* @param[in] clearbits uint16_t Bits that have to be cleared
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*/
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void eth_smi_bit_clear(uint8_t phy, uint8_t reg, uint16_t clearbits)
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{
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uint16_t val = eth_smi_read(phy, reg);
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eth_smi_write(phy, reg, val & (uint16_t)~(clearbits));
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Set bits in the register
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*
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* @param[in] phy uint8_t ID of the PHY (defaults to 1)
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* @param[in] reg uint8_t Register address
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* @param[in] setbits uint16_t Bits that have to be set (or'ed)
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*/
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void eth_smi_bit_set(uint8_t phy, uint8_t reg, uint16_t setbits)
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{
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uint16_t val = eth_smi_read(phy, reg);
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eth_smi_write(phy, reg, val | setbits);
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}
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/*---------------------------------------------------------------------------*/
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/**@}*/
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