Arti Zirk
054740c5de
subrepo: subdir: "libopencm3" merged: "88e91c9a7cce" upstream: origin: "https://github.com/libopencm3/libopencm3.git" branch: "master" commit: "88e91c9a7cce" git-subrepo: version: "0.4.3" origin: "???" commit: "???"
262 lines
7.9 KiB
C
262 lines
7.9 KiB
C
/**
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* @brief <b>PAC55xxxx CCS Driver</b>
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* @author @htmlonly © @endhtmlonly 2020 Kevin Stefanik <kevin@allocor.tech>
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* @date March 7, 2020
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*
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* This library supports the CCS module in the PAC55xx SoC from Qorvo.
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/pac55xx/ccs.h>
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#include <libopencm3/pac55xx/memorymap.h>
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#include <libopencm3/pac55xx/memctl.h>
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#include <libopencm3/cm3/assert.h>
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static volatile uint32_t ccs_extclk_frequency = 0;
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static volatile uint32_t ccs_frclk_frequency = CCS_ROSC_FREQ;
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static volatile uint32_t ccs_sclk_frequency = CCS_ROSC_FREQ;
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static volatile uint32_t ccs_pll_clk_frequency = 0;
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static volatile uint32_t ccs_hclk_frequency = CCS_ROSC_FREQ;
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static volatile uint32_t ccs_aclk_frequency = CCS_ROSC_FREQ;
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static volatile uint32_t ccs_pclk_frequency = CCS_ROSC_FREQ;
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void ccs_frclkmux_select(uint32_t sel) {
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CCSCTL = (CCSCTL & ~CCS_CTL_FRCLKMUXSEL(CCS_CTL_FRCLKMUXSEL_MASK)) | CCS_CTL_FRCLKMUXSEL(sel);
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}
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void ccs_rosc_enable(void) {
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CCSCTL |= CCS_CTL_ROSCEN;
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}
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void ccs_rosc_disable(void) {
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CCSCTL &= ~CCS_CTL_ROSCEN;
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}
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void ccs_sclkmux_select_frclk(void) {
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CCSCTL &= ~CCS_CTL_SCLKMUXSEL;
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}
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void ccs_sclkmux_select_pllclk(void) {
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CCSCTL |= CCS_CTL_SCLKMUXSEL;
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}
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void ccs_clkfail_enable(void) {
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CCSCTL |= CCS_CTL_CLKFAILEN;
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}
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void ccs_clkfail_disable(void) {
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CCSCTL &= ~CCS_CTL_CLKFAILEN;
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}
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void ccs_clkfailmux_select_frclk(void) {
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CCSCTL &= ~CCS_CTL_CLKFAILMUXSEL;
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}
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void ccs_clkfailmux_select_pllclk(void) {
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CCSCTL |= CCS_CTL_CLKFAILMUXSEL;
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}
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void ccs_ldo_enable(void) {
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CCSCTL |= CCS_CTL_LDOEN;
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}
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void ccs_ldo_disable(void) {
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CCSCTL &= ~CCS_CTL_LDOEN;
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}
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void ccs_pclk_enable(void) {
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CCSCTL |= CCS_CTL_PCLKEN;
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}
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void ccs_pclk_disable(void) {
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CCSCTL &= ~CCS_CTL_PCLKEN;
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}
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void ccs_aclk_enable(void) {
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CCSCTL |= CCS_CTL_ACLKEN;
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}
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void ccs_aclk_disable(void) {
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CCSCTL &= ~CCS_CTL_ACLKEN;
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}
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void ccs_adcclk_enable(void) {
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CCSCTL |= CCS_CTL_ADCCLKEN;
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}
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void ccs_adcclk_disable(void) {
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CCSCTL &= ~CCS_CTL_ADCCLKEN;
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}
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void ccs_stclk_sleep_enable(void) {
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CCSCTL |= CCS_CTL_STCLKSLPEN;
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}
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void ccs_stclk_sleep_disable(void) {
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CCSCTL &= ~CCS_CTL_STCLKSLPEN;
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}
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void ccs_set_pclkdiv(uint32_t div) {
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CCSCTL = (CCSCTL & ~CCS_CTL_PCLKDIV(8)) | CCS_CTL_PCLKDIV(div);
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}
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void ccs_set_aclkdiv(uint32_t div) {
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CCSCTL = (CCSCTL & ~CCS_CTL_ACLKDIV(8)) | CCS_CTL_ACLKDIV(div);
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}
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void ccs_set_hclkdiv(uint32_t div) {
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CCSCTL = (CCSCTL & ~CCS_CTL_HCLKDIV(8)) | CCS_CTL_HCLKDIV(div);
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}
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void ccs_pll_enable(void) {
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CCSPLLCTL |= CCS_PLLCTL_PLLEN;
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}
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void ccs_pll_disable(void) {
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CCSPLLCTL &= ~CCS_PLLCTL_PLLEN;
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}
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bool ccs_pll_locked(void) {
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return (CCSPLLCTL & CCS_PLLCTL_PLLLOCK) == CCS_PLLCTL_PLLLOCK;
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}
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void ccs_pll_bypass_enable(void) {
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CCSPLLCTL |= CCS_PLLCTL_PLLBP;
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}
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void ccs_pll_bypass_disable(void) {
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CCSPLLCTL &= ~CCS_PLLCTL_PLLBP;
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}
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void ccs_pll_set_outdiv(uint32_t div) {
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CCSPLLCTL = (CCSPLLCTL & ~CCS_PLLCTL_PLLOUTDIV(CCS_PLLCTL_PLLOUTDIV_MASK)) | CCS_PLLCTL_PLLOUTDIV(div);
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}
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void ccs_pll_set_indiv(uint32_t div) {
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if (div <= 15 && div >= 1) {
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CCSPLLCTL = (CCSPLLCTL & ~CCS_PLLCTL_PLLINDIV(CCS_PLLCTL_PLLINDIV_MASK)) | CCS_PLLCTL_PLLINDIV(div);
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} else {
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cm3_assert_not_reached();
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}
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}
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void ccs_pll_set_fbdiv(uint32_t div) {
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if (div <= 16383 && div >= 4) {
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CCSPLLCTL = (CCSPLLCTL & ~CCS_PLLCTL_PLLFBDIV(CCS_PLLCTL_PLLFBDIV_MASK)) | CCS_PLLCTL_PLLFBDIV(div);
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} else {
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cm3_assert_not_reached();
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}
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}
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void css_pll_config_enable(uint32_t indiv, uint32_t fbdiv, uint32_t outdiv) {
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ccs_pll_disable();
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ccs_pll_set_fbdiv(fbdiv);
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ccs_pll_set_outdiv(outdiv);
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ccs_pll_set_indiv(indiv);
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ccs_pll_enable();
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while (!ccs_pll_locked()) ; /* Wait for PLL lock ~500us */
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}
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uint32_t ccs_get_peripheral_clk_freq(uint32_t periph, uint32_t select) {
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switch (periph) {
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case ADC_BASE:
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return ccs_sclk_frequency;
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case I2C_BASE: /* fall through */
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case USARTA_BASE: /* fall through */
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case USARTB_BASE: /* fall through */
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case USARTC_BASE: /* fall through */
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case USARTD_BASE: /* fall through */
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case CAN_BASE: /* fall through */
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case GPTIMERA_BASE: /* fall through */
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case GPTIMERB_BASE:
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return ccs_pclk_frequency;
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case TIMERA_BASE: /* fall through */
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case TIMERB_BASE: /* fall through */
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case TIMERC_BASE: /* fall through */
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case TIMERD_BASE:
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return (select == 0) ? ccs_pclk_frequency : ccs_aclk_frequency;
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case MEMCTL_BASE:
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return (select == 0) ? CCS_ROSC_FREQ : ccs_hclk_frequency;
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case WWDT_BASE:
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return (select == 0) ? ccs_frclk_frequency : CCS_ROSC_FREQ;
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case RTC_BASE:
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return ccs_frclk_frequency;
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case CRC_BASE: /* fall through */
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case SYS_TICK_BASE:
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return ccs_hclk_frequency;
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default:
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cm3_assert_not_reached();
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}
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}
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void ccs_reset_clocks(void) {
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CCSCTL = CCS_CTL_LDOEN | CCS_CTL_ROSCEN |
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CCS_CTL_PCLKEN | CCS_CTL_ACLKEN |
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CCS_CTL_ADCCLKEN | CCS_CTL_STCLKSLPEN;
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CCSPLLCTL = 0;
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}
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void ccs_configure_clocks(const struct ccs_clk_config *config) {
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MEMCTL_FLASHLOCK = MEMCTL_FLASHLOCK_ALLOW_MEMCTL_WRITE;
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ccs_reset_clocks(); /* set safe defaults */
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ccs_frclkmux_select(CCS_CTL_FRCLKMUXSEL_ROSC);
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ccs_sclkmux_select_frclk();
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memctl_flash_select_roscclk();
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if (config->mem_enable_cache) {
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memctl_flash_cache_enable();
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} else {
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memctl_flash_cache_disable();
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}
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ccs_frclkmux_select(CCS_CTL_FRCLKMUXSEL_CLKREF); /* switch frclk to 4MHz CLKREF */
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switch (config->frclk_source) {
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case CCS_CTL_FRCLKMUXSEL_ROSC:
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ccs_frclkmux_select(CCS_CTL_FRCLKMUXSEL_ROSC);
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ccs_frclk_frequency = CCS_ROSC_FREQ;
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break;
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case CCS_CTL_FRCLKMUXSEL_CLKREF:
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ccs_frclkmux_select(CCS_CTL_FRCLKMUXSEL_CLKREF);
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ccs_frclk_frequency = CCS_CLKREF_FREQ;
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break;
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case CCS_CTL_FRCLKMUXSEL_EXTCLK:
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if (config->extclk_frequency > CCS_EXTCLK_MAX_FREQ
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|| config->extclk_frequency == 0) {
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cm3_assert_not_reached();
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}
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ccs_frclkmux_select(CCS_CTL_FRCLKMUXSEL_EXTCLK);
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ccs_frclk_frequency = ccs_extclk_frequency = config->extclk_frequency;
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break;
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default:
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cm3_assert_not_reached();
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}
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if (config->sclk_source == CCS_CTL_SCLKMUXSEL_FRCLK) {
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ccs_set_hclkdiv(config->hclkdiv);
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ccs_set_aclkdiv(config->aclkdiv);
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memctl_flash_set_wstate(config->mem_wstate);
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ccs_sclkmux_select_frclk();
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memctl_flash_set_mclkdiv(config->mem_mclkdiv);
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if (config->mem_mclksel == false) {
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memctl_flash_select_roscclk();
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} else {
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memctl_flash_select_mclk();
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}
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ccs_sclk_frequency = ccs_frclk_frequency;
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} else if (config->sclk_source == CCS_CTL_SCLKMUXSEL_PLLCLK) {
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css_pll_config_enable(config->pll_indiv, config->pll_fbdiv, config->pll_outdiv);
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ccs_set_hclkdiv(config->hclkdiv);
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ccs_set_aclkdiv(config->aclkdiv);
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memctl_flash_set_wstate(config->mem_wstate);
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ccs_sclkmux_select_pllclk();
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memctl_flash_set_mclkdiv(config->mem_mclkdiv);
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if (config->mem_mclksel == false) {
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memctl_flash_select_roscclk();
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} else {
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memctl_flash_select_mclk();
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}
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ccs_pll_clk_frequency = ((ccs_frclk_frequency * config->pll_fbdiv) / config->pll_indiv) >> config->pll_outdiv;
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ccs_sclk_frequency = ccs_pll_clk_frequency;
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} else {
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cm3_assert_not_reached();
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}
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ccs_set_pclkdiv(config->pclkdiv);
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ccs_pclk_enable();
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ccs_aclk_enable();
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ccs_adcclk_enable();
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ccs_stclk_sleep_disable();
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ccs_hclk_frequency = ccs_sclk_frequency / config->hclkdiv;
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ccs_aclk_frequency = ccs_sclk_frequency / config->aclkdiv;
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ccs_pclk_frequency = ccs_hclk_frequency / config->pclkdiv;
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MEMCTL_FLASHLOCK = MEMCTL_FLASHLOCK_CLEAR;
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}
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