Arti Zirk
054740c5de
subrepo: subdir: "libopencm3" merged: "88e91c9a7cce" upstream: origin: "https://github.com/libopencm3/libopencm3.git" branch: "master" commit: "88e91c9a7cce" git-subrepo: version: "0.4.3" origin: "???" commit: "???"
541 lines
16 KiB
C
541 lines
16 KiB
C
/** @addtogroup adc_file ADC peripheral API
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* @ingroup peripheral_apis
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*
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* based on F3 file
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*
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* @date 14 July 2013
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/cm3/assert.h>
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#include <libopencm3/stm32/adc.h>
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/**@{*/
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/**
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* @defgroup adc_api_opmode ADC Operation mode API
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* @ingroup adc_file
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*
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* @brief ADC Result API
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*
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*@{*/
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Enable Discontinuous Mode for Regular Conversions
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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*/
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void adc_enable_discontinuous_mode(uint32_t adc)
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{
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ADC_CFGR1(adc) |= ADC_CFGR1_DISCEN;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Disable Discontinuous Mode for Regular Conversions
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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*/
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void adc_disable_discontinuous_mode(uint32_t adc)
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{
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ADC_CFGR1(adc) &= ~ADC_CFGR1_DISCEN;
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}
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/*---------------------------------------------------------------------------*/
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/** ADC Set operation mode
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*
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* There are some operation modes, common for entire stm32 branch. In the text
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* the braces are describing result to single trigger event. The trigger event
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* is described by character T in the description. The ADC is configured to
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* convert list of inputs [0, 1, 2, 3]. In Grouped modes, there is used group
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* size of 2 conversions in the examples
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*
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* @li @c ADC_MODE_SEQUENTIAL: T(0) T(1) T(2) T(3)[EOSEQ] T(0) T(1) T(2) ...
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*
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* In this mode, after the trigger event a single channel is converted and the
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* next channel in the list is prepared to convert on next trigger edge.
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*
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* @note This mode can be emulated by ADC_MODE_GROUPED with group size
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* of 1.
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*
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* @li @c ADC_MODE_SCAN: T(0123)[EOSEQ] T(0123)[EOSEQ] T(0123)[EOSEQ]
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*
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* In this mode, after the trigger event, all channels will be converted once,
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* storing results sequentially.
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*
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* @note The DMA must be configured properly for more than single channel to
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* convert.
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*
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* @li @c ADC_MODE_SCAN_INFINITE: T(0123[EOSEQ]0123[EOSEQ]0123[EOSEQ]...)
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*
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* In this mode, after the trigger event, all channels from the list are
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* converted. At the end of list, the conversion continues from the beginning.
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*
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* @note The DMA must be configured properly to operate in this mode.@par
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*
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* @li @c ADC_MODE_GROUPED: T(12) T(34)[EOSEQ] T(12) T(34)[EOSEQ] T(12)
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*
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* In this mode, after the trigger event, a specified group size of channels
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* are converted. If the end of channel list occurs, the EOSEQ is generated
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* and on the next trigger it wraps to the beginning.
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*
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* @note The DMA must be configured properly to operate on more than single
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* channel conversion groups.
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*
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* @warning not all families supports all modes of operation of ADC.
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*
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*/
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Set conversion operation mode
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*
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* @note on SEQUENTIAL mode, the trigger event is necessary to start conversion.
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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* @param[in] opmode ADC operation mode
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*/
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void adc_set_operation_mode(uint32_t adc, enum adc_opmode opmode)
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{
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switch (opmode) {
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case ADC_MODE_SEQUENTIAL:
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ADC_CFGR1(adc) &= ~ADC_CFGR1_CONT;
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ADC_CFGR1(adc) |= ADC_CFGR1_DISCEN;
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break;
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case ADC_MODE_SCAN:
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ADC_CFGR1(adc) &= ~(ADC_CFGR1_CONT | ADC_CFGR1_DISCEN);
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break;
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case ADC_MODE_SCAN_INFINITE:
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ADC_CFGR1(adc) &= ~ADC_CFGR1_DISCEN;
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ADC_CFGR1(adc) |= ADC_CFGR1_CONT;
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break;
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}
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}
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/**@}*/
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/**
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* @defgroup adc_api_trigger ADC Trigger API
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* @ingroup adc_file
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*
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* @brief ADC Trigger API
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*
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*@{*/
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Enable an External Trigger for Regular Channels
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*
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* This enables an external trigger for set of defined regular channels, and
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* sets the polarity of the trigger event: rising or falling edge or both. Note
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* that if the trigger polarity is zero, triggering is disabled.
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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* @param[in] trigger Unsigned int32. Trigger identifier
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* @ref adc_trigger_regular
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* @param[in] polarity Unsigned int32. Trigger polarity @ref
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* adc_trigger_polarity_regular
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*/
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void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger,
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uint32_t polarity)
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{
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ADC_CFGR1(adc) = (ADC_CFGR1(adc) & ~ADC_CFGR1_EXTSEL) | trigger;
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ADC_CFGR1(adc) = (ADC_CFGR1(adc) & ~ADC_CFGR1_EXTEN_MASK) | polarity;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Disable an External Trigger for Regular Channels
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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*/
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void adc_disable_external_trigger_regular(uint32_t adc)
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{
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ADC_CFGR1(adc) &= ~ADC_CFGR1_EXTEN_MASK;
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}
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/**@}*/
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/**
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* @defgroup adc_api_interrupts ADC Interrupt configuration API
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* @ingroup adc_file
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*
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* @brief ADC Interrupt configuration API
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*
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*@{*/
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Enable Analog Watchdog Interrupt
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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*/
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void adc_enable_watchdog_interrupt(uint32_t adc)
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{
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ADC_IER(adc) |= ADC_IER_AWD1IE;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Disable Regular End-Of-Conversion Interrupt
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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*/
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void adc_disable_watchdog_interrupt(uint32_t adc)
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{
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ADC_IER(adc) &= ~ADC_IER_AWD1IE;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Read the Analog Watchdog Flag
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*
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* This flag is set when the converted voltage crosses the high or low
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* thresholds.
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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* @returns bool true, if the signal is out of defined analog range.
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*/
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bool adc_get_watchdog_flag(uint32_t adc)
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{
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return ADC_ISR(adc) & ADC_ISR_AWD1;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Clear Analog Watchdog Flag
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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*/
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void adc_clear_watchdog_flag(uint32_t adc)
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{
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ADC_ISR(adc) = ADC_ISR_AWD1;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Enable Regular End-Of-Conversion Sequence Interrupt
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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*/
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void adc_enable_eoc_sequence_interrupt(uint32_t adc)
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{
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ADC_IER(adc) |= ADC_IER_EOSEQIE;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Disable Regular End-Of-Conversion Sequence Interrupt
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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*/
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void adc_disable_eoc_sequence_interrupt(uint32_t adc)
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{
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ADC_IER(adc) &= ~ADC_IER_EOSEQIE;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Read the Regular End-Of-Conversion Sequence Flag
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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*/
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bool adc_get_eoc_sequence_flag(uint32_t adc)
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{
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return ADC_ISR(adc) & ADC_ISR_EOSEQ;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Clear Regular End-Of-Conversion Sequence Flag
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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*/
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void adc_clear_eoc_sequence_flag(uint32_t adc)
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{
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ADC_ISR(adc) = ADC_ISR_EOSEQ;
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}
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/**@}*/
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/**
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* @defgroup adc_api_config ADC Basic configuration API
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* @ingroup adc_file
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*
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* @brief ADC Basic configuration API
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*
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*@{*/
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Set Clock Source
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*
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* The ADC clock taken from the many sources.
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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* @param[in] source Unsigned int32. Source (@ref adc_api_clksource)
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*/
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void adc_set_clk_source(uint32_t adc, uint32_t source)
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{
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ADC_CFGR2(adc) = ((ADC_CFGR2(adc) & ~ADC_CFGR2_CKMODE) | source);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Set a Regular Channel Conversion Sequence
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*
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* Define a sequence of channels to be converted as a regular group with a
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* length from 1 to 18 channels. If this is called during conversion, the
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* current conversion is reset and conversion begins again with the newly
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* defined group.
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*
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* @warning This core doesn't support the random order of ADC conversions.
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* The channel list must be ordered by channel number.
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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* @param[in] length Unsigned int8. Number of channels in the group.
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* @param[in] channel Unsigned int8[]. Set of channels to convert, integers
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* 0..18.
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*/
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void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[])
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{
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uint32_t reg32 = 0;
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uint8_t i = 0;
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bool stepup = false, stepdn = false;
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if (length == 0) {
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ADC_CHSELR(adc) = 0;
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return;
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}
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reg32 |= (1 << channel[0]);
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for (i = 1; i < length; i++) {
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reg32 |= (1 << channel[i]);
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stepup |= channel[i-1] < channel[i];
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stepdn |= channel[i-1] > channel[i];
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}
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/* Check, if the channel list is in order */
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if (stepup && stepdn) {
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cm3_assert_not_reached();
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}
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/* Update the scan direction flag */
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if (stepdn) {
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ADC_CFGR1(adc) |= ADC_CFGR1_SCANDIR;
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} else {
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ADC_CFGR1(adc) &= ~ADC_CFGR1_SCANDIR;
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}
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ADC_CHSELR(adc) = reg32;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Set the Sample Time for All Channels
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*
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* The sampling time can be selected in ADC clock cycles from 1.5 to 239.5,
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* same for all channels.
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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* @param[in] time Unsigned int8. Sampling time selection (@ref adc_api_smptime)
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*/
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void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time)
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{
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ADC_SMPR(adc) = time & ADC_SMPR_SMP;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Enable The VBat Sensor
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*
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* This enables the battery voltage measurements on channel 17.
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*/
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void adc_enable_vbat_sensor(void)
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{
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ADC_CCR(ADC1) |= ADC_CCR_VBATEN;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Disable The VBat Sensor
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*
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* Disabling this will reduce power consumption from the battery voltage
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* measurement.
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*/
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void adc_disable_vbat_sensor(void)
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{
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ADC_CCR(ADC1) &= ~ADC_CCR_VBATEN;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Start the calibration procedure
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* @deprecated Replaced by adc_calibrate/_async/is_calibrating
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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*/
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void adc_calibrate_start(uint32_t adc)
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{
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ADC_CR(adc) = ADC_CR_ADCAL;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Wait to finish the ADC calibration procedure
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* @deprecated Replaced by adc_calibrate/_async/is_calibrating
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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*/
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void adc_calibrate_wait_finish(uint32_t adc)
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{
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while (ADC_CR(adc) & ADC_CR_ADCAL);
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}
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/**@}*/
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/**
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* @defgroup adc_api_wdg ADC Analog watchdog API
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* @ingroup adc_file
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*
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* @brief ADC analog watchdog API definitions.
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*
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* The analog watchdog allows the monitoring of an analog signal between two
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* threshold levels. The thresholds must be preset. Analog watchdog is disabled
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* by default.
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*
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* @warning Comparison is done before data alignment takes place, so the
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* thresholds are left-aligned.
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*
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* Example 1: Enable watchdog checking on all channels
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*
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* @code
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* // in configuration
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* adc_enable_analog_watchdog_on_all_channels(ADC1);
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* adc_set_watchdog_high_threshold(ADC1, 0xE00);
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* adc_set_watchdog_low_threshold(ADC1, 0x200);
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*
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* // in the main application thread
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* if (adc_get_watchdog_flag(ADC1)) {
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* // the converted signal is out of AWD ranges
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* adc_clear_watchdog_flag(ADC1);
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* }
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* @endcode
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*
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* Example 2: Enable watchdog checking on channel 5
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*
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* @code
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* // in configuration
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* adc_enable_analog_watchdog_on_selected_channel(ADC1,5);
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* adc_set_watchdog_high_threshold(ADC1, 0xE00);
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* adc_set_watchdog_low_threshold(ADC1, 0x200);
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*
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* // in the main application thread
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* if (adc_get_watchdog_flag(ADC1)) {
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* // the converted signal is out of AWD ranges
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* adc_clear_watchdog_flag(ADC1);
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* }
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* @endcode
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*@{*/
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Enable Analog Watchdog for All Channels
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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*/
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void adc_enable_analog_watchdog_on_all_channels(uint32_t adc)
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{
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ADC_CFGR1(adc) |= ADC_CFGR1_AWD1EN;
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ADC_CFGR1(adc) &= ~ADC_CFGR1_AWD1SGL;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Enable Analog Watchdog for a Selected Channel
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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* @param[in] chan Unsigned int8. ADC channel number @ref adc_api_channel
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*/
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void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, uint8_t chan)
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{
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ADC_CFGR1(adc) = (ADC_CFGR1(adc) & ~ADC_CFGR1_AWD1CH) |
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ADC_CFGR1_AWD1CH_VAL(chan);
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ADC_CFGR1(adc) |= ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Disable Analog Watchdog
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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*/
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void adc_disable_analog_watchdog(uint32_t adc)
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{
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ADC_CFGR1(adc) &= ~ADC_CFGR1_AWD1EN;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Set Analog Watchdog Upper Threshold
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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* @param[in] threshold Upper threshold value
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*/
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|
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void adc_set_watchdog_high_threshold(uint32_t adc, uint16_t threshold)
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{
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ADC_TR1(adc) = (ADC_TR1(adc) & ~ADC_TR1_HT) | ADC_TR1_HT_VAL(threshold);
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}
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|
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Set Analog Watchdog Lower Threshold
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*
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|
* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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|
* @param[in] threshold Lower threshold value
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|
*/
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|
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void adc_set_watchdog_low_threshold(uint32_t adc, uint16_t threshold)
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|
{
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ADC_TR1(adc) = (ADC_TR1(adc) & ~ADC_TR1_LT) | ADC_TR1_LT_VAL(threshold);
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}
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|
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/**@}*/
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/*---------------------------------------------------------------------------*/
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/**@}*/
|