Arti Zirk
054740c5de
subrepo: subdir: "libopencm3" merged: "88e91c9a7cce" upstream: origin: "https://github.com/libopencm3/libopencm3.git" branch: "master" commit: "88e91c9a7cce" git-subrepo: version: "0.4.3" origin: "???" commit: "???"
446 lines
11 KiB
YAML
446 lines
11 KiB
YAML
!!omap
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- SSP0_CR0:
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fields: !!omap
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- DSS:
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access: rw
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description: Data Size Select
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lsb: 0
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reset_value: '0'
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width: 4
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- FRF:
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access: rw
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description: Frame Format
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lsb: 4
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reset_value: '0'
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width: 2
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- CPOL:
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access: rw
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description: Clock Out Polarity
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lsb: 6
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reset_value: '0'
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width: 1
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- CPHA:
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access: rw
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description: Clock Out Phase
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lsb: 7
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reset_value: '0'
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width: 1
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- SCR:
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access: rw
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description: Serial Clock Rate
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lsb: 8
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reset_value: '0'
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width: 8
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- SSP1_CR0:
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fields: !!omap
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- DSS:
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access: rw
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description: Data Size Select
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lsb: 0
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reset_value: '0'
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width: 4
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- FRF:
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access: rw
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description: Frame Format
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lsb: 4
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reset_value: '0'
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width: 2
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- CPOL:
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access: rw
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description: Clock Out Polarity
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lsb: 6
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reset_value: '0'
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width: 1
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- CPHA:
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access: rw
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description: Clock Out Phase
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lsb: 7
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reset_value: '0'
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width: 1
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- SCR:
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access: rw
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description: Serial Clock Rate
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lsb: 8
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reset_value: '0'
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width: 8
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- SSP0_CR1:
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fields: !!omap
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- LBM:
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access: rw
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description: Loop Back Mode
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lsb: 0
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reset_value: '0'
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width: 1
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- SSE:
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access: rw
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description: SSP Enable
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lsb: 1
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reset_value: '0'
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width: 1
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- MS:
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access: rw
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description: Master/Slave Mode
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lsb: 2
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reset_value: '0'
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width: 1
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- SOD:
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access: rw
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description: Slave Output Disable
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lsb: 3
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reset_value: '0'
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width: 1
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- SSP1_CR1:
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fields: !!omap
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- SSE:
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access: rw
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description: SSP Enable
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lsb: 1
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reset_value: '0'
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width: 1
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- MS:
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access: rw
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description: Master/Slave Mode
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lsb: 2
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reset_value: '0'
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width: 1
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- SOD:
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access: rw
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description: Slave Output Disable
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lsb: 3
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reset_value: '0'
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width: 1
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- SSP0_DR:
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fields: !!omap
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- DATA:
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access: rw
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description: Software can write data to be transmitted to this register, and
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read data that has been
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lsb: 0
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reset_value: '0'
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width: 16
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- SSP1_DR:
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fields: !!omap
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- DATA:
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access: rw
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description: Software can write data to be transmitted to this register, and
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read data that has been
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lsb: 0
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reset_value: '0'
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width: 16
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- SSP0_SR:
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fields: !!omap
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- TFE:
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access: r
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description: Transmit FIFO Empty
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lsb: 0
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reset_value: '1'
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width: 1
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- TNF:
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access: r
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description: Transmit FIFO Not Full
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lsb: 1
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reset_value: '1'
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width: 1
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- RNE:
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access: r
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description: Receive FIFO Not Empty
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lsb: 2
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reset_value: '0'
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width: 1
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- RFF:
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access: r
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description: Receive FIFO Full
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lsb: 3
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reset_value: '0'
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width: 1
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- BSY:
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access: r
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description: Busy.
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lsb: 4
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reset_value: '0'
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width: 1
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- SSP1_SR:
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fields: !!omap
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- TFE:
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access: r
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description: Transmit FIFO Empty
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lsb: 0
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reset_value: '1'
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width: 1
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- TNF:
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access: r
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description: Transmit FIFO Not Full
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lsb: 1
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reset_value: '1'
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width: 1
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- RNE:
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access: r
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description: Receive FIFO Not Empty
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lsb: 2
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reset_value: '0'
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width: 1
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- RFF:
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access: r
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description: Receive FIFO Full
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lsb: 3
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reset_value: '0'
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width: 1
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- BSY:
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access: r
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description: Busy.
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lsb: 4
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reset_value: '0'
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width: 1
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- SSP0_CPSR:
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fields: !!omap
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- CPSDVSR:
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access: rw
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description: SSP Clock Prescale Register
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lsb: 0
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reset_value: '0'
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width: 8
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- SSP1_CPSR:
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fields: !!omap
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- CPSDVSR:
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access: rw
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description: SSP Clock Prescale Register
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lsb: 0
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reset_value: '0'
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width: 8
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- SSP0_IMSC:
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fields: !!omap
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- RORIM:
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access: rw
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description: Software should set this bit to enable interrupt when a Receive
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Overrun occurs
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lsb: 0
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reset_value: '0'
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width: 1
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- RTIM:
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access: rw
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description: Software should set this bit to enable interrupt when a Receive
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Time-out condition occurs
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lsb: 1
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reset_value: '0'
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width: 1
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- RXIM:
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access: rw
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description: Software should set this bit to enable interrupt when the Rx
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FIFO is at least half full
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lsb: 2
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reset_value: '0'
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width: 1
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- TXIM:
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access: rw
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description: Software should set this bit to enable interrupt when the Tx
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FIFO is at least half empty
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lsb: 3
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reset_value: '0'
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width: 1
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- SSP1_IMSC:
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fields: !!omap
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- RORIM:
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access: rw
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description: Software should set this bit to enable interrupt when a Receive
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Overrun occurs
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lsb: 0
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reset_value: '0'
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width: 1
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- RTIM:
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access: rw
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description: Software should set this bit to enable interrupt when a Receive
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Time-out condition occurs
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lsb: 1
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reset_value: '0'
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width: 1
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- RXIM:
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access: rw
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description: Software should set this bit to enable interrupt when the Rx
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FIFO is at least half full
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lsb: 2
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reset_value: '0'
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width: 1
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- TXIM:
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access: rw
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description: Software should set this bit to enable interrupt when the Tx
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FIFO is at least half empty
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lsb: 3
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reset_value: '0'
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width: 1
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- SSP0_RIS:
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fields: !!omap
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- RORRIS:
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access: r
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description: This bit is 1 if another frame was completely received while
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the RxFIFO was full
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lsb: 0
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reset_value: '0'
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width: 1
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- RTRIS:
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access: r
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description: This bit is 1 if the Rx FIFO is not empty, and has not been read
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for a time-out period
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lsb: 1
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reset_value: '0'
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width: 1
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- RXRIS:
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access: r
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description: This bit is 1 if the Rx FIFO is at least half full
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lsb: 2
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reset_value: '0'
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width: 1
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- TXRIS:
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access: r
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description: This bit is 1 if the Tx FIFO is at least half empty
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lsb: 3
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reset_value: '1'
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width: 1
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- SSP1_RIS:
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fields: !!omap
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- RORRIS:
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access: r
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description: This bit is 1 if another frame was completely received while
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the RxFIFO was full
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lsb: 0
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reset_value: '0'
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width: 1
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- RTRIS:
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access: r
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description: This bit is 1 if the Rx FIFO is not empty, and has not been read
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for a time-out period
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lsb: 1
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reset_value: '0'
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width: 1
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- RXRIS:
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access: r
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description: This bit is 1 if the Rx FIFO is at least half full
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lsb: 2
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reset_value: '0'
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width: 1
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- TXRIS:
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access: r
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description: This bit is 1 if the Tx FIFO is at least half empty
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lsb: 3
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reset_value: '1'
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width: 1
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- SSP0_MIS:
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fields: !!omap
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- RORMIS:
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access: r
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description: This bit is 1 if another frame was completely received while
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the RxFIFO was full, and this interrupt is enabled
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lsb: 0
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reset_value: '0'
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width: 1
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- RTMIS:
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access: r
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description: This bit is 1 if the Rx FIFO is not empty, has not been read
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for a time-out period, and this interrupt is enabled
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lsb: 1
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reset_value: '0'
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width: 1
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- RXMIS:
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access: r
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description: This bit is 1 if the Rx FIFO is at least half full, and this
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interrupt is enabled
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lsb: 2
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reset_value: '0'
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width: 1
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- TXMIS:
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access: r
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description: This bit is 1 if the Tx FIFO is at least half empty, and this
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interrupt is enabled
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lsb: 3
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reset_value: '0'
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width: 1
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- SSP1_MIS:
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fields: !!omap
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- RORMIS:
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access: r
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description: This bit is 1 if another frame was completely received while
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the RxFIFO was full, and this interrupt is enabled
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lsb: 0
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reset_value: '0'
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width: 1
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- RTMIS:
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access: r
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description: This bit is 1 if the Rx FIFO is not empty, has not been read
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for a time-out period, and this interrupt is enabled
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lsb: 1
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reset_value: '0'
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width: 1
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- RXMIS:
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access: r
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description: This bit is 1 if the Rx FIFO is at least half full, and this
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interrupt is enabled
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lsb: 2
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reset_value: '0'
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width: 1
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- TXMIS:
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access: r
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description: This bit is 1 if the Tx FIFO is at least half empty, and this
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interrupt is enabled
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lsb: 3
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reset_value: '0'
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width: 1
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- SSP0_ICR:
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fields: !!omap
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- RORIC:
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access: w
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description: Writing a 1 to this bit clears the 'frame was received when RxFIFO
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was full' interrupt
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lsb: 0
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reset_value: ''
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width: 1
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- RTIC:
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access: w
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description: Writing a 1 to this bit clears the Rx FIFO was not empty and
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has not been read for a time-out period interrupt
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lsb: 1
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reset_value: ''
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width: 1
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- SSP1_ICR:
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fields: !!omap
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- RORIC:
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access: w
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description: Writing a 1 to this bit clears the 'frame was received when RxFIFO
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was full' interrupt
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lsb: 0
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reset_value: ''
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width: 1
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- RTIC:
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access: w
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description: Writing a 1 to this bit clears the Rx FIFO was not empty and
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has not been read for a time-out period interrupt
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lsb: 1
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reset_value: ''
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width: 1
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- SSP0_DMACR:
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fields: !!omap
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- RXDMAE:
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access: rw
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description: Receive DMA Enable
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lsb: 0
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reset_value: '0'
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width: 1
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- TXDMAE:
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access: rw
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description: Transmit DMA Enable
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lsb: 1
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reset_value: '0'
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width: 1
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- SSP1_DMACR:
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fields: !!omap
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- RXDMAE:
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access: rw
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description: Receive DMA Enable
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lsb: 0
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reset_value: '0'
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width: 1
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- TXDMAE:
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access: rw
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description: Transmit DMA Enable
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lsb: 1
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reset_value: '0'
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width: 1
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