Arti Zirk
054740c5de
subrepo: subdir: "libopencm3" merged: "88e91c9a7cce" upstream: origin: "https://github.com/libopencm3/libopencm3.git" branch: "master" commit: "88e91c9a7cce" git-subrepo: version: "0.4.3" origin: "???" commit: "???"
289 lines
9.6 KiB
C
289 lines
9.6 KiB
C
/** @addtogroup rcc_file RCC peripheral API
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* @ingroup peripheral_apis
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2013 Frantisek Burian <bufran@seznam.cz>
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* .. file is merged from many other copyrighted files of stm32 family
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#include <libopencm3/stm32/rcc.h>
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Enable Peripheral Clocks.
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*
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* Enable the clock on particular peripherals. There are three registers
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* involved, each one controlling the enabling of clocks associated with the
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* AHB, APB1 and APB2 respectively. Several peripherals could be enabled
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* simultaneously <em>only if they are controlled by the same register</em>.
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* @sa rcc_periph_clock_enable for a less error prone version, if you only
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* need to enable a single peripheral.
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*
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* @param[in] *reg Unsigned int32. Pointer to a Clock Enable Register
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* (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
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*
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* @param[in] en Unsigned int32. Logical OR of all enables to be set
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* @li If register is RCC_AHBENR, from @ref rcc_ahbenr_en
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* @li If register is RCC_APB1ENR, from @ref rcc_apb1enr_en
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* @li If register is RCC_APB2ENR, from @ref rcc_apb2enr_en
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*/
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void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en)
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{
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*reg |= en;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Disable Peripheral Clocks.
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*
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* Disable the clock on particular peripherals. There are three registers
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* involved, each one controlling the enabling of clocks associated with
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* the AHB, APB1 and APB2 respectively. Several peripherals could be disabled
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* simultaneously <em>only if they are controlled by the same register</em>.
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* @sa rcc_periph_clock_disable for a less error prone version, if you only
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* need to disable a single peripheral.
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*
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* @param[in] *reg Unsigned int32. Pointer to a Clock Enable Register
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* (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
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* @param[in] en Unsigned int32. Logical OR of all enables to be used for
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* disabling.
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* @li If register is RCC_AHBENR, from @ref rcc_ahbenr_en
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* @li If register is RCC_APB1ENR, from @ref rcc_apb1enr_en
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* @li If register is RCC_APB2ENR, from @ref rcc_apb2enr_en
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*/
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void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en)
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{
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*reg &= ~en;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Reset Peripherals.
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*
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* Reset particular peripherals. There are three registers involved, each one
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* controlling reset of peripherals associated with the AHB, APB1 and APB2
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* respectively. Several peripherals could be reset simultaneously <em>only if
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* they are controlled by the same register</em>.
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* @sa rcc_periph_reset_hold for a less error prone version, if you only
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* need to reset a single peripheral.
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* @sa rcc_periph_reset_pulse if you are only going to toggle reset anyway.
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*
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* @param[in] *reg Unsigned int32. Pointer to a Reset Register
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* (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
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* @param[in] reset Unsigned int32. Logical OR of all resets.
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* @li If register is RCC_AHBRSTR, from @ref rcc_ahbrstr_rst
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* @li If register is RCC_APB1RSTR, from @ref rcc_apb1rstr_rst
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* @li If register is RCC_APB2RSTR, from @ref rcc_apb2rstr_rst
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*/
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void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset)
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{
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*reg |= reset;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Remove Reset on Peripherals.
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*
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* Remove the reset on particular peripherals. There are three registers
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* involved, each one controlling reset of peripherals associated with the AHB,
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* APB1 and APB2 respectively. Several peripherals could have the reset removed
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* simultaneously <em>only if they are controlled by the same register</em>.
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* @sa rcc_periph_reset_release for a less error prone version, if you only
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* need to unreset a single peripheral.
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* @sa rcc_periph_reset_pulse if you are only going to toggle reset anyway.
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*
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* @param[in] *reg Unsigned int32. Pointer to a Reset Register
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* (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
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* @param[in] clear_reset Unsigned int32. Logical OR of all resets to be
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* removed:
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* @li If register is RCC_AHBRSTR, from @ref rcc_ahbrstr_rst
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* @li If register is RCC_APB1RSTR, from @ref rcc_apb1rstr_rst
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* @li If register is RCC_APB2RSTR, from @ref rcc_apb2rstr_rst
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*/
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void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset)
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{
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*reg &= ~clear_reset;
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}
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#define _RCC_REG(i) MMIO32(RCC_BASE + ((i) >> 5))
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#define _RCC_BIT(i) (1 << ((i) & 0x1f))
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/*---------------------------------------------------------------------------*/
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/** @brief Enable Peripheral Clock in running mode.
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*
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* Enable the clock on particular peripheral.
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*
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* @param[in] clken rcc_periph_clken Peripheral RCC
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*
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* For available constants, see #rcc_periph_clken (RCC_UART1 for example)
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*/
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void rcc_periph_clock_enable(enum rcc_periph_clken clken)
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{
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_RCC_REG(clken) |= _RCC_BIT(clken);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Disable Peripheral Clock in running mode.
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* Disable the clock on particular peripheral.
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*
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* @param[in] clken rcc_periph_clken Peripheral RCC
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*
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* For available constants, see #rcc_periph_clken (RCC_UART1 for example)
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*/
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void rcc_periph_clock_disable(enum rcc_periph_clken clken)
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{
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_RCC_REG(clken) &= ~_RCC_BIT(clken);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Reset Peripheral, pulsed
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*
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* Reset particular peripheral, and restore to working state.
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*
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* @param[in] rst rcc_periph_rst Peripheral reset
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*
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* For available constants, see #rcc_periph_rst (RST_UART1 for example)
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*/
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void rcc_periph_reset_pulse(enum rcc_periph_rst rst)
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{
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_RCC_REG(rst) |= _RCC_BIT(rst);
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_RCC_REG(rst) &= ~_RCC_BIT(rst);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Reset Peripheral, hold
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*
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* Reset particular peripheral, and hold in reset state.
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*
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* @param[in] rst rcc_periph_rst Peripheral reset
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*
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* For available constants, see #rcc_periph_rst (RST_UART1 for example)
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*/
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void rcc_periph_reset_hold(enum rcc_periph_rst rst)
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{
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_RCC_REG(rst) |= _RCC_BIT(rst);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Reset Peripheral, release
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*
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* Restore peripheral from reset state to working state.
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*
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* @param[in] rst rcc_periph_rst Peripheral reset
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*
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* For available constants, see #rcc_periph_rst (RST_UART1 for example)
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*/
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void rcc_periph_reset_release(enum rcc_periph_rst rst)
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{
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_RCC_REG(rst) &= ~_RCC_BIT(rst);
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}
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/** @brief Select the source of Microcontroller Clock Output
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*
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* Exact sources available depend on your target. On devices with multiple
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* MCO pins, this function controls MCO1
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*
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* @param[in] mcosrc the unshifted source bits
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*/
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void rcc_set_mco(uint32_t mcosrc)
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{
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RCC_CFGR = (RCC_CFGR & ~(RCC_CFGR_MCO_MASK << RCC_CFGR_MCO_SHIFT)) |
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(mcosrc << RCC_CFGR_MCO_SHIFT);
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}
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/**
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* RCC Enable Bypass.
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* Enable an external clock to bypass the internal clock (high speed and low
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* speed clocks only). The external clock must be enabled (see @ref rcc_osc_on)
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* and the internal clock must be disabled (see @ref rcc_osc_off) for this to
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* have effect.
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* @note The LSE clock is in the backup domain and cannot be bypassed until the
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* backup domain write protection has been removed (see @ref
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* pwr_disable_backup_domain_write_protect).
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* @param[in] osc Oscillator ID. Only HSE and LSE have effect.
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*/
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void rcc_osc_bypass_enable(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_HSE:
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RCC_CR |= RCC_CR_HSEBYP;
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break;
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case RCC_LSE:
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#ifdef RCC_CSR_LSEBYP
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RCC_CSR |= RCC_CSR_LSEBYP;
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#else
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RCC_BDCR |= RCC_BDCR_LSEBYP;
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#endif
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break;
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default:
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/* Do nothing, only HSE/LSE allowed here. */
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break;
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}
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}
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/**
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* RCC Disable Bypass.
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* Re-enable the internal clock (high speed and low speed clocks only). The
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* internal clock must be disabled (see @ref rcc_osc_off) for this to have
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* effect.
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* @note The LSE clock is in the backup domain and cannot have bypass removed
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* until the backup domain write protection has been removed (see @ref
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* pwr_disable_backup_domain_write_protect) or the backup domain has been reset
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* (see @ref rcc_backupdomain_reset).
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* @param[in] osc Oscillator ID. Only HSE and LSE have effect.
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*/
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void rcc_osc_bypass_disable(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_HSE:
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RCC_CR &= ~RCC_CR_HSEBYP;
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break;
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case RCC_LSE:
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#ifdef RCC_CSR_LSEBYP
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RCC_CSR &= ~RCC_CSR_LSEBYP;
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#else
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RCC_BDCR &= ~RCC_BDCR_LSEBYP;
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#endif
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break;
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default:
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/* Do nothing, only HSE/LSE allowed here. */
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break;
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}
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}
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/* This is a helper to calculate dividers that go 2/4/8/16/64/128/256/512.
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* These dividers also use the top bit as an "enable". This is typically
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* used for AHB and other system clock prescaler. */
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uint16_t rcc_get_div_from_hpre(uint8_t div_val) {
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if (div_val < 0x8) {
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return 1;
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} else if (div_val <= 0x0b /* DIV16 */) {
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return (1U << (div_val - 7));
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} else {
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return (1U << (div_val - 6));
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}
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}
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/**@}*/
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#undef _RCC_REG
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#undef _RCC_BIT
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