Arti Zirk
054740c5de
subrepo: subdir: "libopencm3" merged: "88e91c9a7cce" upstream: origin: "https://github.com/libopencm3/libopencm3.git" branch: "master" commit: "88e91c9a7cce" git-subrepo: version: "0.4.3" origin: "???" commit: "???"
86 lines
2.8 KiB
C
86 lines
2.8 KiB
C
/** @defgroup clk_file Clock peripheral API
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* @ingroup peripheral_apis
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* @brief SWM050 Clock API.
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* LGPL License Terms @ref lgpl_license
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* @author @htmlonly © @endhtmlonly 2019
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* Caleb Szalacinski <contact@skiboy.net>
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2019 Caleb Szalacinski <contact@skiboy.net>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#include <libopencm3/swm050/clk.h>
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#include <libopencm3/swm050/sysctl.h>
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/*---------------------------------------------------------------------------*/
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/** @brief Setup and change the system clock multiplier and divider
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Change system clock speed and wait for the clock to stabilize. The clock only
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needs time to stabilize on the first invocation of this function. This should be
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run at startup if you want to have a stable clock before doing anything.
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@param[in] mhz Base clock speed @ref clk_speeds
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The base clock speed, before the clock divider
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@param[in] div Clock divider
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Takes values from 0 to 1023 (in reality the possible values are the even
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numbers from 2 to 1022, as well as the number 1). Anything more than the
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first 10 bits is stripped off of the value. If the value is 0, it will
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be treated as a 1. All odd values other than 1 are rounded down to the
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closest even value, due to the fact that all odd values are treated by
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the register as a 1, which would likely be unexpected. A value of 0
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would also normally be treated as a 2, which would also be unexpected
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behavior.
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*/
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void clk_speed(enum clk_speeds mhz, uint16_t div)
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{
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static bool first_run = true;
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if (first_run) {
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first_run = false;
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clk_speed(CLK_18MHZ, 1);
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for (uint16_t i = 0; i < 10000; ++i) {
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__asm__("nop");
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}
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/* The speed doesn't need to be changed
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a second time if the user wants 18Mhz. */
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if ((mhz == CLK_18MHZ) && (div <= 1)) {
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return;
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}
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if ((mhz == CLK_36MHZ) && (div == 2)) {
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return;
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}
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}
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if (mhz == CLK_36MHZ) {
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SYSCTL_SYS_DBLF |= BIT0;
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} else {
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SYSCTL_SYS_DBLF &= ~BIT0;
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}
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if (div <= 1) {
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SYSCTL_SYS_CFG_0 |= BIT0;
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} else {
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uint32_t masked_reg32 = SYSCTL_SYS_CFG_0 & CLK_MASK;
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SYSCTL_SYS_CFG_0 = masked_reg32 | (div & ~(CLK_MASK | 0x1));
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}
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}
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/**@}*/
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