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Add some code that does nothing

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Arti Zirk
2021-09-06 10:18:20 +03:00
parent ad7126362e
commit 5f0cf28755
8 changed files with 465 additions and 10 deletions
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143
include/delay.h Normal file
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/*
* This file is part of the HAL project, inline library above libopencm3.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/** @defgroup DELAY_module DELAY module
*
* @brief Spin-waiting blocking API
*
* @ingroup modules
*
* LGPL License Terms @ref lgpl_license
*/
#ifndef HAL_DELAY_H_INCLUDED
#define HAL_DELAY_H_INCLUDED
#include <libopencm3/cm3/common.h>
#include <libopencm3/stm32/rcc.h>
/**@{*/
/*****************************************************************************/
/* API definitions */
/*****************************************************************************/
/*****************************************************************************/
/* API Functions */
/*****************************************************************************/
BEGIN_DECLS
/*---------------------------------------------------------------------------*/
/** @brief Spin-wait delay, spinning specified amount of processor cycles
*
* @note this function can be used for delays of max 2500000 cycles.
* For larger delays, please consider using timers or other waiting techniques.
*
* @param[in] cycles Cycles count need to spent in spin-wait
*/
static void delay_cycles(const int64_t cycles);
/*---------------------------------------------------------------------------*/
/** @brief Spin-wait delay, spinning specified amount of microseconds
*
* @note this function can be used for delays max 25 sec @ 168MHz CPU clock, or
* max 525 sec @ 8MHz CPU clock! For larger delays, please consider using
* timers or other waiting techniques.
*
* @param[in] us Microseconds needed to spin wait.
* @param[in] cpufreq Current CPU frequency in Hz
*/
static void delay_us(uint32_t us);
/*---------------------------------------------------------------------------*/
/** @brief Spin-wait delay, spinning specified amount of microseconds
*
* @note this function can be used for delays max 25 sec @ 168MHz CPU clock, or
* max 525 sec @ 8MHz CPU clock! For larger delays, please consider using
* timers or other waiting techniques.
*
* @param[in] ms Milliseconds needed to spin wait.
* @param[in] cpufreq Current CPU frequency in Hz
*/
static void delay_ms(uint32_t ms);
END_DECLS
/**@}*/
/*****************************************************************************/
/* Architecture dependent implementations */
/*****************************************************************************/
static void _delay_3t(uint32_t cycles) __attribute__((naked));
/* 3 Tcyc per tick, 4Tcyc call/ret, 1Tcyc hidden reg assignment */
static void _delay_3t(uint32_t cycles)
{
asm __volatile__ (
".syntax unified\n"
"1: \n"
" subs %[cyc],#1 \n" /* 1Tck */
" bne 1b \n" /* 2Tck */
" bx lr \n"
".syntax divided\n"
: /* No output */
: [cyc] "r" (cycles)
: /* No memory */
);
}
static inline __attribute__((always_inline)) void delay_cycles(const int64_t cycles)
{
if (cycles <= 0)
return;
switch (cycles % 3) {
default:
case 0: break;
case 1: asm __volatile__ ("nop"); break;
case 2: asm __volatile__ ("nop\nnop"); break;
}
if (cycles > 3)
_delay_3t((uint32_t)(cycles / 3));
else /* same delay as the function call */
asm __volatile__ ("nop\nnop\nnop\nnop\nnop\nnop\n");
}
/* max 25 sec @ 168MHz! */
/* max 525 sec @ 8MHz! */
static inline __attribute__((always_inline)) void delay_us(uint32_t us)
{
if (us == 0)
return;
delay_cycles(us * rcc_ahb_frequency / 1000000 - 6);
}
/* max 25 sec @ 168MHz! */
/* max 525 sec @ 8MHz! */
static inline __attribute__((always_inline)) void delay_ms(uint32_t ms)
{
if (ms == 0)
return;
delay_cycles(ms * rcc_ahb_frequency / 1000 - 6);
}
#endif /* HAL_DELAY_H_INCLUDED */

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include/sx1276.h Normal file
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#include <stdint.h>
#include <stdbool.h>
#define SX1276_RESET_PORT GPIOB
#define SX1276_RESET_PIN GPIO0
#define SX1276_SPI SPI1
#define SX1276_SS_PORT GPIOA
#define SX1276_SS_PIN GPIO4
enum sx1276_reg {
SX1276_REG_FIFO = 0x00, // FIFO read/write access
SX1276_REG_OP_MODE = 0x01, // Operating mode & LoRa (1) / FSK (0) selection
SX1276_REG_FRF_MSB = 0x06, // RF Carrier Frequency, Most Significant Bits
SX1276_REG_FRF_MID = 0x07, // RF Carrier Frequency, Intermediate Bits
SX1276_REG_FRF_LSB = 0x08, // RF Carrier Frequency, Least Significant Bits
SX1276_REG_PA_CONFIG = 0x09, // PA selection and Output Power control
SX1276_REG_PA_RAMP = 0x0a, // Control of PA ramp time, low phase noise PLL
SX1276_REG_OCP = 0x0b, // Over Current Protection control
SX1276_REG_LNA = 0x0c, // LNA settings
SX1276_REG_FIFO_ADDR_PTR = 0x0d, // FIFO SPI pointer
SX1276_REG_FIFO_TX_BASE_ADDR = 0x0e, // Start Tx data
SX1276_REG_FIFO_RX_BASE_ADDR = 0x0f, // Start Rx data
SX1276_REG_FIFO_RX_CURRENT_ADDR = 0x10, // Start address of last packet received
SX1276_REG_IRQ_FLAGS = 0x12, // IRQ flags
SX1276_REG_RX_NB_BYTES = 0x13, // Number of received bytes
SX1276_REG_MODEM_STATUS = 0x18, // Live LoRa modem status
SX1276_REG_PKT_SNR_VALUE = 0x19, // Espimation of last packet SNR
SX1276_REG_PKT_RSSI_VALUE = 0x1a, // RSSI of last packet
SX1276_REG_MODEM_CONFIG_1 = 0x1d, // Modem PHY config 1
SX1276_REG_MODEM_CONFIG_2 = 0x1e, // Modem PHY config 2
SX1276_REG_PREAMBLE_MSB = 0x20, // Size of preamble
SX1276_REG_PREAMBLE_LSB = 0x21, // Size of preamble
SX1276_REG_PAYLOAD_LENGTH = 0x22, // LoRa payload length
SX1276_REG_MODEM_CONFIG_3 = 0x26, // Modem PHY config 3
SX1276_REG_RSSI_WIDEBAND = 0x2c, // Wideband RSSI measurement
SX1276_REG_DETECTION_OPTIMIZE = 0x31, // LoRa detection Optimize for SF6
SX1276_REG_DETECTION_THRESHOLD = 0x37, // LoRa detection threshold for SF6
SX1276_REG_SYNC_WORD = 0x39, // LoRa Sync Word
SX1276_REG_IRQ_FLAGS1 = 0x3e, // (FSK) Status register: PLL Lock state, Timeout, RSSI
SX1276_REG_DIO_MAPPING_1 = 0x40, // Mapping of pins DIO0 to DIO3
SX1276_REG_DIO_MAPPING_2 = 0x41, // Mapping of pins DIO4 and DIO5, ClkOut frequency
SX1276_REG_VERSION = 0x42 // Semtech ID relating the silicon revision (0x12)
};
enum sx1276_mode { // SX1276_REG_OP_MODE values
SX1276_MODE_LONG_RANGE_MODE = 1<<7, // Set to enable LoRa mode
SX1276_MODE_ACCESS_SHARED_REG = 1<<6, // Set to access FSK registers in 0x0D:0x3F while in LoRa mode
SX1276_MODE_LOW_FREQUENCY_MODE = 1<<3, // Set to access Low Frequency Mode registers
// 3 bits of LoRa Modes
SX1276_MODE_SLEEP = 0x00, // FSK and LoRa modes can only be swiched in SLEEP
SX1276_MODE_STDBY = 0x01,
SX1276_MODE_FSTX = 0x02, // Frequency synthesis TX
SX1276_MODE_TX = 0x03,
SX1276_MODE_FSRX = 0x04, // Frequency synthesis RX
SX1276_MODE_RX_CONTINUOUS = 0x05,
SX1276_MODE_RX_SINGLE = 0x06,
SX1276_MODE_CAD = 0x07 // Channel activity detection
};
// PA config
#define PA_BOOST 1<<7
// IRQ masks
#define IRQ_TX_DONE_MASK 0x08
#define IRQ_PAYLOAD_CRC_ERROR_MASK 0x20
#define IRQ_RX_DONE_MASK 0x40
// FSK IRQ FLAGS
#define IRQ_FLAGS1_MODE_READY 1<<7 // Set when the operation mode requested in Mode, is ready
#define FIFO_SIZE 0xff
struct sx1276_state_st {
uint8_t fifo[FIFO_SIZE];
};
uint8_t sx1276_read(uint8_t reg);
uint8_t sx1276_write(uint8_t reg, uint8_t val);
void sx1276_fifo_dump(struct sx1276_state_st *state);
void sx1276_fifo_load(struct sx1276_state_st *state);
void sx1276_fifo_write(uint8_t addr, uint8_t val);
void sx1276_set_frequency(uint64_t frequency);
struct sx1276_state_st *sx1276_init(uint64_t frequency);

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#ifndef DHT_TEST_UTIL_H
#define DHT_TEST_UTIL_H
#include <stdint.h>
void hexdump(char *buf, size_t size, uint32_t width);
#endif //DHT_TEST_UTIL_H