92 lines
4.5 KiB
C
92 lines
4.5 KiB
C
#include <stdint.h>
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#include <stdbool.h>
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#define SX1276_RESET_PORT GPIOB
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#define SX1276_RESET_PIN GPIO0
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#define SX1276_SPI SPI1
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#define SX1276_SS_PORT GPIOA
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#define SX1276_SS_PIN GPIO4
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enum sx1276_reg {
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SX1276_REG_FIFO = 0x00, // FIFO read/write access
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SX1276_REG_OP_MODE = 0x01, // Operating mode & LoRa (1) / FSK (0) selection
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SX1276_REG_FRF_MSB = 0x06, // RF Carrier Frequency, Most Significant Bits
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SX1276_REG_FRF_MID = 0x07, // RF Carrier Frequency, Intermediate Bits
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SX1276_REG_FRF_LSB = 0x08, // RF Carrier Frequency, Least Significant Bits
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SX1276_REG_PA_CONFIG = 0x09, // PA selection and Output Power control
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SX1276_REG_PA_RAMP = 0x0a, // Control of PA ramp time, low phase noise PLL
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SX1276_REG_OCP = 0x0b, // Over Current Protection control
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SX1276_REG_LNA = 0x0c, // LNA settings
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SX1276_REG_FIFO_ADDR_PTR = 0x0d, // FIFO SPI pointer
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SX1276_REG_FIFO_TX_BASE_ADDR = 0x0e, // Start Tx data
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SX1276_REG_FIFO_RX_BASE_ADDR = 0x0f, // Start Rx data
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SX1276_REG_FIFO_RX_CURRENT_ADDR = 0x10, // Start address of last packet received
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SX1276_REG_IRQ_FLAGS = 0x12, // IRQ flags
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SX1276_REG_RX_NB_BYTES = 0x13, // Number of received bytes
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SX1276_REG_MODEM_STATUS = 0x18, // Live LoRa modem status
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SX1276_REG_PKT_SNR_VALUE = 0x19, // Espimation of last packet SNR
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SX1276_REG_PKT_RSSI_VALUE = 0x1a, // RSSI of last packet
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SX1276_REG_MODEM_CONFIG_1 = 0x1d, // Modem PHY config 1
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SX1276_REG_MODEM_CONFIG_2 = 0x1e, // Modem PHY config 2
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SX1276_REG_PREAMBLE_MSB = 0x20, // Size of preamble
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SX1276_REG_PREAMBLE_LSB = 0x21, // Size of preamble
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SX1276_REG_PAYLOAD_LENGTH = 0x22, // LoRa payload length
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SX1276_REG_FIFO_RX_BYTE_PTR = 0x25, // Current value of RX databuffer pointer (written by Lora receiver)
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SX1276_REG_MODEM_CONFIG_3 = 0x26, // Modem PHY config 3
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SX1276_REG_RSSI_WIDEBAND = 0x2c, // Wideband RSSI measurement
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SX1276_REG_DETECTION_OPTIMIZE = 0x31, // LoRa detection Optimize for SF6
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SX1276_REG_DETECTION_THRESHOLD = 0x37, // LoRa detection threshold for SF6
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SX1276_REG_SYNC_WORD = 0x39, // LoRa Sync Word
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SX1276_REG_IRQ_FLAGS1 = 0x3e, // (FSK) Status register: PLL Lock state, Timeout, RSSI
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SX1276_REG_DIO_MAPPING_1 = 0x40, // Mapping of pins DIO0 to DIO3
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SX1276_REG_DIO_MAPPING_2 = 0x41, // Mapping of pins DIO4 and DIO5, ClkOut frequency
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SX1276_REG_VERSION = 0x42 // Semtech ID relating the silicon revision (0x12)
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};
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enum sx1276_mode { // SX1276_REG_OP_MODE values
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SX1276_MODE_LONG_RANGE_MODE = 1<<7, // Set to enable LoRa mode
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SX1276_MODE_ACCESS_SHARED_REG = 1<<6, // Set to access FSK registers in 0x0D:0x3F while in LoRa mode
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SX1276_MODE_LOW_FREQUENCY_MODE = 1<<3, // Set to access Low Frequency Mode registers
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// 3 bits of LoRa Modes
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SX1276_MODE_SLEEP = 0x00, // FSK and LoRa modes can only be swiched in SLEEP
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SX1276_MODE_STDBY = 0x01,
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SX1276_MODE_FSTX = 0x02, // Frequency synthesis TX
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SX1276_MODE_TX = 0x03,
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SX1276_MODE_FSRX = 0x04, // Frequency synthesis RX
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SX1276_MODE_RX_CONTINUOUS = 0x05,
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SX1276_MODE_RX_SINGLE = 0x06,
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SX1276_MODE_CAD = 0x07 // Channel activity detection
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};
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// PA config
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#define PA_BOOST 1<<7
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// LORA IRQ masks
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enum sx1276_lora_irq {
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SX1267_LORA_IRQ_RX_TIMEOUT = 1<<7,
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SX1267_LORA_IRQ_RX_DONE = 1<<6,
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SX1267_LORA_IRQ_PAYLOAD_CRC_ERR = 1<<5,
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SX1267_LORA_IRQ_VALID_HEADER = 1<<4,
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SX1267_LORA_IRQ_TX_DONE = 1<<3,
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SX1267_LORA_IRQ_CAD_DONE = 1<<2,
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SX1267_LORA_IRQ_FHSS_CHANGE_CH = 1<<1,
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SX1267_LORA_IRQ_CAD_DETECTED = 1<<0,
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};
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// FSK IRQ FLAGS
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#define IRQ_FLAGS1_MODE_READY 1<<7 // Set when the operation mode requested in Mode, is ready
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#define FIFO_SIZE 0xff
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struct sx1276_state_st {
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uint8_t fifo[FIFO_SIZE];
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};
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uint8_t sx1276_read(uint8_t reg);
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uint8_t sx1276_write(uint8_t reg, uint8_t val);
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void sx1276_fifo_dump(struct sx1276_state_st *state);
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void sx1276_fifo_load(struct sx1276_state_st *state);
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void sx1276_fifo_write(uint8_t addr, uint8_t val);
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void sx1276_set_frequency(uint64_t frequency);
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struct sx1276_state_st *sx1276_init(uint64_t frequency);
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