118 lines
3.7 KiB
C
118 lines
3.7 KiB
C
#include <libopencm3/stm32/gpio.h>
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#include <libopencm3/stm32/spi.h>
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#include <SEGGER_RTT.h>
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#include "delay.h"
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#include "util.h"
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#include "sx1276.h"
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static uint8_t sx1276_spi_transaction(uint8_t reg, uint8_t val) {
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uint8_t ret;
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gpio_clear(SX1276_SS_PORT, SX1276_SS_PIN);
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spi_send(SX1276_SPI, reg);
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spi_read(SX1276_SPI);
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spi_send(SX1276_SPI, val);
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ret = spi_read(SX1276_SPI);
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gpio_set(SX1276_SS_PORT, SX1276_SS_PIN);
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return ret;
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}
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uint8_t sx1276_read(uint8_t reg) {
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reg &= 0x7f; // clear upper bit to make it read request
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return sx1276_spi_transaction(reg, 0x00);
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}
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uint8_t sx1276_write(uint8_t reg, uint8_t val) {
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reg |= 0x80; // set upper bit to make it write request
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return sx1276_spi_transaction(reg, val);
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}
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void sx1276_fifo_dump(struct sx1276_state_st *state) {
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sx1276_write(SX1276_REG_FIFO_ADDR_PTR, 0x00);
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gpio_clear(SX1276_SS_PORT, SX1276_SS_PIN);
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spi_send(SX1276_SPI, SX1276_REG_FIFO & 0x7f); // read
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spi_read(SX1276_SPI);
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for (int i=0; i < FIFO_SIZE; i++){
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spi_send(SX1276_SPI, 0x00);
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int val = spi_read(SX1276_SPI);
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state->fifo[i] = val;
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}
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gpio_set(GPIOA, GPIO4);
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}
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void sx1276_fifo_load(struct sx1276_state_st *state) {
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sx1276_write(SX1276_REG_FIFO_ADDR_PTR, 0x00);
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gpio_clear(SX1276_SS_PORT, SX1276_SS_PIN);
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spi_send(SX1276_SPI, SX1276_REG_FIFO | 0x80); // write
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spi_read(SX1276_SPI);
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for (int i=0; i < FIFO_SIZE; i++){
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spi_send(SX1276_SPI, state->fifo[i]);
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spi_read(SX1276_SPI);
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}
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gpio_set(GPIOA, GPIO4);
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}
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void sx1276_fifo_write(uint8_t addr, uint8_t val) {
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sx1276_write(SX1276_REG_FIFO_ADDR_PTR, addr);
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sx1276_write(SX1276_REG_FIFO, val);
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}
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void sx1276_set_frequency(uint64_t frequency) {
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uint64_t frf = ((uint64_t)frequency << 19) / 32000000;
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sx1276_write(SX1276_REG_FRF_MSB, (uint8_t)(frf >> 16));
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sx1276_write(SX1276_REG_FRF_MID, (uint8_t)(frf >> 8));
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sx1276_write(SX1276_REG_FRF_LSB, (uint8_t)(frf >> 0));
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}
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struct sx1276_state_st *sx1276_init(uint64_t frequency) {
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struct sx1276_state_st *sx1276_state = (struct sx1276_state_st*) malloc(sizeof(struct sx1276_state_st));
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if (sx1276_state == NULL) {
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return NULL;
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}
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SEGGER_RTT_printf(0, "SX1276: Reset\n");
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gpio_clear(GPIOB, GPIO0);
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delay_us(100);
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gpio_set(GPIOB, GPIO0);
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delay_ms(5);
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uint8_t ret = sx1276_read(SX1276_REG_VERSION);
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// if (ret != 0x12) {
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// SEGGER_RTT_printf(0, "Invalid Chip Version, got: 0x%02x, expected: 0x12\n", ret);
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// //free(sx1276_state);
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// //return NULL;
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// }
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SEGGER_RTT_printf(0, "Chip Version: 0x%02X\n", ret);
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uint8_t set = SX1276_MODE_LONG_RANGE_MODE | SX1276_MODE_SLEEP;
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ret = sx1276_write(SX1276_REG_OP_MODE, set);
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SEGGER_RTT_printf(0, "Going to LoRa SLEEP from: 0x%02X, to: 0x%02X\n",
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ret, set);
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sx1276_set_frequency(frequency);
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sx1276_write(SX1276_REG_FIFO_TX_BASE_ADDR, 0);
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sx1276_write(SX1276_REG_FIFO_RX_BASE_ADDR, 0);
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sx1276_write(SX1276_REG_LNA, 0b11000000); // minimum strenght
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sx1276_write(SX1276_REG_PA_CONFIG, 1<<7); // minimum 2dBm
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// Bw 7 125khz; CodingRate 1 4/5; implicit header mode
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sx1276_write(SX1276_REG_MODEM_CONFIG_1, (7 << 4) | (1 << 1) | 1);
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// SpreadingFactor 7 128 chips
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sx1276_write(SX1276_REG_MODEM_CONFIG_2, (7 << 4));
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set = SX1276_MODE_LONG_RANGE_MODE | SX1276_MODE_STDBY;
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ret = sx1276_write(SX1276_REG_OP_MODE, set);
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SEGGER_RTT_printf(0, "Going to LoRa STDBY from: 0x%02X, to: 0x%02x\n",
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ret, set);
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// We need to wait ~250us for TS_OSC to startup before we can access FIFO and some other things
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delay_us(250);
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return sx1276_state;
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};
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