subrepo: subdir: "libopencm3" merged: "88e91c9a7cce" upstream: origin: "https://github.com/libopencm3/libopencm3.git" branch: "master" commit: "88e91c9a7cce" git-subrepo: version: "0.4.3" origin: "???" commit: "???"
124 lines
4.0 KiB
C
124 lines
4.0 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2015 Daniele Lacamera <root at danielinux dot net>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LM3S_USART_H
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#define LM3S_USART_H
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#include <libopencm3/cm3/common.h>
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#define USART0_BASE 0x4000C000
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#define USART1_BASE 0x4000D000
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#define USART2_BASE 0x4000E000
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/* --- Universal Synchronous Asynchronous Receiver Transmitter (USART) */
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#define USART_DR(x) MMIO32((x) + 0x0000)
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#define USART_IR(x) MMIO32((x) + 0x0004)
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#define USART_FR(x) MMIO32((x) + 0x0018)
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#define USART_ILPR(x) MMIO32((x) + 0x0020)
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#define USART_IBRD(x) MMIO32((x) + 0x0024)
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#define USART_FBRD(x) MMIO32((x) + 0x0028)
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#define USART_LCRH(x) MMIO32((x) + 0x002c)
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#define USART_CTL(x) MMIO32((x) + 0x0030)
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#define USART_IFLS(x) MMIO32((x) + 0x0034)
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#define USART_IM(x) MMIO32((x) + 0x0038)
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#define USART_RIS(x) MMIO32((x) + 0x003c)
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#define USART_MIS(x) MMIO32((x) + 0x0040)
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#define USART_IC(x) MMIO32((x) + 0x0044)
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/* USART Data Register (USART_DR) */
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/* Bits [31:12] - Reserved */
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#define USART_DR_OE (0x01 << 11)
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#define USART_DR_BE (0x01 << 10)
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#define USART_DR_PE (0x01 << 9)
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#define USART_DR_FE (0x01 << 8)
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/* USART Flags Register (USART_FR) */
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/* Bits [31:8] - Reserved */
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#define USART_FR_TXFE (0x01 << 7)
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#define USART_FR_RXFF (0x01 << 6)
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#define USART_FR_TXFF (0x01 << 5)
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#define USART_FR_RXFE (0x01 << 4)
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#define USART_FR_BUSY (0x01 << 3)
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/* Bits [2:0] - Reserved */
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/* USART Interrupt Mask Register (USART_IM) */
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/* Bits [31:11] - Reserved */
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#define USART_IM_OE (0x01 << 10)
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#define USART_IM_BE (0x01 << 9)
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#define USART_IM_PE (0x01 << 8)
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#define USART_IM_FE (0x01 << 7)
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#define USART_IM_RT (0x01 << 6)
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#define USART_IM_TX (0x01 << 5)
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#define USART_IM_RX (0x01 << 4)
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/* Bits [3:0] - Reserved */
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/* USART Interrupt Clear Register (USART_IC) */
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/* Bits [31:11] - Reserved */
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#define USART_IC_OE (0x01 << 10)
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#define USART_IC_BE (0x01 << 9)
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#define USART_IC_PE (0x01 << 8)
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#define USART_IC_FE (0x01 << 7)
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#define USART_IC_RT (0x01 << 6)
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#define USART_IC_TX (0x01 << 5)
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#define USART_IC_RX (0x01 << 4)
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/* Bits [3:0] - Reserved */
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enum usart_stopbits {
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USART_STOPBITS_1,
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USART_STOPBITS_1_5,
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USART_STOPBITS_2,
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};
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enum usart_parity {
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USART_PARITY_NONE,
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USART_PARITY_ODD,
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USART_PARITY_EVEN,
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};
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enum usart_mode {
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USART_MODE_DISABLED,
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USART_MODE_RX,
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USART_MODE_TX,
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USART_MODE_TX_RX,
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};
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enum usart_flowcontrol {
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USART_FLOWCONTROL_NONE,
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USART_FLOWCONTROL_RTS_CTS,
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};
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void usart_send(uint32_t usart, uint16_t data);
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uint16_t usart_recv(uint32_t usart);
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bool usart_is_send_ready(uint32_t usart);
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bool usart_is_recv_ready(uint32_t usart);
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void usart_send_blocking(uint32_t usart, uint16_t data);
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uint16_t usart_recv_blocking(uint32_t usart);
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void usart_enable_rx_interrupt(uint32_t usart);
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void usart_disable_rx_interrupt(uint32_t usart);
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void usart_clear_rx_interrupt(uint32_t usart);
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void usart_enable_tx_interrupt(uint32_t usart);
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void usart_disable_tx_interrupt(uint32_t usart);
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void usart_clear_tx_interrupt(uint32_t usart);
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bool usart_get_interrupt_source(uint32_t usart, uint32_t flag);
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#endif
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