Arti Zirk
2de3a91b0a
subrepo: subdir: "libopencm3" merged: "88e91c9a7cce" upstream: origin: "https://github.com/libopencm3/libopencm3.git" branch: "master" commit: "88e91c9a7cce" git-subrepo: version: "0.4.3" origin: "???" commit: "???"
419 lines
11 KiB
C
419 lines
11 KiB
C
/** @defgroup rtc_file RTC peripheral API
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*
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* @ingroup peripheral_apis
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*
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* @brief <b>libopencm3 STM32F1xx RTC</b>
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*
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* @author @htmlonly © @endhtmlonly 2010 Uwe Hermann <uwe@hermann-uwe.de>
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* @author @htmlonly © @endhtmlonly 2010 Lord James <lordjames@y7mail.com>
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*
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* @version 1.0.0
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*
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* @date 4 March 2013
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*
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* The Real Time Clock peripheral consists of a set of 16 bit control, status,
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* prescaler, counter and alarm registers. Before the latter three can be
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* written the RTC must be placed in configuration mode by a call to
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* @ref rtc_enter_config_mode(). The functions below handle this implictly.
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*
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* The RTC is completely reset by performing a Backup Domain reset. Note
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* that this can affect unrelated user data contained in the Backup Domain
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* registers. Other forms of reset will not affect the RTC registers as they
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* are contained within the backup domain.
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*
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* The RTC clock source to be used is selected by calling
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* @ref rcc_set_rtc_clock_source().
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*
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* The LSE clock source normally comes from a 32.768kHz external crystal
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* This clock is in the backup domain and so continues to run when only the
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* V_BAT supply is present. A prescaler value of 7FFF will give a 1 second
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* count quantum.
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*
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* The LSI clock source is a low accuracy internal clock of about 40kHz
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* frequency, and the HSE clock source is the external high speed clock
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* divided by 128.
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*
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* Initial configuration of the RTC consists of:
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*
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* @li perform a Backup Domain reset if appropriate;
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* @li select the clock to be used;
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* @li set the prescaler, counter and configuration values;
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* @li enable the RTC.
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*
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* @note reading the RTC registers may result in a corrupted value being
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* returned in certain cases. Refer to the STM32F1xx Reference Manual.
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2010 Lord James <lordjames@y7mail.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#include <libopencm3/stm32/rcc.h>
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#include <libopencm3/stm32/rtc.h>
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#include <libopencm3/stm32/pwr.h>
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/*---------------------------------------------------------------------------*/
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/** @brief RTC Set Operational from the Off state.
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Power up the backup domain clocks, enable write access to the backup domain,
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select the clock source, clear the RTC registers and enable the RTC.
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@param[in] clock_source ::rcc_osc. RTC clock source. Only the values HSE, LSE
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and LSI are permitted.
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*/
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void rtc_awake_from_off(enum rcc_osc clock_source)
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{
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uint32_t reg32;
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/* Enable power and backup interface clocks. */
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rcc_periph_clock_enable(RCC_PWR);
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rcc_periph_clock_enable(RCC_BKP);
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/* Enable access to the backup registers and the RTC. */
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pwr_disable_backup_domain_write_protect();
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/* Set the clock source */
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rcc_set_rtc_clock_source(clock_source);
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/* Clear the RTC Control Register */
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RTC_CRH = 0;
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RTC_CRL = 0;
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/* Enable the RTC. */
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rcc_enable_rtc_clock();
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/* Clear the Registers */
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rtc_enter_config_mode();
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RTC_PRLH = 0;
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RTC_PRLL = 0;
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RTC_CNTH = 0;
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RTC_CNTL = 0;
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RTC_ALRH = 0xFFFF;
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RTC_ALRL = 0xFFFF;
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rtc_exit_config_mode();
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/* Wait for the RSF bit in RTC_CRL to be set by hardware. */
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RTC_CRL &= ~RTC_CRL_RSF;
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while ((reg32 = (RTC_CRL & RTC_CRL_RSF)) == 0);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RTC Enter Configuration Mode.
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Prime the RTC for configuration changes by giving access to the prescaler,
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and counter and alarm registers.
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*/
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void rtc_enter_config_mode(void)
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{
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uint32_t reg32;
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/* Wait until the RTOFF bit is 1 (no RTC register writes ongoing). */
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while ((reg32 = (RTC_CRL & RTC_CRL_RTOFF)) == 0);
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/* Enter configuration mode. */
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RTC_CRL |= RTC_CRL_CNF;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RTC Leave Configuration Mode.
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Revert the RTC to operational state.
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*/
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void rtc_exit_config_mode(void)
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{
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uint32_t reg32;
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/* Exit configuration mode. */
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RTC_CRL &= ~RTC_CRL_CNF;
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/* Wait until the RTOFF bit is 1 (our RTC register write finished). */
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while ((reg32 = (RTC_CRL & RTC_CRL_RTOFF)) == 0);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RTC Set the Alarm Time.
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@param[in] alarm_time uint32_t. time at which the alarm event is triggered.
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*/
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void rtc_set_alarm_time(uint32_t alarm_time)
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{
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rtc_enter_config_mode();
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RTC_ALRL = (alarm_time & 0x0000ffff);
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RTC_ALRH = (alarm_time & 0xffff0000) >> 16;
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rtc_exit_config_mode();
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RTC Enable the Alarm.
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*/
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void rtc_enable_alarm(void)
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{
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rtc_enter_config_mode();
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RTC_CRH |= RTC_CRH_ALRIE;
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rtc_exit_config_mode();
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RTC Disable the Alarm.
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*/
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void rtc_disable_alarm(void)
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{
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rtc_enter_config_mode();
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RTC_CRH &= ~RTC_CRH_ALRIE;
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rtc_exit_config_mode();
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RTC Set the prescaler Value
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@param[in] prescale_val uint32_t. 20 bit prescale divider.
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*/
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void rtc_set_prescale_val(uint32_t prescale_val)
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{
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rtc_enter_config_mode();
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RTC_PRLL = prescale_val & 0x0000ffff; /* PRL[15:0] */
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RTC_PRLH = (prescale_val & 0x000f0000) >> 16; /* PRL[19:16] */
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rtc_exit_config_mode();
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RTC return the Counter Value
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@returns uint32_t: the 32 bit counter value.
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*/
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uint32_t rtc_get_counter_val(void)
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{
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return (RTC_CNTH << 16) | RTC_CNTL;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RTC return the prescaler Value
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@returns uint32_t: the 20 bit prescale divider.
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*/
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uint32_t rtc_get_prescale_div_val(void)
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{
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return (RTC_DIVH << 16) | RTC_DIVL;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RTC return the Alarm Value
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@returns uint32_t: the 32 bit alarm value.
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*/
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uint32_t rtc_get_alarm_val(void)
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{
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return (RTC_ALRH << 16) | RTC_ALRL;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RTC set the Counter
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@param[in] counter_val 32 bit time setting for the counter.
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*/
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void rtc_set_counter_val(uint32_t counter_val)
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{
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rtc_enter_config_mode();
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RTC_CNTH = (counter_val & 0xffff0000) >> 16; /* CNT[31:16] */
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RTC_CNTL = counter_val & 0x0000ffff; /* CNT[15:0] */
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rtc_exit_config_mode();
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RTC Enable Interrupt
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@param[in] flag_val ::rtcflag_t: The flag to enable.
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*/
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void rtc_interrupt_enable(rtcflag_t flag_val)
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{
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rtc_enter_config_mode();
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/* Set the correct interrupt enable. */
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switch (flag_val) {
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case RTC_SEC:
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RTC_CRH |= RTC_CRH_SECIE;
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break;
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case RTC_ALR:
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RTC_CRH |= RTC_CRH_ALRIE;
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break;
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case RTC_OW:
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RTC_CRH |= RTC_CRH_OWIE;
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break;
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}
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rtc_exit_config_mode();
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RTC Disable Interrupt
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@param[in] flag_val ::rtcflag_t: The flag to disable.
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*/
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void rtc_interrupt_disable(rtcflag_t flag_val)
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{
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rtc_enter_config_mode();
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/* Disable the correct interrupt enable. */
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switch (flag_val) {
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case RTC_SEC:
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RTC_CRH &= ~RTC_CRH_SECIE;
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break;
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case RTC_ALR:
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RTC_CRH &= ~RTC_CRH_ALRIE;
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break;
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case RTC_OW:
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RTC_CRH &= ~RTC_CRH_OWIE;
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break;
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}
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rtc_exit_config_mode();
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RTC Clear an Interrupt Flag
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@param[in] flag_val ::rtcflag_t: The flag to clear.
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*/
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void rtc_clear_flag(rtcflag_t flag_val)
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{
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/* Configuration mode not needed. */
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/* Clear the correct flag. */
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switch (flag_val) {
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case RTC_SEC:
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RTC_CRL &= ~RTC_CRL_SECF;
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break;
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case RTC_ALR:
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RTC_CRL &= ~RTC_CRL_ALRF;
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break;
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case RTC_OW:
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RTC_CRL &= ~RTC_CRL_OWF;
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break;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RTC Return a Flag Setting
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@param[in] flag_val ::rtcflag_t: The flag to check.
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@returns uint32_t: a nonzero value if the flag is set, zero otherwise.
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*/
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uint32_t rtc_check_flag(rtcflag_t flag_val)
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{
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uint32_t reg32;
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/* Read correct flag. */
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switch (flag_val) {
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case RTC_SEC:
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reg32 = RTC_CRL & RTC_CRL_SECF;
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break;
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case RTC_ALR:
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reg32 = RTC_CRL & RTC_CRL_ALRF;
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break;
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case RTC_OW:
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reg32 = RTC_CRL & RTC_CRL_OWF;
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break;
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default:
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reg32 = 0;
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break;
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}
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return reg32;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RTC Start RTC after Standby Mode.
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Enable the backup domain clocks, enable write access to the backup
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domain and the RTC, and synchronise the RTC register access.
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*/
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void rtc_awake_from_standby(void)
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{
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uint32_t reg32;
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/* Enable power and backup interface clocks. */
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rcc_periph_clock_enable(RCC_PWR);
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rcc_periph_clock_enable(RCC_BKP);
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/* Enable access to the backup registers and the RTC. */
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pwr_disable_backup_domain_write_protect();
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/* Wait for the RSF bit in RTC_CRL to be set by hardware. */
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RTC_CRL &= ~RTC_CRL_RSF;
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while ((reg32 = (RTC_CRL & RTC_CRL_RSF)) == 0);
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/* Wait for the last write operation to finish. */
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/* TODO: Necessary? */
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while ((reg32 = (RTC_CRL & RTC_CRL_RTOFF)) == 0);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief RTC Configuration on Wakeup
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Enable the backup domain clocks and write access to the backup domain.
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If the RTC has not been enabled, set the clock source and prescaler value.
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The parameters are not used if the RTC has already been enabled.
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@param[in] clock_source ::rcc_osc. RTC clock source. Only HSE, LSE
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and LSI are permitted.
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@param[in] prescale_val uint32_t. 20 bit prescale divider.
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*/
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void rtc_auto_awake(enum rcc_osc clock_source, uint32_t prescale_val)
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{
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uint32_t reg32;
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/* Enable power and backup interface clocks. */
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rcc_periph_clock_enable(RCC_PWR);
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rcc_periph_clock_enable(RCC_BKP);
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reg32 = rcc_rtc_clock_enabled_flag();
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if (reg32 != 0) {
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rtc_awake_from_standby();
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} else {
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rtc_awake_from_off(clock_source);
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rtc_set_prescale_val(prescale_val);
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}
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}
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/**@}*/
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