Arti Zirk
2de3a91b0a
subrepo: subdir: "libopencm3" merged: "88e91c9a7cce" upstream: origin: "https://github.com/libopencm3/libopencm3.git" branch: "master" commit: "88e91c9a7cce" git-subrepo: version: "0.4.3" origin: "???" commit: "???"
187 lines
6.9 KiB
C
187 lines
6.9 KiB
C
/** @addtogroup fdcan_file FDCAN peripheral API
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*
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* @ingroup peripheral_apis
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*
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* @brief <b>libopencm3 STM32 FDCAN</b>
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*
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* @version 1.0.0
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*
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* @author @htmlonly © @endhtmlonly 2021 Eduard Drusa <ventyl86 at netkosice dot sk>
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*
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* Devices can have up to three FDCAN peripherals residing in one FDCAN block. The peripherals
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* support both CAN 2.0 A and B standard and Bosch FDCAN standard. FDCAN frame format and
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* bitrate switching is supported. The peripheral has several filters for incoming messages that
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* can be distributed between two FIFOs and three transmit mailboxes. For transmitted messages
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* it is possible to opt for event notification once message is transmitted.
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2021 Eduard Drusa <ventyl86 at netkosice dot sk>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/stm32/fdcan.h>
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#include <libopencm3/stm32/rcc.h>
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#include <stddef.h>
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/* --- FD-CAN functions ----------------------------------------------------- */
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/** @ingroup fdcan_file */
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/**@{
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* */
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/** Returns actual size of FIFO entry in FIFO for given CAN port and FIFO.
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*
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* Obtains value of FIFO entry length. For G4 it returns constant value as
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* G4 has FIFO element length hardcoded.
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* @param [in] canport FDCAN block base address. See @ref fdcan_block. Unused.
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* @param [in] fifo_id ID of FIFO whole length is queried. Unused.
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* @returns Length of FIFO entry length covering frame header and frame payload.
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*/
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unsigned fdcan_get_fifo_element_size(uint32_t canport, unsigned fifo_id)
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{
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/* Silences compiler. Variables are present for API compatibility
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* with STM32H7
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*/
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(void) (canport);
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(void) (fifo_id);
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return sizeof(struct fdcan_rx_fifo_element);
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}
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/** Returns actual size of transmit entry in transmit queue/FIFO for given CAN port.
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*
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* Obtains value of entry length in transmit queue/FIFO. For G4 it returns constant value
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* as G4 has transmit buffer entries of fixed length.
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*
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* @param [in] canport FDCAN block base address. See @ref fdcan_block. Unused.
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* @returns Length of FIFO entry length covering frame header and frame payload.
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*/
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unsigned fdcan_get_txbuf_element_size(uint32_t canport)
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{
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/* Silences compiler. Variables are present for API compatibility
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* with STM32H7
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*/
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(void) (canport);
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return sizeof(struct fdcan_tx_buffer_element);
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}
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/** Configure amount of filters and initialize filtering block.
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*
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* This function allows to configure global amount of filters present.
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* FDCAN block will only ever check as many filters as this function configures.
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* Function will also clear all filter blocks to zero values. This function
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* can be only called after @ref fdcan_init has already been called and
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* @ref fdcan_start has not been called yet as registers holding filter
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* count are write-protected unless FDCAN block is in INIT mode. It is possible
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* to reconfigure filters (@ref fdcan_set_std_filter and @ref fdcan_set_ext_filter)
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* after FDCAN block has already been started.
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*
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* @param [in] canport FDCAN block base address. See @ref fdcan_block.
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* @param [in] std_filt requested amount of standard ID filter rules (0-28)
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* @param [in] ext_filt requested amount of extended ID filter rules (0-8)
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*/
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void fdcan_init_filter(uint32_t canport, uint8_t std_filt, uint8_t ext_filt)
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{
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struct fdcan_standard_filter *lfssa = fdcan_get_flssa_addr(canport);
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struct fdcan_extended_filter *lfesa = fdcan_get_flesa_addr(canport);
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/* Only perform initialization of message RAM if there are
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* any filters required
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*/
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if (std_filt > 0) {
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FDCAN_RXGFC(canport) =
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(FDCAN_RXGFC(canport) & ~(FDCAN_RXGFC_LSS_MASK << FDCAN_RXGFC_LSS_SHIFT))
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| (std_filt << FDCAN_RXGFC_LSS_SHIFT);
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for (int q = 0; q < FDCAN_SFT_MAX_NR; ++q) {
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lfssa[q].type_id1_conf_id2 = 0;
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}
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} else {
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/* Reset filter count to zero */
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FDCAN_RXGFC(canport) =
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(FDCAN_RXGFC(canport) & ~(FDCAN_RXGFC_LSS_MASK << FDCAN_RXGFC_LSS_SHIFT));
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}
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if (ext_filt > 0) {
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FDCAN_RXGFC(canport) =
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(FDCAN_RXGFC(canport) & ~(FDCAN_RXGFC_LSE_MASK << FDCAN_RXGFC_LSE_SHIFT))
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| (ext_filt << FDCAN_RXGFC_LSE_SHIFT);
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for (int q = 0; q < FDCAN_EFT_MAX_NR; ++q) {
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lfesa[q].conf_id1 = 0;
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lfesa[q].type_id2 = 0;
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}
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} else {
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/* Reset filter count to zero */
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FDCAN_RXGFC(canport) =
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(FDCAN_RXGFC(canport) & ~(FDCAN_RXGFC_LSE_MASK << FDCAN_RXGFC_LSE_SHIFT));
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}
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}
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/** Enable FDCAN operation after FDCAN block has been set up.
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*
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* This function will disable FDCAN configuration effectively
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* allowing FDCAN to sync up with the bus. After calling this function
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* it is not possible to reconfigure amount of filter rules, yet
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* it is possible to configure rules themselves. FDCAN block operation
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* state can be checked using @ref fdcan_get_init_state.
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*
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* @param [in] canport FDCAN block base address. See @ref fdcan_block.
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* @param [in] timeout Amount of empty busy loops, which routine should wait for FDCAN
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* confirming that it left INIT mode. If set to 0, function will return
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* immediately.
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* @returns Operation error status. See @ref fdcan_error.
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* @note If this function returns with timeout, it usually means that
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* FDCAN_clk is not set up properly.
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*/
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int fdcan_start(uint32_t canport, uint32_t timeout)
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{
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/* Error here usually means, that FDCAN_clk is not set up
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* correctly, or at all. This usually can't be seen above
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* when INIT is set to 1, because default value for INIT is
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* 1 as long as one has FDCAN_pclk configured properly.
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**/
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if (fdcan_cccr_init_cfg(canport, false, timeout) != 0) {
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return FDCAN_E_TIMEOUT;
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}
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return FDCAN_E_OK;
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}
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/** Configure FDCAN FIFO lock mode
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*
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* This function allows to choose between locked and overewrite mode of FIFOs. In locked mode,
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* whenever FIFO is full and new frame arrives, which would normally been stored into given
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* FIFO, then frame is dropped. If overwrite mode is active, then most recent message in FIFO
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* is rewritten by frame just received.
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* @param [in] canport FDCAN block base address. See @ref fdcan_block.
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* @param [in] locked true activates locked mode, false activates overwrite mode
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*/
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void fdcan_set_fifo_locked_mode(uint32_t canport, bool locked)
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{
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if (locked) {
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FDCAN_RXGFC(canport) &= ~(FDCAN_RXGFC_F1OM | FDCAN_RXGFC_F0OM);
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} else {
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FDCAN_RXGFC(canport) |= FDCAN_RXGFC_F1OM | FDCAN_RXGFC_F0OM;
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}
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}
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/** @} */
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