Arti Zirk
2de3a91b0a
subrepo: subdir: "libopencm3" merged: "88e91c9a7cce" upstream: origin: "https://github.com/libopencm3/libopencm3.git" branch: "master" commit: "88e91c9a7cce" git-subrepo: version: "0.4.3" origin: "???" commit: "???"
105 lines
3.2 KiB
C
105 lines
3.2 KiB
C
/** @defgroup CM3_dwt_file DWT
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*
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* @ingroup CM3_files
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*
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* @brief <b>libopencm3 Cortex-M Data Watchpoint and Trace unit</b>
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*
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* The DWT provides
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* * Comparators, that support
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* * watch points
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* * data tracing
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* * signalling to ETM
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* * PC value tracing
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* * cycle count matching
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* * extra PC sampling
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* * Sampling as a result of a clock count
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* * external access for sampling
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* * exception trace
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* * performance profiling counters.
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*
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* Which of these features are available is unfortunately implementation defined.
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*
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* @see ARMv7m Architecture Reference Manual (Chapter ARMv7-M Debug)
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*
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* LGPL License Terms @ref lgpl_license
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* @{
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/cm3/scs.h>
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#include <libopencm3/cm3/dwt.h>
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/*---------------------------------------------------------------------------*/
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/** @brief DebugTrace Enable the CPU cycle counter
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*
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* This function will try to enable the CPU cycle counter that is intended for
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* benchmarking performance of the code. If function fails, the cycle counter
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* isn't available on this architecture.
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*
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* @return true, if success
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*/
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bool dwt_enable_cycle_counter(void)
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{
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#if defined(__ARM_ARCH_6M__)
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return false; /* Not supported on ARMv6M */
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#endif /* defined(__ARM_ARCH_6M__) */
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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/* Note TRCENA is for 7M and above*/
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SCS_DEMCR |= SCS_DEMCR_TRCENA;
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if (DWT_CTRL & DWT_CTRL_NOCYCCNT) {
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return false; /* Not supported in implementation */
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}
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DWT_CYCCNT = 0;
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DWT_CTRL |= DWT_CTRL_CYCCNTENA;
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return true;
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#endif /* defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) */
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/* not supported on other architectures */
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return false;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DebugTrace Read the CPU cycle counter
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*
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* This function reads the core cycle counter if it is enabled. It is the
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* fastest clock running on the system.
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*
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* @note The CPU cycle counter must be enabled by @ref dwt_enable_cycle_counter
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*
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* @returns 0 if cycle counter is not supported or enabled, the cycle counter
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* value otherwise.
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*/
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uint32_t dwt_read_cycle_counter(void)
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{
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#if defined(__ARM_ARCH_6M__)
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return 0; /* Not supported on ARMv6M */
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#endif /* defined(__ARM_ARCH_6M__) */
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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if (DWT_CTRL & DWT_CTRL_CYCCNTENA) {
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return DWT_CYCCNT;
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} else {
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return 0; /* not supported or enabled */
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}
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#endif /* defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) */
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}
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/**@}*/ |