Arti Zirk
2de3a91b0a
subrepo: subdir: "libopencm3" merged: "88e91c9a7cce" upstream: origin: "https://github.com/libopencm3/libopencm3.git" branch: "master" commit: "88e91c9a7cce" git-subrepo: version: "0.4.3" origin: "???" commit: "???"
811 lines
28 KiB
C
811 lines
28 KiB
C
/** @defgroup dma_file DMA peripheral API
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@ingroup peripheral_apis
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@brief DMA library for the multi stream controller found in f2/f4/f7 parts.
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@author @htmlonly © @endhtmlonly 2012
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Ken Sarkies <ksarkies@internode.on.net>
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This library supports the DMA Control System in the STM32F2 and STM32F4
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series of ARM Cortex Microcontrollers by ST Microelectronics.
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Up to two DMA controllers are supported each with 8 streams, and each stream
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having up to 8 channels hardware dedicated to various peripheral DMA signals.
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DMA transfers can be configured to occur between peripheral and memory in
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either direction, and memory to memory. Peripheral to peripheral transfer
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is not supported. Circular mode transfers are also supported in transfers
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involving a peripheral. An arbiter is provided to resolve priority DMA
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requests. Transfers can be made with 8, 16 or 32 bit words.
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Each stream has access to a 4 word deep FIFO and can use double buffering
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by means of two memory pointers. When using the FIFO it is possible to
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configure transfers to occur in indivisible bursts.
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It is also possible to select a peripheral instead of the DMA controller to
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control the flow of data. This limits the functionality but is useful when the
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number of transfers is unknown.
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#include <libopencm3/stm32/dma.h>
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Reset
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The specified stream is disabled and configuration registers are cleared.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] stream unsigned int8. Stream number: @ref dma_st_number
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*/
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void dma_stream_reset(uint32_t dma, uint8_t stream)
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{
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/* Disable stream (must be done before register is otherwise changed). */
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DMA_SCR(dma, stream) &= ~DMA_SxCR_EN;
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/* Reset all config bits. */
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DMA_SCR(dma, stream) = 0;
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/* Reset data transfer number. */
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DMA_SNDTR(dma, stream) = 0;
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/* Reset peripheral and memory addresses. */
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DMA_SPAR(dma, stream) = 0;
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DMA_SM0AR(dma, stream) = 0;
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DMA_SM1AR(dma, stream) = 0;
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/* This is the default setting */
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DMA_SFCR(dma, stream) = 0x21;
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/* Reset all stream interrupt flags using the interrupt flag clear register. */
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uint32_t mask = DMA_ISR_MASK(stream);
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if (stream < 4) {
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DMA_LIFCR(dma) |= mask;
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} else {
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DMA_HIFCR(dma) |= mask;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Clear Interrupt Flag
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The interrupt flag for the stream is cleared. More than one interrupt for the
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same stream may be cleared by using the bitwise OR of the interrupt flags.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] stream unsigned int8. Stream number: @ref dma_st_number
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@param[in] interrupts unsigned int32. Bitwise OR of interrupt numbers: @ref
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dma_if_offset
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*/
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void dma_clear_interrupt_flags(uint32_t dma, uint8_t stream,
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uint32_t interrupts)
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{
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/* Get offset to interrupt flag location in stream field */
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uint32_t flags = (interrupts << DMA_ISR_OFFSET(stream));
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/* First four streams are in low register. Flag clear must be set then
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* reset.
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*/
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if (stream < 4) {
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DMA_LIFCR(dma) = flags;
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} else {
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DMA_HIFCR(dma) = flags;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Read Interrupt Flag
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The interrupt flag for the stream is returned.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] stream unsigned int8. Stream number: @ref dma_st_number
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@param[in] interrupt unsigned int32. Interrupt number: @ref dma_if_offset
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@returns bool interrupt flag is set.
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*/
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bool dma_get_interrupt_flag(uint32_t dma, uint8_t stream, uint32_t interrupt)
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{
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/* get offset to interrupt flag location in stream field. Assumes
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* stream and interrupt parameters are integers.
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*/
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uint32_t flag = (interrupt << DMA_ISR_OFFSET(stream));
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/* First four streams are in low register */
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if (stream < 4) {
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return ((DMA_LISR(dma) & flag) > 0);
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} else {
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return ((DMA_HISR(dma) & flag) > 0);
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Enable Transfer Direction
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Set peripheral to memory, memory to peripheral or memory to memory. If memory
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to memory mode is selected, circular mode and double buffer modes are disabled.
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Ensure that these modes are not enabled at a later time.
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Ensure that the stream is disabled otherwise the setting will not be changed.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] stream unsigned int8. Stream number: @ref dma_st_number
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@param[in] direction unsigned int32. Data transfer direction @ref dma_st_dir
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*/
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void dma_set_transfer_mode(uint32_t dma, uint8_t stream, uint32_t direction)
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{
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uint32_t reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_DIR_MASK);
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/* Disable circular and double buffer modes if memory to memory
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* transfers are in effect. (Direct Mode is automatically disabled by
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* hardware)
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*/
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if (direction == DMA_SxCR_DIR_MEM_TO_MEM) {
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reg32 &= ~(DMA_SxCR_CIRC | DMA_SxCR_DBM);
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}
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DMA_SCR(dma, stream) = (reg32 | direction);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Set Priority
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Stream Priority has four levels: low to very high. This has precedence over the
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hardware priority. In the event of equal software priority the lower numbered
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stream has priority.
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Ensure that the stream is disabled otherwise the setting will not be changed.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] stream unsigned int8. Stream number: @ref dma_st_number
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@param[in] prio unsigned int32. Priority level @ref dma_st_pri.
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*/
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void dma_set_priority(uint32_t dma, uint8_t stream, uint32_t prio)
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{
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DMA_SCR(dma, stream) &= ~(DMA_SxCR_PL_MASK);
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DMA_SCR(dma, stream) |= prio;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Set Memory Word Width
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Set the memory word width 8 bits, 16 bits, or 32 bits. Refer to datasheet for
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alignment information if the source and destination widths do not match.
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Ensure that the stream is disabled otherwise the setting will not be changed.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] stream unsigned int8. Stream number: @ref dma_st_number
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@param[in] mem_size unsigned int32. Memory word width @ref dma_st_memwidth.
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*/
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void dma_set_memory_size(uint32_t dma, uint8_t stream, uint32_t mem_size)
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{
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DMA_SCR(dma, stream) &= ~(DMA_SxCR_MSIZE_MASK);
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DMA_SCR(dma, stream) |= mem_size;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Set Peripheral Word Width
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Set the peripheral word width 8 bits, 16 bits, or 32 bits. Refer to datasheet
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for alignment information if the source and destination widths do not match, or
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if the peripheral does not support byte or half-word writes.
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Ensure that the stream is disabled otherwise the setting will not be changed.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] stream unsigned int8. Stream number: @ref dma_st_number
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@param[in] peripheral_size unsigned int32. Peripheral word width @ref
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dma_st_perwidth.
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*/
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void dma_set_peripheral_size(uint32_t dma, uint8_t stream,
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uint32_t peripheral_size)
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{
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DMA_SCR(dma, stream) &= ~(DMA_SxCR_PSIZE_MASK);
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DMA_SCR(dma, stream) |= peripheral_size;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Enable Memory Increment after Transfer
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Following each transfer the current memory address is incremented by
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1, 2 or 4 depending on the data size set in @ref dma_set_memory_size. The
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value held by the base memory address register is unchanged.
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Ensure that the stream is disabled otherwise the setting will not be changed.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] stream unsigned int8. Stream number: @ref dma_st_number
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*/
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void dma_enable_memory_increment_mode(uint32_t dma, uint8_t stream)
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{
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DMA_SCR(dma, stream) |= DMA_SxCR_MINC;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Disable Memory Increment after Transfer
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Ensure that the stream is disabled otherwise the setting will not be changed.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] stream unsigned int8. Stream number: @ref dma_st_number
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*/
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void dma_disable_memory_increment_mode(uint32_t dma, uint8_t stream)
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{
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DMA_SCR(dma, stream) &= ~DMA_SxCR_MINC;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Enable Variable Sized Peripheral Increment after Transfer
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Following each transfer the current peripheral address is incremented by
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1, 2 or 4 depending on the data size set in @ref dma_set_peripheral_size. The
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value held by the base peripheral address register is unchanged.
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Ensure that the stream is disabled otherwise the setting will not be changed.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] stream unsigned int8. Stream number: @ref dma_st_number
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*/
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void dma_enable_peripheral_increment_mode(uint32_t dma, uint8_t stream)
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{
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uint32_t reg32 = (DMA_SCR(dma, stream) | DMA_SxCR_PINC);
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DMA_SCR(dma, stream) = (reg32 & ~DMA_SxCR_PINCOS);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Disable Peripheral Increment after Transfer
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Ensure that the stream is disabled otherwise the setting will not be changed.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] stream unsigned int8. Stream number: @ref dma_st_number
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*/
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void dma_disable_peripheral_increment_mode(uint32_t dma, uint8_t stream)
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{
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DMA_SCR(dma, stream) &= ~DMA_SxCR_PINC;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Enable Fixed Sized Peripheral Increment after Transfer
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Following each transfer the current peripheral address is incremented by
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4 regardless of the data size. The value held by the base peripheral address
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register is unchanged.
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Ensure that the stream is disabled otherwise the setting will not be changed.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] stream unsigned int8. Stream number: @ref dma_st_number
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*/
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void dma_enable_fixed_peripheral_increment_mode(uint32_t dma, uint8_t stream)
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{
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DMA_SCR(dma, stream) |= (DMA_SxCR_PINC | DMA_SxCR_PINCOS);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Enable Memory Circular Mode
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After the number of bytes/words to be transferred has been completed, the
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original transfer block size, memory and peripheral base addresses are
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reloaded and the process repeats.
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Ensure that the stream is disabled otherwise the setting will not be changed.
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@note This cannot be used with memory to memory mode. It is disabled
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automatically if the peripheral is selected as the flow controller.
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It is enabled automatically if double buffered mode is selected.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] stream unsigned int8. Stream number: @ref dma_st_number
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*/
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void dma_enable_circular_mode(uint32_t dma, uint8_t stream)
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{
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DMA_SCR(dma, stream) |= DMA_SxCR_CIRC;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Channel Select
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Associate an input channel to the stream. Not every channel is allocated to a
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hardware DMA request signal. The allocations for each stream are given in the
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STM32F4 Reference Manual.
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Ensure that the stream is disabled otherwise the setting will not be changed.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] stream unsigned int8. Stream number: @ref dma_st_number
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@param[in] channel unsigned int8. Channel selection @ref dma_ch_sel
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*/
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void dma_channel_select(uint32_t dma, uint8_t stream, uint32_t channel)
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{
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DMA_SCR(dma, stream) |= channel;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Set Memory Burst Configuration
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Set the memory burst type to none, 4 8 or 16 word length. This is forced to none
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if direct mode is used.
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Ensure that the stream is disabled otherwise the setting will not be changed.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] stream unsigned int8. Stream number: @ref dma_st_number
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@param[in] burst unsigned int8. Memory Burst selection @ref dma_mburst
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*/
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void dma_set_memory_burst(uint32_t dma, uint8_t stream, uint32_t burst)
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{
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uint32_t reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_MBURST_MASK);
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DMA_SCR(dma, stream) = (reg32 | burst);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Set Peripheral Burst Configuration
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Set the memory burst type to none, 4 8 or 16 word length. This is forced to none
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if direct mode is used.
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Ensure that the stream is disabled otherwise the setting will not be changed.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] stream unsigned int8. Stream number: @ref dma_st_number
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@param[in] burst unsigned int8. Peripheral Burst selection @ref dma_pburst
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*/
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void dma_set_peripheral_burst(uint32_t dma, uint8_t stream, uint32_t burst)
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{
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uint32_t reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_PBURST_MASK);
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DMA_SCR(dma, stream) = (reg32 | burst);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Set Initial Target Memory
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In double buffered mode, set the target memory (M0 or M1) to be used for the
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first transfer.
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Ensure that the stream is disabled otherwise the setting will not be changed.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] stream unsigned int8. Stream number: @ref dma_st_number
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@param[in] memory unsigned int8. Initial memory pointer to use: 0 or 1
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*/
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void dma_set_initial_target(uint32_t dma, uint8_t stream, uint8_t memory)
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{
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uint32_t reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_CT);
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if (memory == 1) {
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reg32 |= DMA_SxCR_CT;
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}
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DMA_SCR(dma, stream) = reg32;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Read Current Memory Target
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In double buffer mode, return the current memory target (M0 or M1). It is
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possible to update the memory pointer in the register that is <b> not </b>
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currently in use. An attempt to change the register currently in use will cause
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the stream to be disabled and the transfer error flag to be set.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] stream unsigned int8. Stream number: @ref dma_st_number
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@returns unsigned int8. Memory buffer in use: 0 or 1
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*/
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uint8_t dma_get_target(uint32_t dma, uint8_t stream)
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{
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if (DMA_SCR(dma, stream) & DMA_SxCR_CT) {
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return 1;
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}
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return 0;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Enable Double Buffer Mode
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Double buffer mode is used for memory to/from peripheral transfers only, and in
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circular mode which is automatically enabled. Two memory buffers must be
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established with pointers stored in the memory pointer registers.
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Ensure that the stream is disabled otherwise the setting will not be changed.
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@note This cannot be used with memory to memory mode.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] stream unsigned int8. Stream number: @ref dma_st_number
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*/
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void dma_enable_double_buffer_mode(uint32_t dma, uint8_t stream)
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{
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DMA_SCR(dma, stream) |= DMA_SxCR_DBM;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Disable Double Buffer Mode
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] stream unsigned int8. Stream number: @ref dma_st_number
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*/
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void dma_disable_double_buffer_mode(uint32_t dma, uint8_t stream)
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{
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DMA_SCR(dma, stream) &= ~DMA_SxCR_DBM;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Stream Set Peripheral Flow Control
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Set the peripheral to control DMA flow. Useful when the number of transfers is
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unknown. This is forced off when memory to memory mode is selected.
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Ensure that the stream is disabled otherwise the setting will not be changed.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] stream unsigned int8. Stream number: @ref dma_st_number
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*/
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void dma_set_peripheral_flow_control(uint32_t dma, uint8_t stream)
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{
|
|
DMA_SCR(dma, stream) |= DMA_SxCR_PFCTRL;
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief DMA Stream Set DMA Flow Control
|
|
|
|
Set the DMA controller to control DMA flow. This is the default.
|
|
|
|
Ensure that the stream is disabled otherwise the setting will not be changed.
|
|
|
|
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
|
|
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
|
|
*/
|
|
|
|
void dma_set_dma_flow_control(uint32_t dma, uint8_t stream)
|
|
{
|
|
DMA_SCR(dma, stream) &= ~DMA_SxCR_PFCTRL;
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief DMA Stream Enable Interrupt on Transfer Error
|
|
|
|
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
|
|
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
|
|
*/
|
|
|
|
void dma_enable_transfer_error_interrupt(uint32_t dma, uint8_t stream)
|
|
{
|
|
dma_clear_interrupt_flags(dma, stream, DMA_TEIF);
|
|
DMA_SCR(dma, stream) |= DMA_SxCR_TEIE;
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief DMA Stream Disable Interrupt on Transfer Error
|
|
|
|
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
|
|
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
|
|
*/
|
|
|
|
void dma_disable_transfer_error_interrupt(uint32_t dma, uint8_t stream)
|
|
{
|
|
DMA_SCR(dma, stream) &= ~DMA_SxCR_TEIE;
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief DMA Stream Enable Interrupt on Transfer Half Complete
|
|
|
|
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
|
|
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
|
|
*/
|
|
|
|
void dma_enable_half_transfer_interrupt(uint32_t dma, uint8_t stream)
|
|
{
|
|
dma_clear_interrupt_flags(dma, stream, DMA_HTIF);
|
|
DMA_SCR(dma, stream) |= DMA_SxCR_HTIE;
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief DMA Stream Disable Interrupt on Transfer Half Complete
|
|
|
|
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
|
|
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
|
|
*/
|
|
|
|
void dma_disable_half_transfer_interrupt(uint32_t dma, uint8_t stream)
|
|
{
|
|
DMA_SCR(dma, stream) &= ~DMA_SxCR_HTIE;
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief DMA Stream Enable Interrupt on Transfer Complete
|
|
|
|
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
|
|
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
|
|
*/
|
|
|
|
void dma_enable_transfer_complete_interrupt(uint32_t dma, uint8_t stream)
|
|
{
|
|
dma_clear_interrupt_flags(dma, stream, DMA_TCIF);
|
|
DMA_SCR(dma, stream) |= DMA_SxCR_TCIE;
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief DMA Stream Disable Interrupt on Transfer Complete
|
|
|
|
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
|
|
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
|
|
*/
|
|
|
|
void dma_disable_transfer_complete_interrupt(uint32_t dma, uint8_t stream)
|
|
{
|
|
DMA_SCR(dma, stream) &= ~DMA_SxCR_TCIE;
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief DMA Stream Enable Interrupt on Direct Mode Error
|
|
|
|
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
|
|
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
|
|
*/
|
|
|
|
void dma_enable_direct_mode_error_interrupt(uint32_t dma, uint8_t stream)
|
|
{
|
|
dma_clear_interrupt_flags(dma, stream, DMA_DMEIF);
|
|
DMA_SCR(dma, stream) |= DMA_SxCR_DMEIE;
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief DMA Stream Disable Interrupt on Direct Mode Error
|
|
|
|
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
|
|
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
|
|
*/
|
|
|
|
void dma_disable_direct_mode_error_interrupt(uint32_t dma, uint8_t stream)
|
|
{
|
|
DMA_SCR(dma, stream) &= ~DMA_SxCR_DMEIE;
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief DMA Enable Interrupt on FIFO Error
|
|
|
|
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
|
|
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
|
|
*/
|
|
|
|
void dma_enable_fifo_error_interrupt(uint32_t dma, uint8_t stream)
|
|
{
|
|
dma_clear_interrupt_flags(dma, stream, DMA_FEIF);
|
|
DMA_SFCR(dma, stream) |= DMA_SxFCR_FEIE;
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief DMA Disable Interrupt on FIFO Error
|
|
|
|
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
|
|
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
|
|
*/
|
|
|
|
void dma_disable_fifo_error_interrupt(uint32_t dma, uint8_t stream)
|
|
{
|
|
DMA_SFCR(dma, stream) &= ~DMA_SxFCR_FEIE;
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief DMA Get FIFO Status
|
|
|
|
Status of FIFO (empty. full or partial filled states) is returned. This has no
|
|
meaning if direct mode is enabled (as the FIFO is not used).
|
|
|
|
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
|
|
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
|
|
@returns uint32_t FIFO Status @ref dma_fifo_status
|
|
*/
|
|
|
|
uint32_t dma_fifo_status(uint32_t dma, uint8_t stream)
|
|
{
|
|
return DMA_SFCR(dma, stream) & DMA_SxFCR_FS_MASK;
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief DMA Enable Direct Mode
|
|
|
|
Direct mode is the default. Data is transferred as soon as a DMA request is
|
|
received. The FIFO is not used. This must not be set when memory to memory
|
|
mode is selected.
|
|
|
|
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
|
|
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
|
|
*/
|
|
|
|
void dma_enable_direct_mode(uint32_t dma, uint8_t stream)
|
|
{
|
|
DMA_SFCR(dma, stream) &= ~DMA_SxFCR_DMDIS;
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief DMA Enable FIFO Mode
|
|
|
|
Data is transferred via a FIFO.
|
|
|
|
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
|
|
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
|
|
*/
|
|
|
|
void dma_enable_fifo_mode(uint32_t dma, uint8_t stream)
|
|
{
|
|
DMA_SFCR(dma, stream) |= DMA_SxFCR_DMDIS;
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief DMA Set FIFO Threshold
|
|
|
|
This is the filled level at which data is transferred out of the FIFO to the
|
|
destination.
|
|
|
|
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
|
|
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
|
|
@param[in] threshold unsigned int8. Threshold setting @ref dma_fifo_thresh
|
|
*/
|
|
|
|
void dma_set_fifo_threshold(uint32_t dma, uint8_t stream, uint32_t threshold)
|
|
{
|
|
uint32_t reg32 = (DMA_SFCR(dma, stream) & ~DMA_SxFCR_FTH_MASK);
|
|
DMA_SFCR(dma, stream) = (reg32 | threshold);
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief DMA Stream Enable
|
|
|
|
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
|
|
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
|
|
*/
|
|
|
|
void dma_enable_stream(uint32_t dma, uint8_t stream)
|
|
{
|
|
DMA_SCR(dma, stream) |= DMA_SxCR_EN;
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief DMA Stream Disable
|
|
|
|
@note The DMA stream registers retain their values when the stream is disabled.
|
|
|
|
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
|
|
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
|
|
*/
|
|
|
|
void dma_disable_stream(uint32_t dma, uint8_t stream)
|
|
{
|
|
DMA_SCR(dma, stream) &= ~DMA_SxCR_EN;
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief DMA Stream Set the Peripheral Address
|
|
|
|
Set the address of the peripheral register to or from which data is to be
|
|
transferred. Refer to the documentation for the specific peripheral.
|
|
|
|
@note The DMA stream must be disabled before setting this address. This function
|
|
has no effect if the stream is enabled.
|
|
|
|
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
|
|
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
|
|
@param[in] address unsigned int32. Peripheral Address.
|
|
*/
|
|
|
|
void dma_set_peripheral_address(uint32_t dma, uint8_t stream, uint32_t address)
|
|
{
|
|
if (!(DMA_SCR(dma, stream) & DMA_SxCR_EN)) {
|
|
DMA_SPAR(dma, stream) = (uint32_t *) address;
|
|
}
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief DMA Stream Set the Base Memory Address 0
|
|
|
|
Set the address pointer to the memory location for DMA transfers. The DMA stream
|
|
must normally be disabled before setting this address, however it is possible
|
|
to change this in double buffer mode when the current target is memory area 1
|
|
(see @ref dma_get_target).
|
|
|
|
This is the default base memory address used in direct mode.
|
|
|
|
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
|
|
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
|
|
@param[in] address unsigned int32. Memory Initial Address.
|
|
*/
|
|
|
|
void dma_set_memory_address(uint32_t dma, uint8_t stream, uint32_t address)
|
|
{
|
|
uint32_t reg32 = DMA_SCR(dma, stream);
|
|
if (!(reg32 & DMA_SxCR_EN) ||
|
|
((reg32 & DMA_SxCR_CT) && (reg32 & DMA_SxCR_DBM))) {
|
|
DMA_SM0AR(dma, stream) = (uint32_t *) address;
|
|
}
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief DMA Stream Set the Base Memory Address 1
|
|
|
|
Set the address pointer to the memory location for DMA transfers. The DMA stream
|
|
must normally be disabled before setting this address, however it is possible
|
|
to change this in double buffer mode when the current target is memory area 0
|
|
(see @ref dma_get_target).
|
|
|
|
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
|
|
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
|
|
@param[in] address unsigned int32. Memory Initial Address.
|
|
*/
|
|
|
|
void dma_set_memory_address_1(uint32_t dma, uint8_t stream, uint32_t address)
|
|
{
|
|
uint32_t reg32 = DMA_SCR(dma, stream);
|
|
if (!(reg32 & DMA_SxCR_EN) ||
|
|
(!(reg32 & DMA_SxCR_CT) && (reg32 & DMA_SxCR_DBM))) {
|
|
DMA_SM1AR(dma, stream) = (uint32_t *) address;
|
|
}
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief DMA Stream Get the Transfer Block Size
|
|
|
|
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
|
|
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
|
|
@returns unsigned int16. Number of remaining data words to transfer (65535
|
|
maximum).
|
|
*/
|
|
|
|
uint16_t dma_get_number_of_data(uint32_t dma, uint8_t stream)
|
|
{
|
|
return DMA_SNDTR(dma, stream);
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief DMA Stream Set the Transfer Block Size
|
|
|
|
@note The DMA stream must be disabled before setting this count value. The count
|
|
is not changed if the stream is enabled.
|
|
|
|
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
|
|
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
|
|
@param[in] number unsigned int16. Number of data words to transfer (65535
|
|
maximum).
|
|
*/
|
|
|
|
void dma_set_number_of_data(uint32_t dma, uint8_t stream, uint16_t number)
|
|
{
|
|
DMA_SNDTR(dma, stream) = number;
|
|
}
|
|
/**@}*/
|
|
|