Arti Zirk
2de3a91b0a
subrepo: subdir: "libopencm3" merged: "88e91c9a7cce" upstream: origin: "https://github.com/libopencm3/libopencm3.git" branch: "master" commit: "88e91c9a7cce" git-subrepo: version: "0.4.3" origin: "???" commit: "???"
313 lines
7.8 KiB
YAML
313 lines
7.8 KiB
YAML
!!omap
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- CREG_CREG0:
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fields: !!omap
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- EN1KHZ:
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access: rw
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description: Enable 1 kHz output
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lsb: 0
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reset_value: '0'
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width: 1
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- EN32KHZ:
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access: rw
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description: Enable 32 kHz output
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lsb: 1
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reset_value: '0'
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width: 1
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- RESET32KHZ:
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access: rw
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description: 32 kHz oscillator reset
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lsb: 2
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reset_value: '1'
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width: 1
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- PD32KHZ:
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access: rw
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description: 32 kHz power control
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lsb: 3
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reset_value: '1'
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width: 1
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- USB0PHY:
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access: rw
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description: USB0 PHY power control
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lsb: 5
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reset_value: '1'
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width: 1
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- ALARMCTRL:
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access: rw
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description: RTC_ALARM pin output control
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lsb: 6
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reset_value: '0'
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width: 2
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- BODLVL1:
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access: rw
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description: BOD trip level to generate an interrupt
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lsb: 8
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reset_value: '0x3'
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width: 2
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- BODLVL2:
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access: rw
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description: BOD trip level to generate a reset
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lsb: 10
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reset_value: '0x3'
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width: 2
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- SAMPLECTRL:
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access: rw
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description: SAMPLE pin input/output control
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lsb: 12
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reset_value: '0'
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width: 2
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- WAKEUP0CTRL:
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access: rw
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description: WAKEUP0 pin input/output control
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lsb: 14
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reset_value: '0'
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width: 2
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- WAKEUP1CTRL:
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access: rw
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description: WAKEUP1 pin input/output control
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lsb: 16
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reset_value: '0'
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width: 2
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- CREG_M4MEMMAP:
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fields: !!omap
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- M4MAP:
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access: rw
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description: Shadow address when accessing memory at address 0x00000000
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lsb: 12
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reset_value: '0x10400000'
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width: 20
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- CREG_CREG5:
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fields: !!omap
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- M4TAPSEL:
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access: rw
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description: JTAG debug select for M4 core
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lsb: 6
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reset_value: '1'
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width: 1
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- M0APPTAPSEL:
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access: rw
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description: JTAG debug select for M0 co-processor
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lsb: 9
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reset_value: '1'
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width: 1
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- CREG_DMAMUX:
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fields: !!omap
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- DMAMUXPER0:
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access: rw
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description: Select DMA to peripheral connection for DMA peripheral 0
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lsb: 0
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reset_value: '0'
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width: 2
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- DMAMUXPER1:
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access: rw
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description: Select DMA to peripheral connection for DMA peripheral 1
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lsb: 2
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reset_value: '0'
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width: 2
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- DMAMUXPER2:
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access: rw
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description: Select DMA to peripheral connection for DMA peripheral 2
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lsb: 4
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reset_value: '0'
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width: 2
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- DMAMUXPER3:
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access: rw
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description: Select DMA to peripheral connection for DMA peripheral 3
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lsb: 6
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reset_value: '0'
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width: 2
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- DMAMUXPER4:
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access: rw
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description: Select DMA to peripheral connection for DMA peripheral 4
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lsb: 8
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reset_value: '0'
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width: 2
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- DMAMUXPER5:
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access: rw
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description: Select DMA to peripheral connection for DMA peripheral 5
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lsb: 10
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reset_value: '0'
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width: 2
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- DMAMUXPER6:
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access: rw
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description: Select DMA to peripheral connection for DMA peripheral 6
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lsb: 12
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reset_value: '0'
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width: 2
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- DMAMUXPER7:
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access: rw
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description: Select DMA to peripheral connection for DMA peripheral 7
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lsb: 14
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reset_value: '0'
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width: 2
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- DMAMUXPER8:
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access: rw
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description: Select DMA to peripheral connection for DMA peripheral 8
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lsb: 16
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reset_value: '0'
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width: 2
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- DMAMUXPER9:
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access: rw
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description: Select DMA to peripheral connection for DMA peripheral 9
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lsb: 18
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reset_value: '0'
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width: 2
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- DMAMUXPER10:
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access: rw
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description: Select DMA to peripheral connection for DMA peripheral 10
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lsb: 20
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reset_value: '0'
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width: 2
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- DMAMUXPER11:
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access: rw
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description: Select DMA to peripheral connection for DMA peripheral 11
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lsb: 22
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reset_value: '0'
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width: 2
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- DMAMUXPER12:
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access: rw
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description: Select DMA to peripheral connection for DMA peripheral 12
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lsb: 24
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reset_value: '0'
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width: 2
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- DMAMUXPER13:
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access: rw
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description: Select DMA to peripheral connection for DMA peripheral 13
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lsb: 26
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reset_value: '0'
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width: 2
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- DMAMUXPER14:
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access: rw
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description: Select DMA to peripheral connection for DMA peripheral 14
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lsb: 28
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reset_value: '0'
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width: 2
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- DMAMUXPER15:
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access: rw
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description: Select DMA to peripheral connection for DMA peripheral 15
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lsb: 30
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reset_value: '0'
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width: 2
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- CREG_FLASHCFGA:
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fields: !!omap
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- FLASHTIM:
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access: rw
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description: Flash access time. The value of this field plus 1 gives the number
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of BASE_M4_CLK clocks used for a flash access
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lsb: 12
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reset_value: ''
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width: 4
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- POW:
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access: rw
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description: Flash bank A power control
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lsb: 31
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reset_value: '1'
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width: 1
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- CREG_FLASHCFGB:
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fields: !!omap
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- FLASHTIM:
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access: rw
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description: Flash access time. The value of this field plus 1 gives the number
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of BASE_M4_CLK clocks used for a flash access
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lsb: 12
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reset_value: ''
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width: 4
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- POW:
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access: rw
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description: Flash bank B power control
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lsb: 31
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reset_value: '1'
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width: 1
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- CREG_ETBCFG:
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fields: !!omap
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- ETB:
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access: rw
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description: Select SRAM interface
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lsb: 0
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reset_value: '1'
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width: 1
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- CREG_CREG6:
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fields: !!omap
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- ETHMODE:
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access: rw
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description: Selects the Ethernet mode. Reset the ethernet after changing
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the PHY interface
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lsb: 0
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reset_value: ''
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width: 3
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- CTOUTCTRL:
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access: rw
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description: Selects the functionality of the SCT outputs
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lsb: 4
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reset_value: '0'
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width: 1
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- I2S0_TX_SCK_IN_SEL:
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access: rw
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description: I2S0_TX_SCK input select
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lsb: 12
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reset_value: '0'
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width: 1
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- I2S0_RX_SCK_IN_SEL:
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access: rw
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description: I2S0_RX_SCK input select
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lsb: 13
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reset_value: '0'
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width: 1
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- I2S1_TX_SCK_IN_SEL:
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access: rw
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description: I2S1_TX_SCK input select
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lsb: 14
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reset_value: '0'
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width: 1
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- I2S1_RX_SCK_IN_SEL:
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access: rw
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description: I2S1_RX_SCK input select
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lsb: 15
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reset_value: '0'
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width: 1
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- EMC_CLK_SEL:
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access: rw
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description: EMC_CLK divided clock select
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lsb: 16
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reset_value: '0'
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width: 1
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- CREG_M4TXEVENT:
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fields: !!omap
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- TXEVCLR:
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access: rw
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description: Cortex-M4 TXEV event
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lsb: 0
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reset_value: '0'
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width: 1
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- CREG_M0TXEVENT:
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fields: !!omap
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- TXEVCLR:
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access: rw
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description: Cortex-M0 TXEV event
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lsb: 0
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reset_value: '0'
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width: 1
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- CREG_M0APPMEMMAP:
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fields: !!omap
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- M0APPMAP:
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access: rw
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description: Shadow address when accessing memory at address 0x00000000
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lsb: 12
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reset_value: '0x20000000'
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width: 20
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- CREG_USB0FLADJ:
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fields: !!omap
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- FLTV:
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access: rw
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description: Frame length timing value
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lsb: 0
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reset_value: '0x20'
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width: 6
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- CREG_USB1FLADJ:
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fields: !!omap
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- FLTV:
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access: rw
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description: Frame length timing value
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lsb: 0
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reset_value: '0x20'
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width: 6
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