Arti Zirk
2de3a91b0a
subrepo: subdir: "libopencm3" merged: "88e91c9a7cce" upstream: origin: "https://github.com/libopencm3/libopencm3.git" branch: "master" commit: "88e91c9a7cce" git-subrepo: version: "0.4.3" origin: "???" commit: "???"
72 lines
1.8 KiB
YAML
72 lines
1.8 KiB
YAML
!!omap
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- ATIMER_DOWNCOUNTER:
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fields: !!omap
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- CVAL:
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access: rw
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description: When equal to zero an interrupt is raised
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lsb: 0
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reset_value: '0'
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width: 16
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- ATIMER_PRESET:
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fields: !!omap
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- PRESETVAL:
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access: rw
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description: Value loaded in DOWNCOUNTER when DOWNCOUNTER equals zero
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lsb: 0
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reset_value: '0'
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width: 16
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- ATIMER_CLR_EN:
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fields: !!omap
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- CLR_EN:
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access: w
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description: Writing a 1 to this bit clears the interrupt enable bit in the
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ENABLE register
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lsb: 0
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reset_value: '0'
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width: 1
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- ATIMER_SET_EN:
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fields: !!omap
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- SET_EN:
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access: w
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description: Writing a 1 to this bit sets the interrupt enable bit in the
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ENABLE register
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lsb: 0
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reset_value: '0'
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width: 1
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- ATIMER_STATUS:
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fields: !!omap
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- STAT:
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access: r
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description: A 1 in this bit shows that the STATUS interrupt has been raised
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lsb: 0
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reset_value: '0'
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width: 1
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- ATIMER_ENABLE:
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fields: !!omap
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- ENA:
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access: r
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description: A 1 in this bit shows that the STATUS interrupt has been enabled
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and that the STATUS interrupt request signal is asserted when STAT = 1 in
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the STATUS register
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lsb: 0
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reset_value: '0'
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width: 1
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- ATIMER_CLR_STAT:
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fields: !!omap
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- CSTAT:
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access: w
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description: Writing a 1 to this bit clears the STATUS interrupt bit in the
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STATUS register
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lsb: 0
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reset_value: '0'
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width: 1
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- ATIMER_SET_STAT:
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fields: !!omap
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- SSTAT:
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access: w
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description: Writing a 1 to this bit sets the STATUS interrupt bit in the
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STATUS register
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lsb: 0
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reset_value: '0'
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width: 1
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