488 lines
15 KiB
C
488 lines
15 KiB
C
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/** @addtogroup dac_file DAC peripheral API
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* @ingroup peripheral_apis
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* @brief Digital to Analog Converter
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@author @htmlonly © @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
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@author @htmlonly © @endhtmlonly 2020 Ben Brewer <ben.brewer@codethink.co.uk>
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This library supports the Digital to Analog Conversion System in the
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STM32 series of ARM Cortex Microcontrollers by ST Microelectronics.
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The DAC peripheral found on many of the devices in the STM32 lineup,
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sometimes with only one channel, but normally with two channels.
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Two DAC channels are available, however unlike the ADC channels these
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are separate DAC devices controlled by the same register block.
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The DAC is on APB1. Its clock must be enabled in RCC and depending on
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specific family, the GPIO
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ports set to alternate function output before it can be used.
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On most families, the GPIO pins should be configured to Analog IN to
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avoid parasitic consumption.
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The digital output driver is disabled so the output driver mode
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(push-pull/open drain) is arbitrary.
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The DAC has a holding (buffer) register and an output register from
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which the analog output is derived. The holding register must be
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loaded first. If triggering is enabled the output register is loaded
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from the holding register after a trigger occurs. If triggering is
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not enabled the holding register contents are transferred directly
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to the output register.
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@note To avoid nonlinearities, do not allow outputs to range close
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to zero or V_analog.
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@section dac_api_dual Dual Channel Conversion
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There are dual modes in which both DACs are used to output data
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simultaneously or independently on both channels. The data must be
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presented according to the formats described in the datasheets. A
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convenience function @ref dac_load_data_buffer_dual is provided
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for software controlled use.
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A variety of modes are available depending on whether independent
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or simultaneous output is desired, and whether waveforms are to be
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superimposed. Refer to the datasheets.
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If DMA is used, only enable it for one of the channels. The DMA
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requests will then serve data in dual format to the data register
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dedicated to dual mode. The data will then be split and loaded to the
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appropriate DAC following the next trigger. There are three registers
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available, one for each of the formats: 12 bit right-aligned, 12 bit
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left-aligned and 8 bit right-aligned. The desired format is determined
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by specifying the appropriate register to the DMA controller.
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@section dac_api_basic_ex Basic DAC handling API.
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Set the DAC's GPIO port to Analog IN. Enable the
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DAC clock. Enable the DAC, set a trigger source and load the buffer
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with the first value. After the DAC is triggered, load the buffer with
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the next value. This example uses software triggering and added noise.
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The trigger and further buffer load calls are made when data is to be
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sent out.
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@code
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gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ,
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GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO4);
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rcc_periph_clock_enable(RCC_DAC);
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dac_disable(DAC1, DAC_CHANNEL1);
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dac_set_waveform_characteristics(DAC1, DAC_CHANNEL1, DAC_CR_MAMP1_8);
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dac_set_waveform_generation(DAC1, DAC_CHANNEL1, DAC_CR_WAVE1_NOISE);
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dac_enable(DAC1, DAC_CHANNEL1);
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dac_set_trigger_source(DAC1, DAC_CR_TSEL1_SW);
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dac_load_data_buffer_single(DAC1, 0, DAC_ALIGN_RIGHT12, DAC_CHANNEL1);
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....
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dac_software_trigger(DAC1, DAC_CHANNEL1);
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dac_load_data_buffer_single(DAC1, value,
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DAC_ALIGN_RIGHT12, DAC_CHANNEL1);
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@endcode
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@section dac_api_dma_ex Simultaneous Dual DAC with DMA.
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This example in part sets up the DAC channel 1 DMA (DMA2 channel 3) to read
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16 bit data from memory into the right-aligned 8 bit dual register DAC_DHR8RD.
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Both DAC channels are enabled, and both triggers are set to the same timer
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2 input as required for simultaneous operation. DMA is enabled for DAC channel
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1 only to ensure that only one DMA request is generated.
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@code
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dma_set_memory_size(DMA2, DMA_CHANNEL3, DMA_CCR_MSIZE_16BIT);
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dma_set_peripheral_size(DMA2, DMA_CHANNEL3, DMA_CCR_PSIZE_16BIT);
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dma_set_read_from_memory(DMA2, DMA_CHANNEL3);
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dma_set_peripheral_address(DMA2, DMA_CHANNEL3,(uint32_t) &DAC_DHR8RD);
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dma_enable_channel(DMA2, DMA_CHANNEL3);
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...
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dac_trigger_enable(DAC1, DAC_CHANNEL_BOTH);
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dac_set_trigger_source(DAC1, DAC_CR_TSEL1_T2 | DAC_CR_TSEL2_T2);
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dac_dma_enable(DAC1, DAC_CHANNEL1);
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dac_enable(DAC1, DAC_CHANNEL_BOTH);
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@endcode
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Ken Sarkies
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* Copyright (C) 2020 Ben Brewer
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#include <libopencm3/stm32/dac.h>
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/** @brief DAC Channel Enable.
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Enable a digital to analog converter channel. After setting this enable, the
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DAC requires a t<sub>wakeup</sub> time typically around 10 microseconds before
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it actually wakes up.
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@param[in] dac the base address of the DAC @ref dac_reg_base
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@param[in] channel with DAC mask. @ref dac_channel_id
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*/
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void dac_enable(uint32_t dac, int channel)
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{
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switch (channel) {
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case DAC_CHANNEL1:
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DAC_CR(dac) |= DAC_CR_EN1;
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break;
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case DAC_CHANNEL2:
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DAC_CR(dac) |= DAC_CR_EN2;
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break;
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case DAC_CHANNEL_BOTH:
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DAC_CR(dac) |= (DAC_CR_EN1 | DAC_CR_EN2);
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break;
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}
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}
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/** @brief DAC Channel Disable.
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Disable a digital to analog converter channel.
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@param[in] dac the base address of the DAC @ref dac_reg_base
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@param[in] channel with DAC mask @ref dac_channel_id
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*/
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void dac_disable(uint32_t dac, int channel)
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{
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switch (channel) {
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case DAC_CHANNEL1:
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DAC_CR(dac) &= ~DAC_CR_EN1;
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break;
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case DAC_CHANNEL2:
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DAC_CR(dac) &= ~DAC_CR_EN2;
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break;
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case DAC_CHANNEL_BOTH:
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DAC_CR(dac) &= ~(DAC_CR_EN1 | DAC_CR_EN2);
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break;
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default:
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break;
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}
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}
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/** @brief DAC Channel DMA Enable.
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Enable a digital to analog converter channel DMA mode (connected to DMA2 channel
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3 for DAC channel 1 and DMA2 channel 4 for DAC channel 2). A DMA request is
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generated following an external trigger.
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@param[in] dac the base address of the DAC. @ref dac_reg_base
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@param[in] channel with DAC mask. @ref dac_channel_id
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*/
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void dac_dma_enable(uint32_t dac, int channel)
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{
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switch (channel) {
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case DAC_CHANNEL1:
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DAC_CR(dac) |= DAC_CR_DMAEN1;
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break;
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case DAC_CHANNEL2:
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DAC_CR(dac) |= DAC_CR_DMAEN2;
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break;
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case DAC_CHANNEL_BOTH:
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DAC_CR(dac) |= (DAC_CR_DMAEN1 | DAC_CR_DMAEN2);
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break;
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default:
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break;
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}
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}
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/** @brief DAC Channel DMA Disable.
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Disable a digital to analog converter channel DMA mode.
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@param[in] dac the base address of the DAC. @ref dac_reg_base
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@param[in] channel with DAC mask. @ref dac_channel_id
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*/
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void dac_dma_disable(uint32_t dac, int channel)
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{
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switch (channel) {
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case DAC_CHANNEL1:
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DAC_CR(dac) &= ~DAC_CR_DMAEN1;
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break;
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case DAC_CHANNEL2:
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DAC_CR(dac) &= ~DAC_CR_DMAEN2;
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break;
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case DAC_CHANNEL_BOTH:
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DAC_CR(dac) &= ~(DAC_CR_DMAEN1 | DAC_CR_DMAEN2);
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break;
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default:
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break;
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}
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}
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/** @brief DAC Channel Trigger Enable.
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Enable a digital to analog converter channel external trigger mode. This allows
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an external trigger to initiate register transfers from the buffer register to
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the DAC output register, followed by a DMA transfer to the buffer register if
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DMA is enabled. The trigger source must also be selected.
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@param[in] dac the base address of the DAC. @ref dac_reg_base
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@param[in] channel with DAC mask. @ref dac_channel_id
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*/
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void dac_trigger_enable(uint32_t dac, int channel)
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{
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switch (channel) {
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case DAC_CHANNEL1:
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DAC_CR(dac) |= DAC_CR_TEN1;
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break;
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case DAC_CHANNEL2:
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DAC_CR(dac) |= DAC_CR_TEN2;
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break;
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case DAC_CHANNEL_BOTH:
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DAC_CR(dac) |= (DAC_CR_TEN1 | DAC_CR_TEN2);
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break;
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default:
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break;
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}
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}
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/** @brief DAC Channel Trigger Disable.
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Disable a digital to analog converter channel external trigger.
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@param[in] dac the base address of the DAC. @ref dac_reg_base
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@param[in] channel with DAC mask. @ref dac_channel_id
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*/
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void dac_trigger_disable(uint32_t dac, int channel)
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{
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switch (channel) {
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case DAC_CHANNEL1:
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DAC_CR(dac) &= ~DAC_CR_TEN1;
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break;
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case DAC_CHANNEL2:
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DAC_CR(dac) &= ~DAC_CR_TEN2;
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break;
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case DAC_CHANNEL_BOTH:
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DAC_CR(dac) &= ~(DAC_CR_TEN1 | DAC_CR_TEN2);
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break;
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default:
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break;
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}
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}
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/** @brief Set DAC Channel Trigger Source.
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Sets the digital to analog converter trigger source, which can be taken from
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various timers, an external trigger or a software trigger.
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@param[in] dac the base address of the DAC. @ref dac_reg_base
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@param[in] source Taken from @ref dac_trig2_sel or @ref
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dac_trig1_sel or a logical OR of one of each of these to set both channels
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simultaneously.
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*/
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void dac_set_trigger_source(uint32_t dac, uint32_t source)
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{
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DAC_CR(dac) |= source;
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}
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/**
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* Set DAC Channel Waveform Generation mode for one or both channels.
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* These signals are superimposed on existing output values in the
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* DAC output registers. Waveform can be disabled, noise, triangular,
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* or sawtooth, depending on family.
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* @note The DAC trigger must be enabled for this to work.
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* @param[in] dac the base address of the DAC. @ref dac_reg_base
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* @param[in] channel one or both, @ref dac_channel_id
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* @param[in] wave enum ::dac_wave. mode for channel
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*/
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void dac_set_waveform_generation(uint32_t dac, int channel, enum dac_wave wave)
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{
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uint32_t reg = DAC_CR(dac);
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switch(channel) {
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case DAC_CHANNEL1:
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reg &= ~(DAC_CR_WAVEx_MASK << DAC_CR_WAVE1_SHIFT);
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reg |= wave << DAC_CR_WAVE1_SHIFT;
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break;
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case DAC_CHANNEL2:
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reg &= ~(DAC_CR_WAVEx_MASK << DAC_CR_WAVE2_SHIFT);
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reg |= wave << DAC_CR_WAVE2_SHIFT;
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break;
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case DAC_CHANNEL_BOTH:
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reg &= ~(DAC_CR_WAVEx_MASK << DAC_CR_WAVE1_SHIFT)
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| ~(DAC_CR_WAVEx_MASK << DAC_CR_WAVE2_SHIFT);
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reg |= wave << DAC_CR_WAVE1_SHIFT;
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reg |= wave << DAC_CR_WAVE2_SHIFT;
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break;
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default:
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break;
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}
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DAC_CR(dac) = reg;
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}
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/**
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* Disable DAC Channel Waveform Generation.
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* @note this is equivalent to @ref dac_set_waveform_generation (dac, channel, DAC_WAVE_DISABLE)
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* @param[in] dac the base address of the DAC. @ref dac_reg_base
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* @param[in] channel with DAC mask. @ref dac_channel_id
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*/
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void dac_disable_waveform_generation(uint32_t dac, int channel)
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{
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dac_set_waveform_generation(dac, channel, DAC_WAVE_DISABLE);
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}
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/** @brief Set DAC Channel LFSR Mask or Triangle Wave Amplitude.
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Sets the digital to analog converter superimposed waveform generation
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characteristics. @li If the noise generation mode is set, this sets the length
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of the PRBS sequence and hence the amplitude of the output noise signal.
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Default setting is length 1. @li If the triangle wave generation mode is set,
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this sets the amplitude of the output signal as 2^(n)-1 where n is the
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parameter value. Default setting is 1.
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@note High amplitude levels of these waveforms can overload the DAC and distort
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the signal output.
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@note This must be called before enabling the DAC as the settings will then
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become read-only.
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@note The DAC trigger must be enabled for this to work.
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@param[in] dac the base address of the DAC. @ref dac_reg_base
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@param[in] channel one or both, select from @ref dac_channel_id
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|
@param[in] mamp amplitude of mixed waveform, bit width @ref DAC_CR_MAMPx_MASK
|
||
|
|
*/
|
||
|
|
void dac_set_waveform_characteristics(uint32_t dac, int channel, int mamp)
|
||
|
|
{
|
||
|
|
uint32_t reg = DAC_CR(dac);
|
||
|
|
switch(channel) {
|
||
|
|
case DAC_CHANNEL1:
|
||
|
|
reg &= ~(DAC_CR_MAMPx_MASK << DAC_CR_MAMP1_SHIFT);
|
||
|
|
reg |= mamp << DAC_CR_MAMP1_SHIFT;
|
||
|
|
break;
|
||
|
|
case DAC_CHANNEL2:
|
||
|
|
reg &= ~(DAC_CR_MAMPx_MASK << DAC_CR_MAMP2_SHIFT);
|
||
|
|
reg |= mamp << DAC_CR_MAMP2_SHIFT;
|
||
|
|
break;
|
||
|
|
case DAC_CHANNEL_BOTH:
|
||
|
|
reg &= ~(DAC_CR_MAMPx_MASK << DAC_CR_MAMP1_SHIFT)
|
||
|
|
| ~(DAC_CR_MAMPx_MASK << DAC_CR_MAMP2_SHIFT);
|
||
|
|
reg |= mamp << DAC_CR_MAMP1_SHIFT;
|
||
|
|
reg |= mamp << DAC_CR_MAMP2_SHIFT;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
DAC_CR(dac) = reg;
|
||
|
|
}
|
||
|
|
|
||
|
|
/** @brief Load DAC Data Register.
|
||
|
|
|
||
|
|
Loads the appropriate digital to analog converter data register with 12 or 8 bit
|
||
|
|
data to be converted on a channel. The data can be aligned as follows:
|
||
|
|
@li right-aligned 8 bit data in bits 0-7
|
||
|
|
@li right-aligned 12 bit data in bits 0-11
|
||
|
|
@li left aligned 12 bit data in bits 4-15
|
||
|
|
|
||
|
|
@param[in] dac the base address of the DAC. @ref dac_reg_base
|
||
|
|
@param[in] data uint16_t with appropriate alignment.
|
||
|
|
@param[in] align enum ::dac_align. Alignment and size.
|
||
|
|
@param[in] channel uint8_t with DAC mask.
|
||
|
|
*/
|
||
|
|
void dac_load_data_buffer_single(uint32_t dac, uint16_t data,
|
||
|
|
enum dac_align align,
|
||
|
|
int channel)
|
||
|
|
{
|
||
|
|
if (channel == DAC_CHANNEL1) {
|
||
|
|
switch (align) {
|
||
|
|
case DAC_ALIGN_RIGHT8:
|
||
|
|
DAC_DHR8R1(dac) = data;
|
||
|
|
break;
|
||
|
|
case DAC_ALIGN_RIGHT12:
|
||
|
|
DAC_DHR12R1(dac) = data;
|
||
|
|
break;
|
||
|
|
case DAC_ALIGN_LEFT12:
|
||
|
|
DAC_DHR12L1(dac) = data;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
} else if (channel == DAC_CHANNEL2) {
|
||
|
|
switch (align) {
|
||
|
|
case DAC_ALIGN_RIGHT8:
|
||
|
|
DAC_DHR8R2(dac) = data;
|
||
|
|
break;
|
||
|
|
case DAC_ALIGN_RIGHT12:
|
||
|
|
DAC_DHR12R2(dac) = data;
|
||
|
|
break;
|
||
|
|
case DAC_ALIGN_LEFT12:
|
||
|
|
DAC_DHR12L2(dac) = data;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/** @brief Load DAC Dual Data Register.
|
||
|
|
|
||
|
|
Loads the appropriate digital to analog converter dual data register with 12 or
|
||
|
|
8 bit data to be converted for both channels. This allows high bandwidth
|
||
|
|
simultaneous or independent analog output. The data in both channels are aligned
|
||
|
|
identically.
|
||
|
|
|
||
|
|
@param[in] dac the base address of the DAC. @ref dac_reg_base
|
||
|
|
@param[in] data1 uint16_t for channel 1 with appropriate alignment.
|
||
|
|
@param[in] data2 uint16_t for channel 2 with appropriate alignment.
|
||
|
|
@param[in] align enum ::dac_align. Right or left aligned, and 8 or
|
||
|
|
12 bit.
|
||
|
|
*/
|
||
|
|
void dac_load_data_buffer_dual(uint32_t dac,
|
||
|
|
uint16_t data1, uint16_t data2,
|
||
|
|
enum dac_align align)
|
||
|
|
{
|
||
|
|
switch (align) {
|
||
|
|
case DAC_ALIGN_RIGHT8:
|
||
|
|
DAC_DHR8RD(dac) = ((data1 & 0xFF) | ((data2 & 0xFF) << 8));
|
||
|
|
break;
|
||
|
|
case DAC_ALIGN_RIGHT12:
|
||
|
|
DAC_DHR12RD(dac) = ((data1 & 0xFFF) |
|
||
|
|
((data2 & 0xFFF) << 16));
|
||
|
|
break;
|
||
|
|
case DAC_ALIGN_LEFT12:
|
||
|
|
DAC_DHR12LD(dac) = ((data1 & 0xFFF) |
|
||
|
|
((data2 & 0xFFF) << 16));
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/** @brief Trigger the DAC by a Software Trigger.
|
||
|
|
|
||
|
|
If the trigger source is set to be a software trigger, cause a trigger to occur.
|
||
|
|
The trigger is cleared by hardware after conversion.
|
||
|
|
|
||
|
|
@param[in] dac the base address of the DAC. @ref dac_reg_base
|
||
|
|
@param[in] channel with DAC mask. @ref dac_channel_id
|
||
|
|
*/
|
||
|
|
void dac_software_trigger(uint32_t dac, int channel)
|
||
|
|
{
|
||
|
|
switch (channel) {
|
||
|
|
case DAC_CHANNEL1:
|
||
|
|
DAC_SWTRIGR(dac) |= DAC_SWTRIGR_SWTRIG1;
|
||
|
|
break;
|
||
|
|
case DAC_CHANNEL2:
|
||
|
|
DAC_SWTRIGR(dac) |= DAC_SWTRIGR_SWTRIG2;
|
||
|
|
break;
|
||
|
|
case DAC_CHANNEL_BOTH:
|
||
|
|
DAC_SWTRIGR(dac) |= (DAC_SWTRIGR_SWTRIG1 | DAC_SWTRIGR_SWTRIG2);
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
/**@}*/
|
||
|
|
|