520 lines
13 KiB
C
520 lines
13 KiB
C
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/** @defgroup rcc_file RCC peripheral API
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*
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* @ingroup peripheral_apis
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*
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* @section rcc_l4_api_ex Reset and Clock Control API.
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*
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* @brief <b>libopencm3 STM32L4xx Reset and Clock Control</b>
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*
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* @author @htmlonly © @endhtmlonly 2016 Karl Palsson <karlp@tweak.net.au>
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*
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* @date 12 Feb 2016
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*
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* This library supports the Reset and Clock Control System in the STM32 series
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* of ARM Cortex Microcontrollers by ST Microelectronics.
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2016 Karl Palsson <karlp@tweak.net.au>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#include <libopencm3/cm3/assert.h>
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#include <libopencm3/stm32/rcc.h>
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/* Set the default clock frequencies after reset. */
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uint32_t rcc_ahb_frequency = 4000000;
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uint32_t rcc_apb1_frequency = 4000000;
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uint32_t rcc_apb2_frequency = 4000000;
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void rcc_osc_ready_int_clear(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CICR |= RCC_CICR_PLLRDYC;
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break;
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case RCC_HSE:
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RCC_CICR |= RCC_CICR_HSERDYC;
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break;
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case RCC_HSI16:
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RCC_CICR |= RCC_CICR_HSIRDYC;
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break;
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case RCC_MSI:
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RCC_CICR |= RCC_CICR_MSIRDYC;
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break;
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case RCC_LSE:
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RCC_CICR |= RCC_CICR_LSERDYC;
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break;
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case RCC_LSI:
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RCC_CICR |= RCC_CICR_LSIRDYC;
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break;
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case RCC_HSI48:
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RCC_CICR |= RCC_CICR_HSI48RDYC;
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break;
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}
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}
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void rcc_osc_ready_int_enable(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CIER |= RCC_CIER_PLLRDYIE;
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break;
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case RCC_HSE:
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RCC_CIER |= RCC_CIER_HSERDYIE;
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break;
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case RCC_HSI16:
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RCC_CIER |= RCC_CIER_HSIRDYIE;
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break;
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case RCC_MSI:
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RCC_CIER |= RCC_CIER_MSIRDYIE;
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break;
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case RCC_LSE:
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RCC_CIER |= RCC_CIER_LSERDYIE;
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break;
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case RCC_LSI:
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RCC_CIER |= RCC_CIER_LSIRDYIE;
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break;
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case RCC_HSI48:
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RCC_CIER |= RCC_CIER_HSI48RDYIE;
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break;
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}
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}
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void rcc_osc_ready_int_disable(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CIER &= ~RCC_CIER_PLLRDYIE;
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break;
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case RCC_HSE:
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RCC_CIER &= ~RCC_CIER_HSERDYIE;
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break;
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case RCC_HSI16:
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RCC_CIER &= ~RCC_CIER_HSIRDYIE;
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break;
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case RCC_MSI:
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RCC_CIER &= ~RCC_CIER_MSIRDYIE;
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break;
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case RCC_LSE:
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RCC_CIER &= ~RCC_CIER_LSERDYIE;
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break;
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case RCC_LSI:
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RCC_CIER &= ~RCC_CIER_LSIRDYIE;
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break;
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case RCC_HSI48:
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RCC_CIER &= ~RCC_CIER_HSI48RDYIE;
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break;
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}
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}
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int rcc_osc_ready_int_flag(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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return ((RCC_CIFR & RCC_CIFR_PLLRDYF) != 0);
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break;
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case RCC_HSE:
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return ((RCC_CIFR & RCC_CIFR_HSERDYF) != 0);
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break;
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case RCC_HSI16:
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return ((RCC_CIFR & RCC_CIFR_HSIRDYF) != 0);
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break;
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case RCC_MSI:
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return ((RCC_CIFR & RCC_CIFR_MSIRDYF) != 0);
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break;
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case RCC_LSE:
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return ((RCC_CIFR & RCC_CIFR_LSERDYF) != 0);
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break;
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case RCC_LSI:
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return ((RCC_CIFR & RCC_CIFR_LSIRDYF) != 0);
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break;
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case RCC_HSI48:
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return ((RCC_CIFR & RCC_CIFR_HSI48RDYF) != 0);
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break;
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}
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return false;
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}
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void rcc_css_int_clear(void)
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{
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RCC_CICR |= RCC_CICR_CSSC;
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}
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int rcc_css_int_flag(void)
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{
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return ((RCC_CIFR & RCC_CIFR_CSSF) != 0);
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}
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bool rcc_is_osc_ready(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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return RCC_CR & RCC_CR_PLLRDY;
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case RCC_HSE:
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return RCC_CR & RCC_CR_HSERDY;
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case RCC_HSI16:
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return RCC_CR & RCC_CR_HSIRDY;
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case RCC_MSI:
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return RCC_CR & RCC_CR_MSIRDY;
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case RCC_LSE:
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return RCC_BDCR & RCC_BDCR_LSERDY;
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case RCC_LSI:
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return RCC_CSR & RCC_CSR_LSIRDY;
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case RCC_HSI48:
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return RCC_CRRCR & RCC_CRRCR_HSI48RDY;
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}
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return false;
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}
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void rcc_wait_for_osc_ready(enum rcc_osc osc)
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{
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while (!rcc_is_osc_ready(osc));
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}
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void rcc_wait_for_sysclk_status(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK)
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!= RCC_CFGR_SWS_PLL);
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break;
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case RCC_HSE:
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while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK)
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!= RCC_CFGR_SWS_HSE);
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break;
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case RCC_HSI16:
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while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK)
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!= RCC_CFGR_SWS_HSI16);
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break;
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case RCC_MSI:
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while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK)
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!= RCC_CFGR_SWS_MSI);
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break;
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default:
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/* Shouldn't be reached. */
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break;
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}
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}
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void rcc_osc_on(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CR |= RCC_CR_PLLON;
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break;
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case RCC_HSE:
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RCC_CR |= RCC_CR_HSEON;
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break;
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case RCC_HSI16:
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RCC_CR |= RCC_CR_HSION;
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break;
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case RCC_MSI:
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RCC_CR |= RCC_CR_MSION;
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break;
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case RCC_LSE:
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RCC_BDCR |= RCC_BDCR_LSEON;
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break;
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case RCC_LSI:
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RCC_CSR |= RCC_CSR_LSION;
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break;
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case RCC_HSI48:
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RCC_CRRCR |= RCC_CRRCR_HSI48ON;
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break;
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}
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}
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void rcc_osc_off(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CR &= ~RCC_CR_PLLON;
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break;
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case RCC_HSE:
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RCC_CR &= ~RCC_CR_HSEON;
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break;
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case RCC_HSI16:
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RCC_CR &= ~RCC_CR_HSION;
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break;
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case RCC_MSI:
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RCC_CR &= ~RCC_CR_MSION;
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break;
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case RCC_LSE:
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RCC_BDCR &= ~RCC_BDCR_LSEON;
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break;
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case RCC_LSI:
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RCC_CSR &= ~RCC_CSR_LSION;
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break;
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case RCC_HSI48:
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RCC_CRRCR &= ~RCC_CRRCR_HSI48ON;
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break;
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}
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}
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void rcc_css_enable(void)
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{
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RCC_CR |= RCC_CR_CSSON;
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}
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void rcc_css_disable(void)
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{
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RCC_CR &= ~RCC_CR_CSSON;
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}
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void rcc_set_sysclk_source(uint32_t clk)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~(RCC_CFGR_SW_MASK << RCC_CFGR_SW_SHIFT);
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RCC_CFGR = (reg32 | (clk << RCC_CFGR_SW_SHIFT));
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}
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void rcc_set_pll_source(uint32_t pllsrc)
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{
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uint32_t reg32;
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reg32 = RCC_PLLCFGR;
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reg32 &= ~(RCC_PLLCFGR_PLLSRC_MASK << RCC_PLLCFGR_PLLSRC_SHIFT);
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RCC_PLLCFGR = (reg32 | (pllsrc << RCC_PLLCFGR_PLLSRC_SHIFT));
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}
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void rcc_set_ppre2(uint32_t ppre2)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~(RCC_CFGR_PPRE2_MASK << RCC_CFGR_PPRE2_SHIFT);
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RCC_CFGR = (reg32 | (ppre2 << RCC_CFGR_PPRE2_SHIFT));
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}
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void rcc_set_ppre1(uint32_t ppre1)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~(RCC_CFGR_PPRE1_MASK << RCC_CFGR_PPRE1_SHIFT);
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RCC_CFGR = (reg32 | (ppre1 << RCC_CFGR_PPRE1_SHIFT));
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}
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void rcc_set_hpre(uint32_t hpre)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~(RCC_CFGR_HPRE_MASK << RCC_CFGR_HPRE_SHIFT);
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RCC_CFGR = (reg32 | (hpre << RCC_CFGR_HPRE_SHIFT));
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}
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void rcc_set_main_pll(uint32_t source, uint32_t pllm, uint32_t plln, uint32_t pllp,
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uint32_t pllq, uint32_t pllr)
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{
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RCC_PLLCFGR = (RCC_PLLCFGR_PLLM(pllm) << RCC_PLLCFGR_PLLM_SHIFT) |
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(plln << RCC_PLLCFGR_PLLN_SHIFT) |
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(pllp) |
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(source << RCC_PLLCFGR_PLLSRC_SHIFT) |
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(pllq << RCC_PLLCFGR_PLLQ_SHIFT) |
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(pllr << RCC_PLLCFGR_PLLR_SHIFT) | RCC_PLLCFGR_PLLREN;
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}
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uint32_t rcc_system_clock_source(void)
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{
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/* Return the clock source which is used as system clock. */
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return (RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK;
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}
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/**
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* Set the msi run time range.
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* Can only be called when MSI is either OFF, or when MSI is on _and_
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* ready. (RCC_CR_MSIRDY bit). @sa rcc_set_msi_range_standby
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* @param msi_range range number @ref rcc_cr_msirange
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*/
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void rcc_set_msi_range(uint32_t msi_range)
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{
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uint32_t reg = RCC_CR;
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reg &= ~(RCC_CR_MSIRANGE_MASK << RCC_CR_MSIRANGE_SHIFT);
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reg |= msi_range << RCC_CR_MSIRANGE_SHIFT;
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RCC_CR = reg | RCC_CR_MSIRGSEL;
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}
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/**
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* Set the msi range after reset/standby.
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* Until MSIRGSEl bit is set, this defines the MSI range.
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* Note that not all MSI range values are allowed here!
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* @sa rcc_set_msi_range
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* @param msi_range range number valid for post standby @ref rcc_csr_msirange
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*/
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void rcc_set_msi_range_standby(uint32_t msi_range)
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{
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uint32_t reg = RCC_CSR;
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reg &= ~(RCC_CSR_MSIRANGE_MASK << RCC_CSR_MSIRANGE_SHIFT);
|
||
|
|
reg |= msi_range << RCC_CSR_MSIRANGE_SHIFT;
|
||
|
|
RCC_CSR = reg;
|
||
|
|
}
|
||
|
|
|
||
|
|
/** Enable PLL Output
|
||
|
|
*
|
||
|
|
* - P (RCC_PLLCFGR_PLLPEN)
|
||
|
|
* - Q (RCC_PLLCFGR_PLLQEN)
|
||
|
|
* - R (RCC_PLLCFGR_PLLREN)
|
||
|
|
*
|
||
|
|
* @param pllout One or more of the definitions above
|
||
|
|
*/
|
||
|
|
void rcc_pll_output_enable(uint32_t pllout)
|
||
|
|
{
|
||
|
|
RCC_PLLCFGR |= pllout;
|
||
|
|
}
|
||
|
|
|
||
|
|
/** Set clock source for 48MHz clock
|
||
|
|
*
|
||
|
|
* The 48 MHz clock is derived from one of the four following sources:
|
||
|
|
* - main PLL VCO (RCC_CCIPR_CLK48SEL_PLL)
|
||
|
|
* - PLLSAI1 VCO (RCC_CCIPR_CLK48SEL_PLLSAI1Q)
|
||
|
|
* - MSI clock (RCC_CCIPR_CLK48SEL_MSI)
|
||
|
|
* - HSI48 internal oscillator (RCC_CCIPR_CLK48SEL_HSI48)
|
||
|
|
*
|
||
|
|
* @param clksel One of the definitions above
|
||
|
|
*/
|
||
|
|
void rcc_set_clock48_source(uint32_t clksel)
|
||
|
|
{
|
||
|
|
RCC_CCIPR &= ~(RCC_CCIPR_CLK48SEL_MASK << RCC_CCIPR_CLK48SEL_SHIFT);
|
||
|
|
RCC_CCIPR |= (clksel << RCC_CCIPR_CLK48SEL_SHIFT);
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/** Enable the RTC clock */
|
||
|
|
void rcc_enable_rtc_clock(void)
|
||
|
|
{
|
||
|
|
RCC_BDCR |= RCC_BDCR_RTCEN;
|
||
|
|
}
|
||
|
|
|
||
|
|
/** Disable the RTC clock */
|
||
|
|
void rcc_disable_rtc_clock(void)
|
||
|
|
{
|
||
|
|
RCC_BDCR &= ~RCC_BDCR_RTCEN;
|
||
|
|
}
|
||
|
|
|
||
|
|
/** Set the source for the RTC clock
|
||
|
|
* @param[in] clk ::rcc_osc. RTC clock source. Only HSE/32, LSE and LSI.
|
||
|
|
*/
|
||
|
|
void rcc_set_rtc_clock_source(enum rcc_osc clk)
|
||
|
|
{
|
||
|
|
RCC_BDCR &= ~(RCC_BDCR_RTCSEL_MASK << RCC_BDCR_RTCSEL_SHIFT);
|
||
|
|
|
||
|
|
switch (clk) {
|
||
|
|
case RCC_HSE:
|
||
|
|
RCC_BDCR |= (RCC_BDCR_RTCSEL_HSEDIV32 << RCC_BDCR_RTCSEL_SHIFT);
|
||
|
|
break;
|
||
|
|
case RCC_LSE:
|
||
|
|
RCC_BDCR |= (RCC_BDCR_RTCSEL_LSE << RCC_BDCR_RTCSEL_SHIFT);
|
||
|
|
break;
|
||
|
|
case RCC_LSI:
|
||
|
|
RCC_BDCR |= (RCC_BDCR_RTCSEL_LSI << RCC_BDCR_RTCSEL_SHIFT);
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
/* none selected */
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Helper to calculate the frequency of a UART/I2C based on the apb and clksel value. */
|
||
|
|
static uint32_t rcc_uart_i2c_clksel_freq_hz(uint32_t apb_clk, uint8_t shift) {
|
||
|
|
uint8_t clksel = (RCC_CCIPR >> shift) & RCC_CCIPR_USARTxSEL_MASK;
|
||
|
|
uint8_t hpre = (RCC_CFGR >> RCC_CFGR_HPRE_SHIFT) & RCC_CFGR_HPRE_MASK;
|
||
|
|
switch (clksel) {
|
||
|
|
case RCC_CCIPR_USARTxSEL_APB:
|
||
|
|
return apb_clk;
|
||
|
|
case RCC_CCIPR_USARTxSEL_SYS:
|
||
|
|
return rcc_ahb_frequency * rcc_get_div_from_hpre(hpre);
|
||
|
|
case RCC_CCIPR_USARTxSEL_HSI16:
|
||
|
|
return 16000000U;
|
||
|
|
}
|
||
|
|
cm3_assert_not_reached();
|
||
|
|
}
|
||
|
|
|
||
|
|
/*---------------------------------------------------------------------------*/
|
||
|
|
/** @brief Get the peripheral clock speed for the USART at base specified.
|
||
|
|
* @param usart Base address of USART to get clock frequency for.
|
||
|
|
*/
|
||
|
|
uint32_t rcc_get_usart_clk_freq(uint32_t usart)
|
||
|
|
{
|
||
|
|
/* Handle values with selectable clocks. */
|
||
|
|
if (usart == LPUART1_BASE) {
|
||
|
|
return rcc_uart_i2c_clksel_freq_hz(rcc_apb2_frequency, RCC_CCIPR_LPUART1SEL_SHIFT);
|
||
|
|
} else if (usart == USART1_BASE) {
|
||
|
|
return rcc_uart_i2c_clksel_freq_hz(rcc_apb1_frequency, RCC_CCIPR_USART1SEL_SHIFT);
|
||
|
|
} else if (usart == USART2_BASE) {
|
||
|
|
return rcc_uart_i2c_clksel_freq_hz(rcc_apb1_frequency, RCC_CCIPR_USART2SEL_SHIFT);
|
||
|
|
} else if (usart == USART3_BASE) {
|
||
|
|
return rcc_uart_i2c_clksel_freq_hz(rcc_apb1_frequency, RCC_CCIPR_USART3SEL_SHIFT);
|
||
|
|
} else if (usart == UART4_BASE) {
|
||
|
|
return rcc_uart_i2c_clksel_freq_hz(rcc_apb1_frequency, RCC_CCIPR_UART4SEL_SHIFT);
|
||
|
|
} else { /* USART5 */
|
||
|
|
return rcc_uart_i2c_clksel_freq_hz(rcc_apb1_frequency, RCC_CCIPR_UART5SEL_SHIFT);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*---------------------------------------------------------------------------*/
|
||
|
|
/** @brief Get the peripheral clock speed for the Timer at base specified.
|
||
|
|
* @param timer Base address of TIM to get clock frequency for.
|
||
|
|
*/
|
||
|
|
uint32_t rcc_get_timer_clk_freq(uint32_t timer)
|
||
|
|
{
|
||
|
|
/* Handle APB1 timers, and apply multiplier if necessary. */
|
||
|
|
if (timer >= TIM2_BASE && timer <= TIM7_BASE) {
|
||
|
|
uint8_t ppre1 = (RCC_CFGR >> RCC_CFGR_PPRE1_SHIFT) & RCC_CFGR_PPRE1_MASK;
|
||
|
|
return (ppre1 == RCC_CFGR_PPRE1_NODIV) ? rcc_apb1_frequency
|
||
|
|
: 2 * rcc_apb1_frequency;
|
||
|
|
} else {
|
||
|
|
uint8_t ppre2 = (RCC_CFGR >> RCC_CFGR_PPRE2_SHIFT) & RCC_CFGR_PPRE2_MASK;
|
||
|
|
return (ppre2 == RCC_CFGR_PPRE2_NODIV) ? rcc_apb2_frequency
|
||
|
|
: 2 * rcc_apb2_frequency;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*---------------------------------------------------------------------------*/
|
||
|
|
/** @brief Get the peripheral clock speed for the I2C device at base specified.
|
||
|
|
* @param i2c Base address of I2C to get clock frequency for.
|
||
|
|
*/
|
||
|
|
uint32_t rcc_get_i2c_clk_freq(uint32_t i2c)
|
||
|
|
{
|
||
|
|
if (i2c == I2C1_BASE) {
|
||
|
|
return rcc_uart_i2c_clksel_freq_hz(rcc_apb1_frequency, RCC_CCIPR_I2C1SEL_SHIFT);
|
||
|
|
} else if (i2c == I2C2_BASE) {
|
||
|
|
return rcc_uart_i2c_clksel_freq_hz(rcc_apb1_frequency, RCC_CCIPR_I2C2SEL_SHIFT);
|
||
|
|
} else { /* I2C3 */
|
||
|
|
return rcc_uart_i2c_clksel_freq_hz(rcc_apb1_frequency, RCC_CCIPR_I2C3SEL_SHIFT);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*---------------------------------------------------------------------------*/
|
||
|
|
/** @brief Get the peripheral clock speed for the SPI device at base specified.
|
||
|
|
* @param spi Base address of SPI device to get clock frequency for (e.g. SPI1_BASE).
|
||
|
|
*/
|
||
|
|
uint32_t rcc_get_spi_clk_freq(uint32_t spi) {
|
||
|
|
if (spi == SPI1_BASE) {
|
||
|
|
return rcc_apb2_frequency;
|
||
|
|
} else {
|
||
|
|
return rcc_apb1_frequency;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
/**@}*/
|