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  origin:   "https://github.com/libopencm3/libopencm3"
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  commit:   "f5813a54"
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Arti Zirk
2021-09-30 16:34:10 +03:00
parent 1a441e5806
commit 244fdbc35c
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63
libopencm3/lib/stm32/f3/Makefile Normal file
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##
## This file is part of the libopencm3 project.
##
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
##
## This library is free software: you can redistribute it and/or modify
## it under the terms of the GNU Lesser General Public License as published by
## the Free Software Foundation, either version 3 of the License, or
## (at your option) any later version.
##
## This library is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU Lesser General Public License for more details.
##
## You should have received a copy of the GNU Lesser General Public License
## along with this library. If not, see <http://www.gnu.org/licenses/>.
##
LIBNAME = libopencm3_stm32f3
SRCLIBDIR ?= ../..
FP_FLAGS ?= -mfloat-abi=hard -mfpu=fpv4-sp-d16
CC = $(PREFIX)gcc
AR = $(PREFIX)ar
TGT_CFLAGS = -Os \
-Wall -Wextra -Wimplicit-function-declaration \
-Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \
-Wundef -Wshadow \
-I../../../include -fno-common \
-mcpu=cortex-m4 -mthumb $(FP_FLAGS) -Wstrict-prototypes \
-ffunction-sections -fdata-sections -MD -DSTM32F3
TGT_CFLAGS += $(DEBUG_FLAGS)
TGT_CFLAGS += $(STANDARD_FLAGS)
ARFLAGS = rcs
OBJS += adc.o adc_common_v2.o adc_common_v2_multi.o
OBJS += can.o
OBJS += crc_common_all.o crc_v2.o
OBJS += dac_common_all.o dac_common_v1.o
OBJS += desig_common_all.o desig_common_v1.o
OBJS += dma_common_l1f013.o
OBJS += exti_common_all.o
OBJS += flash.o flash_common_all.o flash_common_f.o
OBJS += gpio_common_all.o gpio_common_f0234.o
OBJS += i2c_common_v2.o
OBJS += iwdg_common_all.o
OBJS += opamp_common_all.o opamp_common_v1.o
OBJS += pwr_common_v1.o
OBJS += rcc.o rcc_common_all.o
OBJS += spi_common_all.o spi_common_v2.o
OBJS += timer_common_all.o timer_common_f0234.o
OBJS += usart_common_v2.o usart_common_all.o
OBJS += usb.o usb_control.o usb_standard.o usb_msc.o
OBJS += usb_hid.o
OBJS += usb_audio.o usb_cdc.o usb_midi.o
OBJS += st_usbfs_core.o st_usbfs_v1.o
VPATH += ../../usb:../:../../cm3:../common
include ../../Makefile.include

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libopencm3/lib/stm32/f3/adc.c Normal file
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/** @addtogroup adc_file ADC peripheral API
* @ingroup peripheral_apis
*
* @author @htmlonly &copy; @endhtmlonly 2012
* Ken Sarkies <ksarkies@internode.on.net>
*
* @date 30 August 2012
*
* This library supports the A/D Converter Control System in the STM32 series
* of ARM Cortex Microcontrollers by ST Microelectronics.
*
* Devices can have up to three A/D converters each with their own set of
* registers. However all the A/D converters share a common clock which is
* prescaled from the APB2 clock by default by a minimum factor of 2 to a
* maximum of 8. The ADC resolution can be set to 12, 10, 8 or 6 bits.
*
* Each A/D converter has up to 19 channels:
* @li On ADC1 the analog channels 16 is internally connected to the
* temperature sensor, channel 17 to V<sub>REFINT</sub>, and channel 18
* to V<sub>BATT</sub>.
* @li On ADC2 and ADC3 the analog channels 16 - 18 are not used.
*
* The conversions can occur as a one-off conversion whereby the process stops
* once conversion is complete. The conversions can also be continuous wherein
* a new conversion starts immediately the previous conversion has ended.
*
* Conversion can occur as a single channel conversion or a scan of a group of
* channels in either continuous or one-off mode. If more than one channel is
* converted in a scan group, DMA must be used to transfer the data as there is
* only one result register available. An interrupt can be set to occur at the
* end*
* of conversion, which occurs after all channels have been scanned.
*
* A discontinuous mode allows a subgroup of group of a channels to be
* converted in bursts of a given length.
*
* Injected conversions allow a second group of channels to be converted
* separately from the regular group. An interrupt can be set to occur at the
* end of conversion, which occurs after all channels have been scanned.
*
* @section adc_f3_api_ex Basic ADC Handling API.
*
* Example 1: Simple single channel conversion polled. Enable the peripheral
* clock and ADC, reset ADC and set the prescaler divider. Set multiple mode to
* independent.
*
* @code
* gpio_mode_setup(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO1);
* rcc_periph_clock_enable(RCC_ADC1);
* adc_set_clk_prescale(RCC_CFGR_ADCPRE_BY2);
* adc_disable_scan_mode(ADC1);
* adc_set_single_conversion_mode(ADC1);
* adc_set_sample_time(ADC1, ADC_CHANNEL0, ADC_SMPR1_SMP_1DOT5CYC);
* uint8_t channels[] = ADC_CHANNEL0;
* adc_set_regular_sequence(ADC1, 1, channels);
* adc_set_multi_mode(ADC_CCR_DUAL_INDEPENDENT);
* adc_power_on(ADC1);
* adc_start_conversion_regular(ADC1);
* while (! adc_eoc(ADC1));
* reg16 = adc_read_regular(ADC1);
* @endcode
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#include <libopencm3/stm32/adc.h>
/**@{*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Analog Watchdog for Regular Conversions
*
* The analog watchdog allows the monitoring of an analog signal between two
* threshold levels. The thresholds must be preset. Comparison is done before
* data alignment takes place, so the thresholds are left-aligned.
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_enable_analog_watchdog_regular(uint32_t adc)
{
ADC_CFGR1(adc) |= ADC_CFGR1_AWD1EN;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Analog Watchdog for Regular Conversions
*
* The analog watchdog allows the monitoring of an analog signal between two
* threshold levels. The thresholds must be preset. Comparison is done before
* data alignment takes place, so the thresholds are left-aligned.
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_disable_analog_watchdog_regular(uint32_t adc)
{
ADC_CFGR1(adc) &= ~ADC_CFGR1_AWD1EN;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Analog Watchdog for Injected Conversions
*
* The analog watchdog allows the monitoring of an analog signal between two
* threshold levels. The thresholds must be preset. Comparison is done before
* data alignment takes place, so the thresholds are left-aligned.
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_enable_analog_watchdog_injected(uint32_t adc)
{
ADC_CFGR1(adc) |= ADC_CFGR1_JAWD1EN;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable Analog Watchdog for Injected Conversions
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_disable_analog_watchdog_injected(uint32_t adc)
{
ADC_CFGR1(adc) &= ~ADC_CFGR1_JAWD1EN;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Discontinuous Mode for Regular Conversions
*
* In this mode the ADC converts, on each trigger, a subgroup of up to 8 of the
* defined regular channel group. The subgroup is defined by the number of
* consecutive channels to be converted. After a subgroup has been converted
* the next trigger will start conversion of the immediately following subgroup
* of the same length or until the whole group has all been converted. When the
* whole group has been converted, the next trigger will restart conversion of
* the subgroup at the beginning of the whole group.
*
* @param[in] adc ADC block register address base @ref adc_reg_base
* @param[in] length Number of channels in the group @ref adc_cr1_discnum
*/
void adc_enable_discontinuous_mode_regular(uint32_t adc, uint8_t length)
{
if ((length-1) > 7) {
return;
}
ADC_CFGR1(adc) |= ADC_CFGR1_DISCEN;
ADC_CFGR1(adc) |= ((length-1) << ADC_CFGR1_DISCNUM_SHIFT);
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable Discontinuous Mode for Regular Conversions
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_disable_discontinuous_mode_regular(uint32_t adc)
{
ADC_CFGR1(adc) &= ~ADC_CFGR1_DISCEN;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Discontinuous Mode for Injected Conversions
*
* In this mode the ADC converts sequentially one channel of the defined group
* of injected channels, cycling back to the first channel in the group once
* the entire group has been converted.
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_enable_discontinuous_mode_injected(uint32_t adc)
{
ADC_CFGR1(adc) |= ADC_CFGR1_JDISCEN;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable Discontinuous Mode for Injected Conversions
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_disable_discontinuous_mode_injected(uint32_t adc)
{
ADC_CFGR1(adc) &= ~ADC_CFGR1_JDISCEN;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Automatic Injected Conversions
*
* The ADC converts a defined injected group of channels immediately after the
* regular channels have been converted. The external trigger on the injected
* channels is disabled as required.
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_enable_automatic_injected_group_conversion(uint32_t adc)
{
adc_disable_external_trigger_injected(adc);
ADC_CFGR1(adc) |= ADC_CFGR1_JAUTO;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable Automatic Injected Conversions
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_disable_automatic_injected_group_conversion(uint32_t adc)
{
ADC_CFGR1(adc) &= ~ADC_CFGR1_JAUTO;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Analog Watchdog for All Regular and/or Injected Channels
*
* The analog watchdog allows the monitoring of an analog signal between two
* threshold levels. The thresholds must be preset. Comparison is done before
* data alignment takes place, so the thresholds are left-aligned.
*
* @note The analog watchdog must be enabled for either or both of the regular
* or injected channels. If neither are enabled, the analog watchdog feature
* will be disabled.
*
* @ref adc_enable_analog_watchdog_injected, @ref
* adc_enable_analog_watchdog_regular.
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_enable_analog_watchdog_on_all_channels(uint32_t adc)
{
ADC_CFGR1(adc) &= ~ADC_CFGR1_AWD1SGL;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Analog Watchdog for a Selected Channel
*
* The analog watchdog allows the monitoring of an analog signal between two
* threshold levels. The thresholds must be preset. Comparison is done before
* data alignment takes place, so the thresholds are left-aligned.
*
* @note The analog watchdog must be enabled for either or both of the regular
* or injected channels. If neither are enabled, the analog watchdog feature
* will be disabled. If both are enabled, the same channel number is monitored
* @ref adc_enable_analog_watchdog_injected, @ref
* adc_enable_analog_watchdog_regular.
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
* @param[in] channel Unsigned int8. ADC channel numbe
* @ref adc_watchdog_channel
*/
void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc,
uint8_t channel)
{
ADC_CFGR1(adc) = (ADC_CFGR1(adc) & ~ADC_CFGR1_AWD1CH) |
ADC_CFGR1_AWD1CH_VAL(channel);
ADC_CFGR1(adc) |= ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Injected End-Of-Conversion Interrupt
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_enable_eoc_interrupt_injected(uint32_t adc)
{
ADC_IER(adc) |= ADC_IER_JEOCIE;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable Injected End-Of-Conversion Interrupt
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_disable_eoc_interrupt_injected(uint32_t adc)
{
ADC_IER(adc) &= ~ADC_IER_JEOCIE;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Injected End-Of-Sequence Interrupt
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_enable_eos_interrupt_injected(uint32_t adc)
{
ADC_IER(adc) |= ADC_IER_JEOSIE;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable Injected End-Of-Sequence Interrupt
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_disable_eos_interrupt_injected(uint32_t adc)
{
ADC_IER(adc) &= ~ADC_IER_JEOSIE;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Analog Watchdog Interrupt
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_enable_all_awd_interrupt(uint32_t adc)
{
ADC_IER(adc) |= ADC_IER_AWD1IE;
ADC_IER(adc) |= ADC_IER_AWD2IE;
ADC_IER(adc) |= ADC_IER_AWD3IE;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable Analog Watchdog Interrupt
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_disable_all_awd_interrupt(uint32_t adc)
{
ADC_IER(adc) &= ~ADC_IER_AWD1IE;
ADC_IER(adc) &= ~ADC_IER_AWD2IE;
ADC_IER(adc) &= ~ADC_IER_AWD3IE;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Regular End-Of-Sequence Interrupt
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_enable_eos_interrupt(uint32_t adc)
{
ADC_IER(adc) |= ADC_IER_EOSIE;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable Regular End-Of-Sequence Interrupt
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_disable_eos_interrupt(uint32_t adc)
{
ADC_IER(adc) &= ~ADC_IER_EOSIE;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Software Triggered Conversion on Injected Channels
*
* This starts conversion on a set of defined injected channels.
* Depending on the configuration bits JEXTEN, a conversion will start
* immediately (software trigger configuration) or once an injected hardware
* trigger event occurs (hardware trigger configuration).
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_start_conversion_injected(uint32_t adc)
{
/* Start conversion on injected channels. */
ADC_CR(adc) |= ADC_CR_JADSTART;
}
/** ADC Set Analog Watchdog Upper Threshold.
* @param[in] adc ADC block register address base
* @ref adc_reg_base
* @param[in] threshold Upper threshold value
*/
void adc_set_watchdog_high_threshold(uint32_t adc, uint16_t threshold)
{
uint32_t reg32 = 0;
uint32_t mask = 0xf000ffff;
reg32 |= (threshold << 16);
reg32 &= ~mask; /* clear masked bits. */
ADC_TR1(adc) = (ADC_TR1(adc) & mask) | reg32;
ADC_TR2(adc) = (ADC_TR2(adc) & mask) | reg32;
ADC_TR3(adc) = (ADC_TR3(adc) & mask) | reg32;
}
/** ADC Set Analog Watchdog Lower Threshold.
* @param[in] adc ADC block register address base
* @ref adc_reg_base
* @param[in] threshold Lower threshold value
*/
void adc_set_watchdog_low_threshold(uint32_t adc, uint16_t threshold)
{
uint32_t reg32 = 0;
uint32_t mask = 0xfffff000;
reg32 = (uint32_t)threshold;
reg32 &= ~mask; /* clear masked bits. */
ADC_TR1(adc) = (ADC_TR1(adc) & mask) | reg32;
ADC_TR2(adc) = (ADC_TR2(adc) & mask) | reg32;
ADC_TR3(adc) = (ADC_TR3(adc) & mask) | reg32;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Set an Injected Channel Conversion Sequence
*
* Defines a sequence of channels to be converted as an injected group with a
* length from 1 to 4 channels. If this is called during conversion, the current
* conversion is reset and conversion begins again with the newly defined group.
*
* @param[in] adc Unsigned int32. ADC block register address base
* @ref adc_reg_base
* @param[in] length Unsigned int8. Number of channels in the group.
* @param[in] channel Unsigned int8[]. Set of channels in sequence, integers
* 0..18
*/
void adc_set_injected_sequence(uint32_t adc, uint8_t length, uint8_t channel[])
{
uint32_t reg32 = 0;
uint8_t i = 0;
/* Maximum sequence length is 4 channels. Minimum sequence is 1.*/
if ((length - 1) > 3) {
return;
}
for (i = 0; i < length; i++) {
reg32 |= ADC_JSQR_JSQ_VAL(4 - i, channel[length - i - 1]);
}
reg32 |= ADC_JSQR_JL_VAL(length);
ADC_JSQR(adc) = reg32;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Read the End-of-Conversion Flag for Injected Conversion
*
* This flag is set by hardware at the end of each injected conversion of a
* channel when a new data is available in the corresponding ADCx_JDRy register.
*
* @param[in] adc Unsigned int32. ADC block register address base
* @ref adc_reg_base
* @returns bool. End of conversion flag.
*/
bool adc_eoc_injected(uint32_t adc)
{
return ADC_ISR(adc) & ADC_ISR_JEOC;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Read the End-of-Sequence Flag for Injected Conversions
*
* This flag is set after all channels of an injected group have been
* converted.
*
* @param[in] adc Unsigned int32. ADC block register address base
* @ref adc_reg_base
* @returns bool. End of conversion flag.
*/
bool adc_eos_injected(uint32_t adc)
{
return ADC_ISR(adc) & ADC_ISR_JEOS;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Read from an Injected Conversion Result Register
*
* The result read back from the selected injected result register (one of four)
* is 12 bits, right or left aligned within the first 16 bits. The result can
* have a negative value if the injected channel offset has been set @see
* adc_set_injected_offset.
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
* @param[in] reg Unsigned int8. Register number (1 ... 4).
* @returns Unsigned int32 conversion result.
*/
uint32_t adc_read_injected(uint32_t adc, uint8_t reg)
{
switch (reg) {
case 1:
return ADC_JDR1(adc);
case 2:
return ADC_JDR2(adc);
case 3:
return ADC_JDR3(adc);
case 4:
return ADC_JDR4(adc);
}
return 0;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Set the Injected Channel Data Offset
*
* This value is subtracted from the injected channel results after conversion
* is complete, and can result in negative results. A separate value can be
* specified for each injected data register.
*
* @param[in] adc Unsigned int32. ADC block register address base
* @ref adc_reg_base
* @param[in] reg Unsigned int8. Register number (1 ... 4).
* @param[in] offset Unsigned int32.
*/
void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset)
{
switch (reg) {
case 1:
ADC_OFR1(adc) |= ADC_OFR1_OFFSET1_EN;
ADC_OFR1(adc) |= offset;
break;
case 2:
ADC_OFR2(adc) |= ADC_OFR2_OFFSET2_EN;
ADC_OFR2(adc) |= offset;
break;
case 3:
ADC_OFR3(adc) |= ADC_OFR3_OFFSET3_EN;
ADC_OFR3(adc) |= offset;
break;
case 4:
ADC_OFR4(adc) |= ADC_OFR4_OFFSET4_EN;
ADC_OFR4(adc) |= offset;
break;
}
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Set Clock Prescale
*
* The ADC clock taken from the APB2 clock can be scaled down by 2, 4, 6 or 8.
*
* @param adc peripheral of choice @ref adc_reg_base
* @param[in] prescale Unsigned int32. Prescale value for ADC Clock @ref
* adc_ccr_adcpre
*/
void adc_set_clk_prescale(uint32_t adc, uint32_t prescale)
{
uint32_t reg32 = ((ADC_CCR(adc) & ~ADC_CCR_CKMODE_MASK) | prescale);
ADC_CCR(adc) = reg32;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC set multi mode
*
* The multiple mode can uses these arrangement:
* - ADC1 as master and ADC2 as slave
* - ADC3 as master and ADC4 as slave
*
* This setting is applied to ADC master only (ADC1 or ADC3).
*
* The various modes possible are described in the reference manual.
*
* @param adc peripheral of choice @ref adc_reg_base
* @param[in] mode Multiple mode selection from @ref adc_multi_mode
*/
void adc_set_multi_mode(uint32_t adc, uint32_t mode)
{
ADC_CCR(adc) &= ~(ADC_CCR_DUAL_MASK << ADC_CCR_DUAL_SHIFT);
ADC_CCR(adc) |= (mode << ADC_CCR_DUAL_SHIFT);
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable an External Trigger for Regular Channels
*
* This enables an external trigger for set of defined regular channels, and
* sets the polarity of the trigger event: rising or falling edge or both. Note
* that if the trigger polarity is zero, triggering is disabled.
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
* @param[in] trigger Unsigned int32. Trigger identifier
* @ref adc_trigger_regular
* @param[in] polarity Unsigned int32. Trigger polarity @ref
* adc_trigger_polarity_regular
*/
void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger,
uint32_t polarity)
{
uint32_t reg32 = ADC_CFGR1(adc);
reg32 &= ~(ADC_CFGR1_EXTSEL_MASK | ADC_CFGR1_EXTEN_MASK);
reg32 |= (trigger | polarity);
ADC_CFGR1(adc) = reg32;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable an External Trigger for Regular Channels
*
* @param[in] adc Unsigned int32. ADC block register address base
* @ref adc_reg_base
*/
void adc_disable_external_trigger_regular(uint32_t adc)
{
ADC_CFGR1(adc) &= ~ADC_CFGR1_EXTEN_MASK;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable an External Trigger for Injected Channels
*
* This enables an external trigger for set of defined injected channels, and
* sets the polarity of the trigger event: rising or falling edge or both.
*
* @param[in] adc Unsigned int32. ADC block register address base
* @ref adc_reg_base
* @param[in] trigger Unsigned int8. Trigger identifier
* @ref adc_trigger_injected
* @param[in] polarity Unsigned int32. Trigger polarity
* @ref adc_trigger_polarity_injected
*/
void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger,
uint32_t polarity)
{
uint32_t reg32 = ADC_JSQR(adc);
reg32 &= ~(ADC_JSQR_JEXTSEL_MASK | ADC_JSQR_JEXTEN_MASK);
reg32 |= (trigger | polarity);
ADC_JSQR(adc) = reg32;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable an External Trigger for Injected Channels
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_disable_external_trigger_injected(uint32_t adc)
{
ADC_JSQR(adc) &= ~ADC_JSQR_JEXTEN_MASK;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Read the Analog Watchdog Flag
*
* This flag is set when the converted voltage crosses the high or low
* thresholds.
*
* @param[in] adc Unsigned int32. ADC block register address base
* @ref adc_reg_base
* @returns bool. AWD flag.
*/
bool adc_awd(uint32_t adc)
{
return (ADC_ISR(adc) & ADC_ISR_AWD1) &&
(ADC_ISR(adc) & ADC_ISR_AWD2) &&
(ADC_ISR(adc) & ADC_ISR_AWD3);
}
/**
* Enable the ADC Voltage regulator
* Before any use of the ADC, the ADC Voltage regulator must be enabled.
* You must wait up to 10uSecs afterwards before trying anything else.
* @param[in] adc ADC block register address base
* @sa adc_disable_regulator
*/
void adc_enable_regulator(uint32_t adc)
{
ADC_CR(adc) &= ~ADC_CR_ADVREGEN_MASK;
ADC_CR(adc) |= ADC_CR_ADVREGEN_ENABLE;
}
/**
* Disable the ADC Voltage regulator
* You can disable the adc vreg when not in use to save power
* @param[in] adc ADC block register address base
* @sa adc_enable_regulator
*/
void adc_disable_regulator(uint32_t adc)
{
ADC_CR(adc) &= ~ADC_CR_ADVREGEN_MASK;
ADC_CR(adc) |= ADC_CR_ADVREGEN_DISABLE;
}
/**@}*/

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/** @defgroup flash_file FLASH peripheral API
*
* @ingroup peripheral_apis
*
* @brief <b>libopencm3 STM32F3xx FLASH</b>
*
* @version 1.0.0
*
* @author @htmlonly &copy; @endhtmlonly 2010
* Thomas Otto <tommi@viadmin.org>
* @author @htmlonly &copy; @endhtmlonly 2010
* Mark Butler <mbutler@physics.otago.ac.nz>
*
* @date 14 January 2014
*
* This library supports the FLASH memory controller in the STM32F3
* series of ARM Cortex Microcontrollers by ST Microelectronics.
*
* For the STM32F3xx, accessing FLASH memory is described in
* section 3 of the STM32F3xx Reference Manual.
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
* Copyright (C) 2010 Mark Butler <mbutler@physics.otago.ac.nz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
#include <libopencm3/stm32/flash.h>
void flash_wait_for_last_operation(void)
{
while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY);
}
void flash_clear_pgerr_flag(void)
{
FLASH_SR |= FLASH_SR_PGERR;
}
void flash_clear_wrprterr_flag(void)
{
FLASH_SR |= FLASH_SR_WRPRTERR;
}
/*---------------------------------------------------------------------------*/
/** @brief Clear All Status Flags
Clears program error, end of operation, busy flags.
*/
void flash_clear_status_flags(void)
{
flash_clear_pgerr_flag();
flash_clear_wrprterr_flag();
flash_clear_eop_flag();
}
void flash_program_half_word(uint32_t address, uint16_t data)
{
flash_wait_for_last_operation();
FLASH_CR |= FLASH_CR_PG;
MMIO16(address) = data;
flash_wait_for_last_operation();
FLASH_CR &= ~FLASH_CR_PG;
}
void flash_erase_page(uint32_t page_address)
{
flash_wait_for_last_operation();
FLASH_CR |= FLASH_CR_PER;
FLASH_AR = page_address;
FLASH_CR |= FLASH_CR_STRT;
flash_wait_for_last_operation();
FLASH_CR &= ~FLASH_CR_PER;
}
void flash_erase_all_pages(void)
{
flash_wait_for_last_operation();
FLASH_CR |= FLASH_CR_MER;
FLASH_CR |= FLASH_CR_STRT;
flash_wait_for_last_operation();
FLASH_CR &= ~FLASH_CR_MER;
}
/**@}*/

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/** @defgroup i2c_file I2C
*
* @ingroup STM32F3xx
*
* @brief <b>libopencm3 STM32F3xx I2C</b>
*
* @version 1.0.0
*
* @date 15 October 2012
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#include <libopencm3/stm32/i2c.h>

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/** @defgroup rcc_file RCC peripheral API
*
* @ingroup peripheral_apis
*
* @brief <b>libopencm3 STM32F3xx Reset and Clock Control</b>
*
* @version 1.0.0
*
* @date 11 July 2013
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
* Modified by 2013 Fernando Cortes <fernando.corcam@gmail.com> (stm32f3)
* Modified by 2013 Guillermo Rivera <memogrg@gmail.com> (stm32f3)
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
#include <libopencm3/cm3/assert.h>
#include <libopencm3/stm32/rcc.h>
#include <libopencm3/stm32/flash.h>
#include <libopencm3/stm32/i2c.h>
/* Set the default clock frequencies after reset. */
uint32_t rcc_ahb_frequency = 8000000;
uint32_t rcc_apb1_frequency = 8000000;
uint32_t rcc_apb2_frequency = 8000000;
const struct rcc_clock_scale rcc_hsi_configs[] = {
{ /* 48MHz */
.pllmul = RCC_CFGR_PLLMUL_MUL12,
.pllsrc = RCC_CFGR_PLLSRC_HSI_DIV2,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPRE_DIV2,
.ppre2 = RCC_CFGR_PPRE_NODIV,
.flash_waitstates = 1,
.ahb_frequency = 48000000,
.apb1_frequency = 24000000,
.apb2_frequency = 48000000,
},
{ /* 64MHz */
.pllmul = RCC_CFGR_PLLMUL_MUL16,
.pllsrc = RCC_CFGR_PLLSRC_HSI_DIV2,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPRE_DIV2,
.ppre2 = RCC_CFGR_PPRE_NODIV,
.flash_waitstates = 2,
.ahb_frequency = 64000000,
.apb1_frequency = 32000000,
.apb2_frequency = 64000000,
}
};
const struct rcc_clock_scale rcc_hse8mhz_configs[] = {
{
.pllsrc = RCC_CFGR_PLLSRC_HSE_PREDIV,
.pllmul = RCC_CFGR_PLLMUL_MUL9,
.plldiv = RCC_CFGR2_PREDIV_NODIV,
.usbdiv1 = false,
.flash_waitstates = 2,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPRE_DIV2,
.ppre2 = RCC_CFGR_PPRE_NODIV,
.ahb_frequency = 72e6,
.apb1_frequency = 36e6,
.apb2_frequency = 72e6,
}
};
void rcc_osc_ready_int_clear(enum rcc_osc osc)
{
switch (osc) {
case RCC_PLL:
RCC_CIR |= RCC_CIR_PLLRDYC;
break;
case RCC_HSE:
RCC_CIR |= RCC_CIR_HSERDYC;
break;
case RCC_HSI:
RCC_CIR |= RCC_CIR_HSIRDYC;
break;
case RCC_LSE:
RCC_CIR |= RCC_CIR_LSERDYC;
break;
case RCC_LSI:
RCC_CIR |= RCC_CIR_LSIRDYC;
break;
}
}
void rcc_osc_ready_int_enable(enum rcc_osc osc)
{
switch (osc) {
case RCC_PLL:
RCC_CIR |= RCC_CIR_PLLRDYIE;
break;
case RCC_HSE:
RCC_CIR |= RCC_CIR_HSERDYIE;
break;
case RCC_HSI:
RCC_CIR |= RCC_CIR_HSIRDYIE;
break;
case RCC_LSE:
RCC_CIR |= RCC_CIR_LSERDYIE;
break;
case RCC_LSI:
RCC_CIR |= RCC_CIR_LSIRDYIE;
break;
}
}
void rcc_osc_ready_int_disable(enum rcc_osc osc)
{
switch (osc) {
case RCC_PLL:
RCC_CIR &= ~RCC_CIR_PLLRDYIE;
break;
case RCC_HSE:
RCC_CIR &= ~RCC_CIR_HSERDYIE;
break;
case RCC_HSI:
RCC_CIR &= ~RCC_CIR_HSIRDYIE;
break;
case RCC_LSE:
RCC_CIR &= ~RCC_CIR_LSERDYIE;
break;
case RCC_LSI:
RCC_CIR &= ~RCC_CIR_LSIRDYIE;
break;
}
}
int rcc_osc_ready_int_flag(enum rcc_osc osc)
{
switch (osc) {
case RCC_PLL:
return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0);
break;
case RCC_HSE:
return ((RCC_CIR & RCC_CIR_HSERDYF) != 0);
break;
case RCC_HSI:
return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0);
break;
case RCC_LSE:
return ((RCC_CIR & RCC_CIR_LSERDYF) != 0);
break;
case RCC_LSI:
return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0);
break;
}
cm3_assert_not_reached();
}
void rcc_css_int_clear(void)
{
RCC_CIR |= RCC_CIR_CSSC;
}
int rcc_css_int_flag(void)
{
return ((RCC_CIR & RCC_CIR_CSSF) != 0);
}
bool rcc_is_osc_ready(enum rcc_osc osc)
{
switch (osc) {
case RCC_PLL:
return RCC_CR & RCC_CR_PLLRDY;
case RCC_HSE:
return RCC_CR & RCC_CR_HSERDY;
case RCC_HSI:
return RCC_CR & RCC_CR_HSIRDY;
case RCC_LSE:
return RCC_BDCR & RCC_BDCR_LSERDY;
case RCC_LSI:
return RCC_CSR & RCC_CSR_LSIRDY;
}
return false;
}
void rcc_wait_for_osc_ready(enum rcc_osc osc)
{
while (!rcc_is_osc_ready(osc));
}
void rcc_wait_for_osc_not_ready(enum rcc_osc osc)
{
while (rcc_is_osc_ready(osc));
}
void rcc_wait_for_sysclk_status(enum rcc_osc osc)
{
switch (osc) {
case RCC_PLL:
while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK) !=
RCC_CFGR_SWS_PLL);
break;
case RCC_HSE:
while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK) !=
RCC_CFGR_SWS_HSE);
break;
case RCC_HSI:
while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK) !=
RCC_CFGR_SWS_HSI);
break;
default:
/* Shouldn't be reached. */
break;
}
}
void rcc_osc_on(enum rcc_osc osc)
{
switch (osc) {
case RCC_PLL:
RCC_CR |= RCC_CR_PLLON;
break;
case RCC_HSE:
RCC_CR |= RCC_CR_HSEON;
break;
case RCC_HSI:
RCC_CR |= RCC_CR_HSION;
break;
case RCC_LSE:
RCC_BDCR |= RCC_BDCR_LSEON;
break;
case RCC_LSI:
RCC_CSR |= RCC_CSR_LSION;
break;
}
}
void rcc_osc_off(enum rcc_osc osc)
{
switch (osc) {
case RCC_PLL:
RCC_CR &= ~RCC_CR_PLLON;
break;
case RCC_HSE:
RCC_CR &= ~RCC_CR_HSEON;
break;
case RCC_HSI:
RCC_CR &= ~RCC_CR_HSION;
break;
case RCC_LSE:
RCC_BDCR &= ~RCC_BDCR_LSEON;
break;
case RCC_LSI:
RCC_CSR &= ~RCC_CSR_LSION;
break;
}
}
void rcc_css_enable(void)
{
RCC_CR |= RCC_CR_CSSON;
}
void rcc_css_disable(void)
{
RCC_CR &= ~RCC_CR_CSSON;
}
void rcc_set_sysclk_source(uint32_t clk)
{
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 1) | (1 << 0));
RCC_CFGR = (reg32 | clk);
}
void rcc_set_pll_source(uint32_t pllsrc)
{
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~RCC_CFGR_PLLSRC;
RCC_CFGR = (reg32 | (pllsrc << 16));
}
void rcc_set_ppre2(uint32_t ppre2)
{
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~(RCC_CFGR_PPRE2_MASK << RCC_CFGR_PPRE2_SHIFT);
RCC_CFGR = (reg32 | (ppre2 << RCC_CFGR_PPRE2_SHIFT));
}
void rcc_set_ppre1(uint32_t ppre1)
{
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~(RCC_CFGR_PPRE1_MASK << RCC_CFGR_PPRE1_SHIFT);
RCC_CFGR = (reg32 | (ppre1 << RCC_CFGR_PPRE1_SHIFT));
}
void rcc_set_hpre(uint32_t hpre)
{
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~(RCC_CFGR_HPRE_MASK << RCC_CFGR_HPRE_SHIFT);
RCC_CFGR = (reg32 | (hpre << RCC_CFGR_HPRE_SHIFT));
}
/**
* Set PLL Source pre-divider **CAUTION**.
* On some F3 devices, prediv only applies to HSE source. On others,
* this is _after_ source selection. See also f0.
* @param[in] prediv division by prediv+1 @ref rcc_cfgr2_prediv
*/
void rcc_set_prediv(uint32_t prediv)
{
RCC_CFGR2 = (RCC_CFGR2 & ~RCC_CFGR2_PREDIV) | prediv;
}
void rcc_set_pll_multiplier(uint32_t pll)
{
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~(RCC_CFGR_PLLMUL_MASK << RCC_CFGR_PLLMUL_SHIFT);
RCC_CFGR = (reg32 | (pll << RCC_CFGR_PLLMUL_SHIFT));
}
uint32_t rcc_get_system_clock_source(void)
{
/* Return the clock source which is used as system clock. */
return (RCC_CFGR & 0x000c) >> 2;
}
/**
* Setup clocks to run from PLL.
* The arguments provide the pll source, multipliers, dividers, all that's
* needed to establish a system clock.
* @param clock clock information structure
*/
void rcc_clock_setup_pll(const struct rcc_clock_scale *clock)
{
if (clock->pllsrc == RCC_CFGR_PLLSRC_HSE_PREDIV) {
rcc_osc_on(RCC_HSE);
rcc_wait_for_osc_ready(RCC_HSE);
} else {
rcc_osc_on(RCC_HSI);
rcc_wait_for_osc_ready(RCC_HSI);
}
rcc_osc_off(RCC_PLL);
rcc_usb_prescale_1_5();
if (clock->usbdiv1) {
rcc_usb_prescale_1();
}
rcc_wait_for_osc_not_ready(RCC_PLL);
rcc_set_pll_source(clock->pllsrc);
rcc_set_pll_multiplier(clock->pllmul);
rcc_set_prediv(clock->plldiv);
/* Enable PLL oscillator and wait for it to stabilize. */
rcc_osc_on(RCC_PLL);
rcc_wait_for_osc_ready(RCC_PLL);
/* Configure flash settings. */
flash_prefetch_enable();
flash_set_ws(clock->flash_waitstates);
rcc_set_hpre(clock->hpre);
rcc_set_ppre2(clock->ppre2);
rcc_set_ppre1(clock->ppre1);
/* Select PLL as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_PLL);
/* Wait for PLL clock to be selected. */
rcc_wait_for_sysclk_status(RCC_PLL);
/* Set the peripheral clock frequencies used. */
rcc_ahb_frequency = clock->ahb_frequency;
rcc_apb1_frequency = clock->apb1_frequency;
rcc_apb2_frequency = clock->apb2_frequency;
}
void __attribute__((deprecated)) rcc_clock_setup_hsi(const struct rcc_clock_scale *clock)
{
/* Enable internal high-speed oscillator. */
rcc_osc_on(RCC_HSI);
rcc_wait_for_osc_ready(RCC_HSI);
/* Select HSI as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_HSI); /* XXX: se cayo */
rcc_wait_for_sysclk_status(RCC_HSI);
rcc_osc_off(RCC_PLL);
rcc_wait_for_osc_not_ready(RCC_PLL);
rcc_set_pll_source(clock->pllsrc);
rcc_set_pll_multiplier(clock->pllmul);
/* Enable PLL oscillator and wait for it to stabilize. */
rcc_osc_on(RCC_PLL);
rcc_wait_for_osc_ready(RCC_PLL);
/*
* Set prescalers for AHB, ADC, APB1, APB2.
* Do this before touching the PLL (TODO: why?).
*/
rcc_set_hpre(clock->hpre);
rcc_set_ppre2(clock->ppre2);
rcc_set_ppre1(clock->ppre1);
/* Configure flash settings. */
flash_set_ws(clock->flash_waitstates);
/* Select PLL as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_PLL); /* XXX: se cayo */
/* Wait for PLL clock to be selected. */
rcc_wait_for_sysclk_status(RCC_PLL);
/* Set the peripheral clock frequencies used. */
rcc_ahb_frequency = clock->ahb_frequency;
rcc_apb1_frequency = clock->apb1_frequency;
rcc_apb2_frequency = clock->apb2_frequency;
}
void rcc_backupdomain_reset(void)
{
/* Set the backup domain software reset. */
RCC_BDCR |= RCC_BDCR_BDRST;
/* Clear the backup domain software reset. */
RCC_BDCR &= ~RCC_BDCR_BDRST;
}
void rcc_set_i2c_clock_hsi(uint32_t i2c)
{
if (i2c == I2C1) {
RCC_CFGR3 &= ~RCC_CFGR3_I2C1SW;
}
if (i2c == I2C2) {
RCC_CFGR3 &= ~RCC_CFGR3_I2C2SW;
}
}
void rcc_set_i2c_clock_sysclk(uint32_t i2c)
{
if (i2c == I2C1) {
RCC_CFGR3 |= RCC_CFGR3_I2C1SW;
}
if (i2c == I2C2) {
RCC_CFGR3 |= RCC_CFGR3_I2C2SW;
}
}
uint32_t rcc_get_i2c_clocks(void)
{
return RCC_CFGR3 & (RCC_CFGR3_I2C1SW | RCC_CFGR3_I2C2SW);
}
void rcc_usb_prescale_1_5(void)
{
RCC_CFGR &= ~RCC_CFGR_USBPRES;
}
void rcc_usb_prescale_1(void)
{
RCC_CFGR |= RCC_CFGR_USBPRES;
}
void rcc_adc_prescale(uint32_t prescale1, uint32_t prescale2)
{
uint32_t clear_mask = (RCC_CFGR2_ADCxPRES_MASK
<< RCC_CFGR2_ADC12PRES_SHIFT)
| (RCC_CFGR2_ADCxPRES_MASK
<< RCC_CFGR2_ADC34PRES_SHIFT);
uint32_t set = (prescale1 << RCC_CFGR2_ADC12PRES_SHIFT) |
(prescale2 << RCC_CFGR2_ADC34PRES_SHIFT);
RCC_CFGR2 &= ~(clear_mask);
RCC_CFGR2 |= (set);
}
static uint32_t rcc_get_usart_clksel_freq(uint32_t apb_clk, uint8_t shift) {
uint8_t clksel = (RCC_CFGR3 >> shift) & RCC_CFGR3_UARTxSW_MASK;
uint8_t hpre = (RCC_CFGR >> RCC_CFGR_HPRE_SHIFT) & RCC_CFGR_HPRE_MASK;
switch (clksel) {
case RCC_CFGR3_UART1SW_PCLK:
return apb_clk;
case RCC_CFGR3_UART1SW_SYSCLK:
return rcc_ahb_frequency * rcc_get_div_from_hpre(hpre);
case RCC_CFGR3_UART1SW_HSI:
return 8000000U;
}
cm3_assert_not_reached();
}
/*---------------------------------------------------------------------------*/
/** @brief Get the peripheral clock speed for the USART at base specified.
* @param usart Base address of USART to get clock frequency for.
*/
uint32_t rcc_get_usart_clk_freq(uint32_t usart)
{
/* Handle values with selectable clocks. */
if (usart == USART1_BASE) {
return rcc_get_usart_clksel_freq(rcc_apb2_frequency, RCC_CFGR3_UART1SW_SHIFT);
} else if (usart == USART2_BASE) {
return rcc_get_usart_clksel_freq(rcc_apb1_frequency, RCC_CFGR3_UART2SW_SHIFT);
} else if (usart == USART3_BASE) {
return rcc_get_usart_clksel_freq(rcc_apb1_frequency, RCC_CFGR3_UART3SW_SHIFT);
} else if (usart == UART4_BASE) {
return rcc_get_usart_clksel_freq(rcc_apb1_frequency, RCC_CFGR3_UART4SW_SHIFT);
} else { /* UART5 */
return rcc_get_usart_clksel_freq(rcc_apb1_frequency, RCC_CFGR3_UART5SW_SHIFT);
}
}
/*---------------------------------------------------------------------------*/
/** @brief Get the peripheral clock speed for the Timer at base specified.
* @param timer Base address of TIM to get clock frequency for.
*/
uint32_t rcc_get_timer_clk_freq(uint32_t timer)
{
/* Handle APB1 timer clocks. */
if (timer >= TIM2_BASE && timer <= TIM7_BASE) {
uint8_t ppre1 = (RCC_CFGR >> RCC_CFGR_PPRE1_SHIFT) & RCC_CFGR_PPRE1_MASK;
return (ppre1 == RCC_CFGR_PPRE1_DIV_NONE) ? rcc_apb1_frequency
: 2 * rcc_apb1_frequency;
} else {
uint8_t ppre2 = (RCC_CFGR >> RCC_CFGR_PPRE2_SHIFT) & RCC_CFGR_PPRE2_MASK;
return (ppre2 == RCC_CFGR_PPRE2_DIV_NONE) ? rcc_apb2_frequency
: 2 * rcc_apb2_frequency;
}
}
/*---------------------------------------------------------------------------*/
/** @brief Get the peripheral clock speed for the I2C device at base specified.
* @param i2c Base address of I2C to get clock frequency for.
*/
uint32_t rcc_get_i2c_clk_freq(uint32_t i2c)
{
if (i2c == I2C1_BASE) {
if (RCC_CFGR3 & RCC_CFGR3_I2C1SW) {
uint8_t hpre = (RCC_CFGR >> RCC_CFGR_HPRE_SHIFT) & RCC_CFGR_HPRE_MASK;
return rcc_ahb_frequency * rcc_get_div_from_hpre(hpre);
} else {
return 8000000U;
}
} else {
return rcc_apb1_frequency;
}
}
/*---------------------------------------------------------------------------*/
/** @brief Get the peripheral clock speed for the SPI device at base specified.
* @param spi Base address of SPI device to get clock frequency for (e.g. SPI1_BASE).
*/
uint32_t rcc_get_spi_clk_freq(uint32_t spi) {
if (spi == SPI1_BASE || spi == SPI4_BASE) {
return rcc_apb2_frequency;
} else {
return rcc_apb1_frequency;
}
}
/**@}*/

27
libopencm3/lib/stm32/f3/vector_chipset.c Normal file
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@@ -0,0 +1,27 @@
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#include <libopencm3/cm3/scb.h>
static void pre_main(void)
{
/* Enable access to Floating-Point coprocessor. */
SCB_CPACR |= SCB_CPACR_FULL * (SCB_CPACR_CP10 | SCB_CPACR_CP11);
}