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  subdir:   "libopencm3"
  merged:   "f5813a54"
upstream:
  origin:   "https://github.com/libopencm3/libopencm3"
  branch:   "master"
  commit:   "f5813a54"
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Arti Zirk
2021-09-30 16:34:10 +03:00
parent 1a441e5806
commit 244fdbc35c
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64
libopencm3/lib/stm32/g4/Makefile Normal file
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##
## This file is part of the libopencm3 project.
##
## Copyright (C) 2020 Karl Palsson <karlp@tweak.net.au>
##
## This library is free software: you can redistribute it and/or modify
## it under the terms of the GNU Lesser General Public License as published by
## the Free Software Foundation, either version 3 of the License, or
## (at your option) any later version.
##
## This library is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU Lesser General Public License for more details.
##
## You should have received a copy of the GNU Lesser General Public License
## along with this library. If not, see <http://www.gnu.org/licenses/>.
##
LIBNAME = libopencm3_stm32g4
SRCLIBDIR ?= ../..
FP_FLAGS ?= -mfloat-abi=hard -mfpu=fpv4-sp-d16
CC = $(PREFIX)gcc
AR = $(PREFIX)ar
TGT_CFLAGS = -Os \
-Wall -Wextra -Wimplicit-function-declaration \
-Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \
-Wundef -Wshadow \
-I../../../include -fno-common \
-mcpu=cortex-m4 -mthumb $(FP_FLAGS) \
-Wstrict-prototypes \
-ffunction-sections -fdata-sections -MD -DSTM32G4
TGT_CFLAGS += $(DEBUG_FLAGS)
TGT_CFLAGS += $(STANDARD_FLAGS)
ARFLAGS = rcs
OBJS += adc.o adc_common_v2.o adc_common_v2_multi.o
OBJS += crs_common_all.o
OBJS += dac_common_all.o dac_common_v2.o
OBJS += dma_common_l1f013.o
OBJS += dmamux.o
OBJS += fdcan.o fdcan_common.o
OBJS += flash.o flash_common_all.o flash_common_f.o flash_common_idcache.o
OBJS += gpio_common_all.o gpio_common_f0234.o
OBJS += opamp_common_all.o opamp_common_v2.o
OBJS += pwr.o
OBJS += rcc.o rcc_common_all.o
OBJS += spi_common_all.o spi_common_v2.o
OBJS += timer_common_all.o timer_common_f0234.o
OBJS += quadspi_common_v1.o
OBJS += usb.o usb_control.o usb_standard.o
OBJS += usb_audio.o
OBJS += usb_cdc.o
OBJS += usb_hid.o
OBJS += usb_midi.o
OBJS += usb_msc.o
OBJS += st_usbfs_core.o st_usbfs_v2.o
VPATH += ../../usb:../:../../cm3:../common
VPATH += ../../ethernet
include ../../Makefile.include

718
libopencm3/lib/stm32/g4/adc.c Normal file
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/** @addtogroup adc_file ADC peripheral API
* @ingroup peripheral_apis
*
* @brief <b>libopencm3 STM32G4xx ADC</b>
*
* @version 1.0.0
*
* @date 10 Jul 2020
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#include <libopencm3/stm32/adc.h>
/**@{*/
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Analog Watchdog for Regular Conversions
*
* The analog watchdog allows the monitoring of an analog signal between two
* threshold levels. The thresholds must be preset. Comparison is done before
* data alignment takes place, so the thresholds are left-aligned.
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_enable_analog_watchdog_regular(uint32_t adc)
{
ADC_CFGR1(adc) |= ADC_CFGR1_AWD1EN;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Analog Watchdog for Regular Conversions
*
* The analog watchdog allows the monitoring of an analog signal between two
* threshold levels. The thresholds must be preset. Comparison is done before
* data alignment takes place, so the thresholds are left-aligned.
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_disable_analog_watchdog_regular(uint32_t adc)
{
ADC_CFGR1(adc) &= ~ADC_CFGR1_AWD1EN;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Analog Watchdog for Injected Conversions
*
* The analog watchdog allows the monitoring of an analog signal between two
* threshold levels. The thresholds must be preset. Comparison is done before
* data alignment takes place, so the thresholds are left-aligned.
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_enable_analog_watchdog_injected(uint32_t adc)
{
ADC_CFGR1(adc) |= ADC_CFGR1_JAWD1EN;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable Analog Watchdog for Injected Conversions
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_disable_analog_watchdog_injected(uint32_t adc)
{
ADC_CFGR1(adc) &= ~ADC_CFGR1_JAWD1EN;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Discontinuous Mode for Regular Conversions
*
* In this mode the ADC converts, on each trigger, a subgroup of up to 8 of the
* defined regular channel group. The subgroup is defined by the number of
* consecutive channels to be converted. After a subgroup has been converted
* the next trigger will start conversion of the immediately following subgroup
* of the same length or until the whole group has all been converted. When the
* whole group has been converted, the next trigger will restart conversion of
* the subgroup at the beginning of the whole group.
*
* @param[in] adc ADC block register address base @ref adc_reg_base
* @param[in] length Number of channels in the group @ref adc_cr1_discnum
*/
void adc_enable_discontinuous_mode_regular(uint32_t adc, uint8_t length)
{
if ((length-1) > 7) {
return;
}
ADC_CFGR1(adc) |= ADC_CFGR1_DISCEN;
ADC_CFGR1(adc) |= ((length-1) << ADC_CFGR1_DISCNUM_SHIFT);
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable Discontinuous Mode for Regular Conversions
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_disable_discontinuous_mode_regular(uint32_t adc)
{
ADC_CFGR1(adc) &= ~ADC_CFGR1_DISCEN;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Discontinuous Mode for Injected Conversions
*
* In this mode the ADC converts sequentially one channel of the defined group
* of injected channels, cycling back to the first channel in the group once
* the entire group has been converted.
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_enable_discontinuous_mode_injected(uint32_t adc)
{
ADC_CFGR1(adc) |= ADC_CFGR1_JDISCEN;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable Discontinuous Mode for Injected Conversions
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_disable_discontinuous_mode_injected(uint32_t adc)
{
ADC_CFGR1(adc) &= ~ADC_CFGR1_JDISCEN;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Automatic Injected Conversions
*
* The ADC converts a defined injected group of channels immediately after the
* regular channels have been converted. The external trigger on the injected
* channels is disabled as required.
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_enable_automatic_injected_group_conversion(uint32_t adc)
{
adc_disable_external_trigger_injected(adc);
ADC_CFGR1(adc) |= ADC_CFGR1_JAUTO;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable Automatic Injected Conversions
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_disable_automatic_injected_group_conversion(uint32_t adc)
{
ADC_CFGR1(adc) &= ~ADC_CFGR1_JAUTO;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Analog Watchdog for All Regular and/or Injected Channels
*
* The analog watchdog allows the monitoring of an analog signal between two
* threshold levels. The thresholds must be preset. Comparison is done before
* data alignment takes place, so the thresholds are left-aligned.
*
* @note The analog watchdog must be enabled for either or both of the regular
* or injected channels. If neither are enabled, the analog watchdog feature
* will be disabled.
*
* @ref adc_enable_analog_watchdog_injected, @ref
* adc_enable_analog_watchdog_regular.
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_enable_analog_watchdog_on_all_channels(uint32_t adc)
{
ADC_CFGR1(adc) &= ~ADC_CFGR1_AWD1SGL;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Analog Watchdog for a Selected Channel
*
* The analog watchdog allows the monitoring of an analog signal between two
* threshold levels. The thresholds must be preset. Comparison is done before
* data alignment takes place, so the thresholds are left-aligned.
*
* @note The analog watchdog must be enabled for either or both of the regular
* or injected channels. If neither are enabled, the analog watchdog feature
* will be disabled. If both are enabled, the same channel number is monitored
* @ref adc_enable_analog_watchdog_injected, @ref
* adc_enable_analog_watchdog_regular.
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
* @param[in] channel Unsigned int8. ADC channel numbe
* @ref adc_watchdog_channel
*/
void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc,
uint8_t channel)
{
ADC_CFGR1(adc) = (ADC_CFGR1(adc) & ~ADC_CFGR1_AWD1CH) |
ADC_CFGR1_AWD1CH_VAL(channel);
ADC_CFGR1(adc) |= ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Injected End-Of-Conversion Interrupt
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_enable_eoc_interrupt_injected(uint32_t adc)
{
ADC_IER(adc) |= ADC_IER_JEOCIE;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable Injected End-Of-Conversion Interrupt
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_disable_eoc_interrupt_injected(uint32_t adc)
{
ADC_IER(adc) &= ~ADC_IER_JEOCIE;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Injected End-Of-Sequence Interrupt
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_enable_eos_interrupt_injected(uint32_t adc)
{
ADC_IER(adc) |= ADC_IER_JEOSIE;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable Injected End-Of-Sequence Interrupt
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_disable_eos_interrupt_injected(uint32_t adc)
{
ADC_IER(adc) &= ~ADC_IER_JEOSIE;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Analog Watchdog Interrupt
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_enable_all_awd_interrupt(uint32_t adc)
{
ADC_IER(adc) |= ADC_IER_AWD1IE;
ADC_IER(adc) |= ADC_IER_AWD2IE;
ADC_IER(adc) |= ADC_IER_AWD3IE;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable Analog Watchdog Interrupt
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_disable_all_awd_interrupt(uint32_t adc)
{
ADC_IER(adc) &= ~ADC_IER_AWD1IE;
ADC_IER(adc) &= ~ADC_IER_AWD2IE;
ADC_IER(adc) &= ~ADC_IER_AWD3IE;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Regular End-Of-Sequence Interrupt
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_enable_eos_interrupt(uint32_t adc)
{
ADC_IER(adc) |= ADC_IER_EOSIE;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable Regular End-Of-Sequence Interrupt
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_disable_eos_interrupt(uint32_t adc)
{
ADC_IER(adc) &= ~ADC_IER_EOSIE;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Software Triggered Conversion on Injected Channels
*
* This starts conversion on a set of defined injected channels.
* Depending on the configuration bits JEXTEN, a conversion will start
* immediately (software trigger configuration) or once an injected hardware
* trigger event occurs (hardware trigger configuration).
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_start_conversion_injected(uint32_t adc)
{
/* Start conversion on injected channels. */
ADC_CR(adc) |= ADC_CR_JADSTART;
}
/** ADC Set Analog Watchdog Upper Threshold.
* @param[in] adc ADC block register address base
* @ref adc_reg_base
* @param[in] threshold Upper threshold value
*/
void adc_set_watchdog_high_threshold(uint32_t adc, uint16_t threshold)
{
uint32_t reg32 = 0;
uint32_t mask = 0xf000ffff;
reg32 |= (threshold << 16);
reg32 &= ~mask; /* clear masked bits. */
ADC_TR1(adc) = (ADC_TR1(adc) & mask) | reg32;
ADC_TR2(adc) = (ADC_TR2(adc) & mask) | reg32;
ADC_TR3(adc) = (ADC_TR3(adc) & mask) | reg32;
}
/** ADC Set Analog Watchdog Lower Threshold.
* @param[in] adc ADC block register address base
* @ref adc_reg_base
* @param[in] threshold Lower threshold value
*/
void adc_set_watchdog_low_threshold(uint32_t adc, uint16_t threshold)
{
uint32_t reg32 = 0;
uint32_t mask = 0xfffff000;
reg32 = (uint32_t)threshold;
reg32 &= ~mask; /* clear masked bits. */
ADC_TR1(adc) = (ADC_TR1(adc) & mask) | reg32;
ADC_TR2(adc) = (ADC_TR2(adc) & mask) | reg32;
ADC_TR3(adc) = (ADC_TR3(adc) & mask) | reg32;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Set an Injected Channel Conversion Sequence
*
* Defines a sequence of channels to be converted as an injected group with a
* length from 1 to 4 channels. If this is called during conversion, the current
* conversion is reset and conversion begins again with the newly defined group.
*
* @param[in] adc Unsigned int32. ADC block register address base
* @ref adc_reg_base
* @param[in] length Unsigned int8. Number of channels in the group.
* @param[in] channel Unsigned int8[]. Set of channels in sequence, integers
* 0..18
*/
void adc_set_injected_sequence(uint32_t adc, uint8_t length, uint8_t channel[])
{
uint32_t reg32 = 0;
uint8_t i = 0;
/* Maximum sequence length is 4 channels. Minimum sequence is 1.*/
if ((length - 1) > 3) {
return;
}
for (i = 0; i < length; i++) {
reg32 |= ADC_JSQR_JSQ_VAL(4 - i, channel[length - i - 1]);
}
reg32 |= ADC_JSQR_JL_VAL(length);
ADC_JSQR(adc) = reg32;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Read the End-of-Conversion Flag for Injected Conversion
*
* This flag is set by hardware at the end of each injected conversion of a
* channel when a new data is available in the corresponding ADCx_JDRy register.
*
* @param[in] adc Unsigned int32. ADC block register address base
* @ref adc_reg_base
* @returns bool. End of conversion flag.
*/
bool adc_eoc_injected(uint32_t adc)
{
return ADC_ISR(adc) & ADC_ISR_JEOC;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Read the End-of-Sequence Flag for Injected Conversions
*
* This flag is set after all channels of an injected group have been
* converted.
*
* @param[in] adc Unsigned int32. ADC block register address base
* @ref adc_reg_base
* @returns bool. End of conversion flag.
*/
bool adc_eos_injected(uint32_t adc)
{
return ADC_ISR(adc) & ADC_ISR_JEOS;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Read from an Injected Conversion Result Register
*
* The result read back from the selected injected result register (one of four)
* is 12 bits, right or left aligned within the first 16 bits. The result can
* have a negative value if the injected channel offset has been set @see
* adc_set_injected_offset.
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
* @param[in] reg Unsigned int8. Register number (1 ... 4).
* @returns Unsigned int32 conversion result.
*/
uint32_t adc_read_injected(uint32_t adc, uint8_t reg)
{
switch (reg) {
case 1:
return ADC_JDR1(adc);
case 2:
return ADC_JDR2(adc);
case 3:
return ADC_JDR3(adc);
case 4:
return ADC_JDR4(adc);
}
return 0;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Set the Injected Channel Data Offset
*
* This value is subtracted from the injected channel results after conversion
* is complete, and can result in negative results. A separate value can be
* specified for each injected data register.
*
* @param[in] adc Unsigned int32. ADC block register address base
* @ref adc_reg_base
* @param[in] reg Unsigned int8. Register number (1 ... 4).
* @param[in] offset Unsigned int32.
*/
void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset)
{
switch (reg) {
case 1:
ADC_OFR1(adc) |= ADC_OFR1_OFFSET1_EN;
ADC_OFR1(adc) |= offset;
break;
case 2:
ADC_OFR2(adc) |= ADC_OFR2_OFFSET2_EN;
ADC_OFR2(adc) |= offset;
break;
case 3:
ADC_OFR3(adc) |= ADC_OFR3_OFFSET3_EN;
ADC_OFR3(adc) |= offset;
break;
case 4:
ADC_OFR4(adc) |= ADC_OFR4_OFFSET4_EN;
ADC_OFR4(adc) |= offset;
break;
}
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Set Clock Source
*
* The ADC clock taken from the APB2 clock can be scaled down by 2, 4, 6 or 8.
*
* @param adc peripheral of choice @ref adc_reg_base
* @param[in] source Unsigned int32. Source value for ADC Clock @ref
* adc_ccr_adcpre
*/
void adc_set_clk_source(uint32_t adc, uint32_t source)
{
uint32_t reg32 = ((ADC_CCR(adc) & ~ADC_CCR_CKMODE_MASK) | source);
ADC_CCR(adc) = reg32;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Set Clock Prescale
*
* The ADC clock taken from the APB2 clock can be scaled down by 2, 4, 6 or 8.
*
* @param adc peripheral of choice @ref adc_reg_base
* @param[in] prescale Unsigned int32. Prescale value for ADC Clock @ref
* adc_ccr_adcpre
*/
void adc_set_clk_prescale(uint32_t adc, uint32_t ckmode)
{
uint32_t reg32 = ((ADC_CCR(adc) & ~ADC_CCR_CKMODE_MASK) | ckmode);
ADC_CCR(adc) = reg32;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC set multi mode
*
* The multiple mode can uses these arrangement:
* - ADC1 as master and ADC2 as slave
* - ADC3 as master and ADC4 as slave
*
* This setting is applied to ADC master only (ADC1 or ADC3).
*
* The various modes possible are described in the reference manual.
*
* @param adc peripheral of choice @ref adc_reg_base
* @param[in] mode Multiple mode selection from @ref adc_multi_mode
*/
void adc_set_multi_mode(uint32_t adc, uint32_t mode)
{
ADC_CCR(adc) &= ~(ADC_CCR_DUAL_MASK << ADC_CCR_DUAL_SHIFT);
ADC_CCR(adc) |= (mode << ADC_CCR_DUAL_SHIFT);
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable an External Trigger for Regular Channels
*
* This enables an external trigger for set of defined regular channels, and
* sets the polarity of the trigger event: rising or falling edge or both. Note
* that if the trigger polarity is zero, triggering is disabled.
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
* @param[in] trigger Unsigned int32. Trigger identifier
* @ref adc_trigger_regular
* @param[in] polarity Unsigned int32. Trigger polarity @ref
* adc_trigger_polarity_regular
*/
void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger,
uint32_t polarity)
{
uint32_t reg32 = ADC_CFGR1(adc);
reg32 &= ~(ADC_CFGR1_EXTSEL_MASK | ADC_CFGR1_EXTEN_MASK);
reg32 |= (trigger | polarity);
ADC_CFGR1(adc) = reg32;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable an External Trigger for Regular Channels
*
* @param[in] adc Unsigned int32. ADC block register address base
* @ref adc_reg_base
*/
void adc_disable_external_trigger_regular(uint32_t adc)
{
ADC_CFGR1(adc) &= ~ADC_CFGR1_EXTEN_MASK;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable an External Trigger for Injected Channels
*
* This enables an external trigger for set of defined injected channels, and
* sets the polarity of the trigger event: rising or falling edge or both.
*
* @param[in] adc Unsigned int32. ADC block register address base
* @ref adc_reg_base
* @param[in] trigger Unsigned int8. Trigger identifier
* @ref adc_trigger_injected
* @param[in] polarity Unsigned int32. Trigger polarity
* @ref adc_trigger_polarity_injected
*/
void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger,
uint32_t polarity)
{
uint32_t reg32 = ADC_JSQR(adc);
reg32 &= ~(ADC_JSQR_JEXTSEL_MASK | ADC_JSQR_JEXTEN_MASK);
reg32 |= (trigger | polarity);
ADC_JSQR(adc) = reg32;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable an External Trigger for Injected Channels
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_disable_external_trigger_injected(uint32_t adc)
{
ADC_JSQR(adc) &= ~ADC_JSQR_JEXTEN_MASK;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Read the Analog Watchdog Flag
*
* This flag is set when the converted voltage crosses the high or low
* thresholds.
*
* @param[in] adc Unsigned int32. ADC block register address base
* @ref adc_reg_base
* @returns bool. AWD flag.
*/
bool adc_awd(uint32_t adc)
{
return (ADC_ISR(adc) & ADC_ISR_AWD1) &&
(ADC_ISR(adc) & ADC_ISR_AWD2) &&
(ADC_ISR(adc) & ADC_ISR_AWD3);
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Enable Deep-Power-Down Mdoe
*
* Deep-power-down mode allows additional power saving by internally switching
* off to reduce leakage currents.
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_enable_deeppwd(uint32_t adc)
{
ADC_CR(adc) |= ADC_CR_DEEPPWD;
}
/*---------------------------------------------------------------------------*/
/** @brief ADC Disable Deep-Power-Down Mdoe
*
* Deep-power-down mode allows additional power saving by internally switching
* off to reduce leakage currents.
*
* @param[in] adc Unsigned int32. ADC block register address base @ref
* adc_reg_base
*/
void adc_disable_deeppwd(uint32_t adc)
{
ADC_CR(adc) &= ~ADC_CR_DEEPPWD;
}
/**
* Enable the ADC Voltage regulator
* Before any use of the ADC, the ADC Voltage regulator must be enabled.
* You must wait up to 10uSecs afterwards before trying anything else.
* @param[in] adc ADC block register address base
* @sa adc_disable_regulator
*/
void adc_enable_regulator(uint32_t adc)
{
ADC_CR(adc) |= ADC_CR_ADVREGEN;
}
/**
* Disable the ADC Voltage regulator
* You can disable the adc vreg when not in use to save power
* @param[in] adc ADC block register address base
* @sa adc_enable_regulator
*/
void adc_disable_regulator(uint32_t adc)
{
ADC_CR(adc) &= ~ADC_CR_ADVREGEN;
}
/**@}*/

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/** @addtogroup fdcan_file FDCAN peripheral API
*
* @ingroup peripheral_apis
*
* @brief <b>libopencm3 STM32 FDCAN</b>
*
* @version 1.0.0
*
* @author @htmlonly &copy; @endhtmlonly 2021 Eduard Drusa <ventyl86 at netkosice dot sk>
*
* Devices can have up to three FDCAN peripherals residing in one FDCAN block. The peripherals
* support both CAN 2.0 A and B standard and Bosch FDCAN standard. FDCAN frame format and
* bitrate switching is supported. The peripheral has several filters for incoming messages that
* can be distributed between two FIFOs and three transmit mailboxes. For transmitted messages
* it is possible to opt for event notification once message is transmitted.
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2021 Eduard Drusa <ventyl86 at netkosice dot sk>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#include <libopencm3/stm32/fdcan.h>
#include <libopencm3/stm32/rcc.h>
#include <stddef.h>
/* --- FD-CAN functions ----------------------------------------------------- */
/** @ingroup fdcan_file */
/**@{
* */
/** Returns actual size of FIFO entry in FIFO for given CAN port and FIFO.
*
* Obtains value of FIFO entry length. For G4 it returns constant value as
* G4 has FIFO element length hardcoded.
* @param [in] canport FDCAN block base address. See @ref fdcan_block. Unused.
* @param [in] fifo_id ID of FIFO whole length is queried. Unused.
* @returns Length of FIFO entry length covering frame header and frame payload.
*/
unsigned fdcan_get_fifo_element_size(uint32_t canport, unsigned fifo_id)
{
/* Silences compiler. Variables are present for API compatibility
* with STM32H7
*/
(void) (canport);
(void) (fifo_id);
return sizeof(struct fdcan_rx_fifo_element);
}
/** Returns actual size of transmit entry in transmit queue/FIFO for given CAN port.
*
* Obtains value of entry length in transmit queue/FIFO. For G4 it returns constant value
* as G4 has transmit buffer entries of fixed length.
*
* @param [in] canport FDCAN block base address. See @ref fdcan_block. Unused.
* @returns Length of FIFO entry length covering frame header and frame payload.
*/
unsigned fdcan_get_txbuf_element_size(uint32_t canport)
{
/* Silences compiler. Variables are present for API compatibility
* with STM32H7
*/
(void) (canport);
return sizeof(struct fdcan_tx_buffer_element);
}
/** Configure amount of filters and initialize filtering block.
*
* This function allows to configure global amount of filters present.
* FDCAN block will only ever check as many filters as this function configures.
* Function will also clear all filter blocks to zero values. This function
* can be only called after @ref fdcan_init has already been called and
* @ref fdcan_start has not been called yet as registers holding filter
* count are write-protected unless FDCAN block is in INIT mode. It is possible
* to reconfigure filters (@ref fdcan_set_std_filter and @ref fdcan_set_ext_filter)
* after FDCAN block has already been started.
*
* @param [in] canport FDCAN block base address. See @ref fdcan_block.
* @param [in] std_filt requested amount of standard ID filter rules (0-28)
* @param [in] ext_filt requested amount of extended ID filter rules (0-8)
*/
void fdcan_init_filter(uint32_t canport, uint8_t std_filt, uint8_t ext_filt)
{
struct fdcan_standard_filter *lfssa = fdcan_get_flssa_addr(canport);
struct fdcan_extended_filter *lfesa = fdcan_get_flesa_addr(canport);
/* Only perform initialization of message RAM if there are
* any filters required
*/
if (std_filt > 0) {
FDCAN_RXGFC(canport) =
(FDCAN_RXGFC(canport) & ~(FDCAN_RXGFC_LSS_MASK << FDCAN_RXGFC_LSS_SHIFT))
| (std_filt << FDCAN_RXGFC_LSS_SHIFT);
for (int q = 0; q < FDCAN_SFT_MAX_NR; ++q) {
lfssa[q].type_id1_conf_id2 = 0;
}
} else {
/* Reset filter count to zero */
FDCAN_RXGFC(canport) =
(FDCAN_RXGFC(canport) & ~(FDCAN_RXGFC_LSS_MASK << FDCAN_RXGFC_LSS_SHIFT));
}
if (ext_filt > 0) {
FDCAN_RXGFC(canport) =
(FDCAN_RXGFC(canport) & ~(FDCAN_RXGFC_LSE_MASK << FDCAN_RXGFC_LSE_SHIFT))
| (ext_filt << FDCAN_RXGFC_LSE_SHIFT);
for (int q = 0; q < FDCAN_EFT_MAX_NR; ++q) {
lfesa[q].conf_id1 = 0;
lfesa[q].type_id2 = 0;
}
} else {
/* Reset filter count to zero */
FDCAN_RXGFC(canport) =
(FDCAN_RXGFC(canport) & ~(FDCAN_RXGFC_LSE_MASK << FDCAN_RXGFC_LSE_SHIFT));
}
}
/** Enable FDCAN operation after FDCAN block has been set up.
*
* This function will disable FDCAN configuration effectively
* allowing FDCAN to sync up with the bus. After calling this function
* it is not possible to reconfigure amount of filter rules, yet
* it is possible to configure rules themselves. FDCAN block operation
* state can be checked using @ref fdcan_get_init_state.
*
* @param [in] canport FDCAN block base address. See @ref fdcan_block.
* @param [in] timeout Amount of empty busy loops, which routine should wait for FDCAN
* confirming that it left INIT mode. If set to 0, function will return
* immediately.
* @returns Operation error status. See @ref fdcan_error.
* @note If this function returns with timeout, it usually means that
* FDCAN_clk is not set up properly.
*/
int fdcan_start(uint32_t canport, uint32_t timeout)
{
/* Error here usually means, that FDCAN_clk is not set up
* correctly, or at all. This usually can't be seen above
* when INIT is set to 1, because default value for INIT is
* 1 as long as one has FDCAN_pclk configured properly.
**/
if (fdcan_cccr_init_cfg(canport, false, timeout) != 0) {
return FDCAN_E_TIMEOUT;
}
return FDCAN_E_OK;
}
/** Configure FDCAN FIFO lock mode
*
* This function allows to choose between locked and overewrite mode of FIFOs. In locked mode,
* whenever FIFO is full and new frame arrives, which would normally been stored into given
* FIFO, then frame is dropped. If overwrite mode is active, then most recent message in FIFO
* is rewritten by frame just received.
* @param [in] canport FDCAN block base address. See @ref fdcan_block.
* @param [in] locked true activates locked mode, false activates overwrite mode
*/
void fdcan_set_fifo_locked_mode(uint32_t canport, bool locked)
{
if (locked) {
FDCAN_RXGFC(canport) &= ~(FDCAN_RXGFC_F1OM | FDCAN_RXGFC_F0OM);
} else {
FDCAN_RXGFC(canport) |= FDCAN_RXGFC_F1OM | FDCAN_RXGFC_F0OM;
}
}
/** @} */

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/** @defgroup flash_file FLASH peripheral API
*
* @ingroup peripheral_apis
*
* @brief <b>libopencm3 STM32G4xx FLASH</b>
*
* @version 1.0.0
*
* Benjamin Levine <benjamin@jesco.karoo.co.uk>
* Ben Brewer <ben.brewer@codethink.co.uk>
*
* @date 30 July 2020
*
* This library supports the FLASH memory controller in the STM32G4
* series of ARM Cortex Microcontrollers by ST Microelectronics.
*
* For the STM32G4xx, accessing FLASH memory is described briefly in
* section 3 of the STM32G4 Reference Manual.
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2016 Benjamin Levine <benjamin@jesco.karoo.co.uk>
* Copyright (C) 2020 Ben Brewer <ben.brewer@codethink.co.uk>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
#include <libopencm3/stm32/flash.h>
/** @brief Wait until Last Operation has Ended
* This loops indefinitely until an operation (write or erase) has completed
* by testing the busy flag.
*/
void flash_wait_for_last_operation(void)
{
while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY);
}
/** @brief Clear the Programming Sequence Error Flag
* This flag is set when incorrect programming configuration has been made.
*/
void flash_clear_pgserr_flag(void)
{
FLASH_SR |= FLASH_SR_PGSERR;
}
/** Clear programming size error flag */
void flash_clear_size_flag(void)
{
FLASH_SR |= FLASH_SR_SIZERR;
}
/** @brief Clear the Programming Alignment Error Flag
*/
void flash_clear_pgaerr_flag(void)
{
FLASH_SR |= FLASH_SR_PGAERR;
}
/** @brief Clear the Write Protect Error Flag
*/
void flash_clear_wrperr_flag(void)
{
FLASH_SR |= FLASH_SR_WRPERR;
}
/** @brief Clear the Programming Error Status Flag
*/
void flash_clear_progerr_flag(void)
{
FLASH_SR |= FLASH_SR_PROGERR;
}
/** @brief Clear All Status Flags
* Program error, end of operation, write protect error, busy.
*/
void flash_clear_status_flags(void)
{
flash_clear_pgserr_flag();
flash_clear_size_flag();
flash_clear_pgaerr_flag();
flash_clear_wrperr_flag();
flash_clear_progerr_flag();
flash_clear_eop_flag();
}
/** @brief Lock the Option Byte Access
* This disables write access to the option bytes. It is locked by default on
* reset.
*/
void flash_lock_option_bytes(void)
{
FLASH_CR |= FLASH_CR_OPTLOCK;
}
/** @brief Program a 64 bit word to FLASH
*
* This performs all operations necessary to program a 64 bit word to FLASH memory.
* The program error flag should be checked separately for the event that memory
* was not properly erased.
*
* @param[in] address Starting address in Flash.
* @param[in] data Double word to write
*/
void flash_program_double_word(uint32_t address, uint64_t data)
{
/* Ensure that all flash operations are complete. */
flash_wait_for_last_operation();
/* Enable writes to flash. */
FLASH_CR |= FLASH_CR_PG;
/* Program the each word separately. */
MMIO32(address) = (uint32_t)data;
MMIO32(address+4) = (uint32_t)(data >> 32);
/* Wait for the write to complete. */
flash_wait_for_last_operation();
/* Disable writes to flash. */
FLASH_CR &= ~FLASH_CR_PG;
}
/** @brief Program a Data Block to FLASH
* This programs an arbitrary length data block to FLASH memory.
* The program error flag should be checked separately for the event that
* memory was not properly erased.
* @param[in] address Starting address in Flash.
* @param[in] data Pointer to start of data block.
* @param[in] len Length of data block in bytes (multiple of 8).
*/
void flash_program(uint32_t address, uint8_t *data, uint32_t len)
{
for (uint32_t i = 0; i < len; i += 8) {
flash_program_double_word(address+i, *(uint64_t*)(data + i));
}
}
/** @brief Erase a page of FLASH
* @param[in] page (0 - 255 for bank 1, 256-511 for bank 2)
*/
void flash_erase_page(uint32_t page)
{
flash_wait_for_last_operation();
/* page and bank are contiguous bits */
FLASH_CR &= ~((FLASH_CR_PNB_MASK << FLASH_CR_PNB_SHIFT) | FLASH_CR_BKER);
if (page > 255) {
FLASH_CR |= FLASH_CR_BKER;
}
FLASH_CR |= page << FLASH_CR_PNB_SHIFT;
FLASH_CR |= FLASH_CR_PER;
FLASH_CR |= FLASH_CR_START;
flash_wait_for_last_operation();
FLASH_CR &= ~FLASH_CR_PER;
}
/** @brief Erase All FLASH
* This performs all operations necessary to erase all sectors in the FLASH
* memory.
*/
void flash_erase_all_pages(void)
{
flash_wait_for_last_operation();
FLASH_CR |= FLASH_CR_MER1 | FLASH_CR_MER2;
FLASH_CR |= FLASH_CR_START;
flash_wait_for_last_operation();
FLASH_CR &= ~FLASH_CR_MER1 & ~FLASH_CR_MER2;
}
/** @brief Program the Option Bytes
* This performs all operations necessary to program the option bytes.
* The option bytes do not need to be erased first.
* @param[in] data value to be programmed.
*/
void flash_program_option_bytes(uint32_t data)
{
flash_wait_for_last_operation();
if (FLASH_CR & FLASH_CR_OPTLOCK) {
flash_unlock_option_bytes();
}
FLASH_OPTR = data;
FLASH_CR |= FLASH_CR_OPTSTRT;
flash_wait_for_last_operation();
}
/**@}*/

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/** @defgroup pwr_file PWR peripheral API
*
* @ingroup peripheral_apis
*
* @brief <b>libopencm3 STM32G4xx Power Control</b>
*
* @version 1.0.0
*
* @author @htmlonly &copy; @endhtmlonly 2016 Benjamin Levine <benjamin@jesco.karoo.co.uk>
* @author @htmlonly &copy; @endhtmlonly 2019 Guillaume Revaillot <g.revaillot@gmail.com>
* @author @htmlonly &copy; @endhtmlonly 2020 Ben Brewer <ben.brewer@codethink.co.uk>
*
* @date 29 July 2020
*
* This library supports the power control system for the
* STM32G4 series of ARM Cortex Microcontrollers by ST Microelectronics.
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2016 Benjamin Levine <benjamin@jesco.karoo.co.uk>
* Copyright (C) 2019 Guillaume Revaillot <g.revaillot@gmail.com>
* Copyright (C) 2020 Ben Brewer <ben.brewer@codethink.co.uk>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
#include <libopencm3/stm32/pwr.h>
void pwr_set_vos_scale(enum pwr_vos_scale scale)
{
uint32_t reg32;
reg32 = PWR_CR1 & ~(PWR_CR1_VOS_MASK << PWR_CR1_VOS_SHIFT);
reg32 |= (scale & PWR_CR1_VOS_MASK) << PWR_CR1_VOS_SHIFT;
PWR_CR1 = reg32;
}
/** Disable Backup Domain Write Protection
*
* This allows backup domain registers to be changed. These registers are write
* protected after a reset.
*/
void pwr_disable_backup_domain_write_protect(void)
{
PWR_CR1 |= PWR_CR1_DBP;
}
/** Re-enable Backup Domain Write Protection
*
* This protects backup domain registers from inadvertent change.
*/
void pwr_enable_backup_domain_write_protect(void)
{
PWR_CR1 &= ~PWR_CR1_DBP;
}
/*---------------------------------------------------------------------------*/
/** @brief Select the low power mode used in deep sleep.
* @param lpms low power mode @ref pwr_cr1_lpms
*/
void pwr_set_low_power_mode_selection(uint32_t lpms)
{
uint32_t reg32;
reg32 = PWR_CR1;
reg32 &= ~(PWR_CR1_LPMS_MASK << PWR_CR1_LPMS_SHIFT);
PWR_CR1 = (reg32 | (lpms << PWR_CR1_LPMS_SHIFT));
}
/*---------------------------------------------------------------------------*/
/** @brief Enable Power Voltage Detector.
* @param[in] pvd_level Power Voltage Detector Falling Threshold voltage @ref pwr_pls.
*/
void pwr_enable_power_voltage_detect(uint32_t pvd_level)
{
uint32_t reg32;
reg32 = PWR_CR2;
reg32 &= ~(PWR_CR2_PLS_MASK << PWR_CR2_PLS_SHIFT);
PWR_CR2 = (reg32 | (pvd_level << PWR_CR2_PLS_SHIFT) | PWR_CR2_PVDE);
}
/*---------------------------------------------------------------------------*/
/** @brief Disable Power Voltage Detector.
*/
void pwr_disable_power_voltage_detect(void)
{
PWR_CR2 &= ~PWR_CR2_PVDE;
}
/*---------------------------------------------------------------------------*/
/** @brief Enable Boost Mode.
*/
void pwr_enable_boost(void)
{
PWR_CR5 &= ~PWR_CR5_R1MODE;
}
/*---------------------------------------------------------------------------*/
/** @brief Disable Boost Mode.
*/
void pwr_disable_boost(void)
{
PWR_CR5 |= PWR_CR5_R1MODE;
}
/**@}*/

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/** @defgroup rcc_file RCC peripheral API
*
* @ingroup peripheral_apis
*
* @brief <b>libopencm3 STM32G4xx Reset and Clock Control</b>
*
* @author @htmlonly &copy; @endhtmlonly 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
* @author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
* @author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
* @author @htmlonly &copy; @endhtmlonly 2013 Frantisek Burian <BuFran at seznam.cz>
* @author @htmlonly &copy; @endhtmlonly 2020 Sam Kirkham <sam.kirkham@codethink.co.uk>
* @author @htmlonly &copy; @endhtmlonly 2020 Ben Brewer <ben.brewer@codethink.co.uk>
*
* @date 30 July 2020
*
* This library supports the Reset and Clock Control System in the STM32 series
* of ARM Cortex Microcontrollers by ST Microelectronics.
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
* Copyright (C) 2013 Frantisek Burian <BuFran at seznam.cz>
* Copyright (C) 2020 Sam Kirkham <sam.kirkham@codethink.co.uk>
* Copyright (C) 2020 Ben Brewer <ben.brewer@codethink.co.uk>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#include <libopencm3/cm3/assert.h>
#include <libopencm3/stm32/rcc.h>
#include <libopencm3/stm32/pwr.h>
#include <libopencm3/stm32/flash.h>
/**@{*/
/* Set the default clock frequencies after reset. */
uint32_t rcc_ahb_frequency = 16000000;
uint32_t rcc_apb1_frequency = 16000000;
uint32_t rcc_apb2_frequency = 16000000;
const struct rcc_clock_scale rcc_hsi_configs[RCC_CLOCK_3V3_END] = {
{ /* 24MHz */
.pllm = 2,
.plln = 12,
.pllp = 0,
.pllq = 2,
.pllr = 4,
.pll_source = RCC_PLLCFGR_PLLSRC_HSI16,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPREx_NODIV,
.ppre2 = RCC_CFGR_PPREx_NODIV,
.vos_scale = PWR_SCALE2,
.boost = false,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN,
.flash_waitstates = 1,
.ahb_frequency = 24e6,
.apb1_frequency = 24e6,
.apb2_frequency = 24e6,
},
{ /* 48MHz */
.pllm = 2,
.plln = 12,
.pllp = 0,
.pllq = 2,
.pllr = 2,
.pll_source = RCC_PLLCFGR_PLLSRC_HSI16,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPREx_NODIV,
.ppre2 = RCC_CFGR_PPREx_NODIV,
.vos_scale = PWR_SCALE1,
.boost = false,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN,
.flash_waitstates = 1,
.ahb_frequency = 48e6,
.apb1_frequency = 48e6,
.apb2_frequency = 48e6,
},
{ /* 96MHz */
.pllm = 2,
.plln = 24,
.pllp = 0,
.pllq = 4,
.pllr = 2,
.pll_source = RCC_PLLCFGR_PLLSRC_HSI16,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPREx_NODIV,
.ppre2 = RCC_CFGR_PPREx_NODIV,
.vos_scale = PWR_SCALE1,
.boost = false,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN,
.flash_waitstates = 3,
.ahb_frequency = 96e6,
.apb1_frequency = 96e6,
.apb2_frequency = 96e6,
},
{ /* 170MHz */
.pllm = 4,
.plln = 85,
.pllp = 0,
.pllq = 0, /* USB requires CRS at this speed. */
.pllr = 2,
.pll_source = RCC_PLLCFGR_PLLSRC_HSI16,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPREx_NODIV,
.ppre2 = RCC_CFGR_PPREx_NODIV,
.vos_scale = PWR_SCALE1,
.boost = true,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN,
.flash_waitstates = 4,
.ahb_frequency = 170e6,
.apb1_frequency = 170e6,
.apb2_frequency = 170e6,
},
};
const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = {
{ /* 24MHz */
.pllm = 1,
.plln = 12,
.pllp = 0,
.pllq = 2,
.pllr = 4,
.pll_source = RCC_PLLCFGR_PLLSRC_HSE,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPREx_NODIV,
.ppre2 = RCC_CFGR_PPREx_NODIV,
.vos_scale = PWR_SCALE2,
.boost = false,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN,
.flash_waitstates = 1,
.ahb_frequency = 24e6,
.apb1_frequency = 24e6,
.apb2_frequency = 24e6,
},
{ /* 48MHz */
.pllm = 1,
.plln = 12,
.pllp = 0,
.pllq = 2,
.pllr = 2,
.pll_source = RCC_PLLCFGR_PLLSRC_HSE,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPREx_NODIV,
.ppre2 = RCC_CFGR_PPREx_NODIV,
.vos_scale = PWR_SCALE1,
.boost = false,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN,
.flash_waitstates = 1,
.ahb_frequency = 48e6,
.apb1_frequency = 48e6,
.apb2_frequency = 48e6,
},
{ /* 96MHz */
.pllm = 1,
.plln = 24,
.pllp = 0,
.pllq = 4,
.pllr = 2,
.pll_source = RCC_PLLCFGR_PLLSRC_HSE,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPREx_NODIV,
.ppre2 = RCC_CFGR_PPREx_NODIV,
.vos_scale = PWR_SCALE1,
.boost = false,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN,
.flash_waitstates = 3,
.ahb_frequency = 96e6,
.apb1_frequency = 96e6,
.apb2_frequency = 96e6,
},
{ /* 170MHz */
.pllm = 2,
.plln = 85,
.pllp = 0,
.pllq = 0, /* USB requires CRS at this speed. */
.pllr = 2,
.pll_source = RCC_PLLCFGR_PLLSRC_HSE,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPREx_NODIV,
.ppre2 = RCC_CFGR_PPREx_NODIV,
.vos_scale = PWR_SCALE1,
.boost = true,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN,
.flash_waitstates = 4,
.ahb_frequency = 170e6,
.apb1_frequency = 170e6,
.apb2_frequency = 170e6,
},
};
const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = {
{ /* 24MHz */
.pllm = 2,
.plln = 16,
.pllp = 0,
.pllq = 2,
.pllr = 4,
.pll_source = RCC_PLLCFGR_PLLSRC_HSE,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPREx_NODIV,
.ppre2 = RCC_CFGR_PPREx_NODIV,
.vos_scale = PWR_SCALE2,
.boost = false,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN,
.flash_waitstates = 1,
.ahb_frequency = 24e6,
.apb1_frequency = 24e6,
.apb2_frequency = 24e6,
},
{ /* 48MHz */
.pllm = 2,
.plln = 16,
.pllp = 0,
.pllq = 2,
.pllr = 2,
.pll_source = RCC_PLLCFGR_PLLSRC_HSE,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPREx_NODIV,
.ppre2 = RCC_CFGR_PPREx_NODIV,
.vos_scale = PWR_SCALE1,
.boost = false,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN,
.flash_waitstates = 1,
.ahb_frequency = 48e6,
.apb1_frequency = 48e6,
.apb2_frequency = 48e6,
},
{ /* 96MHz */
.pllm = 2,
.plln = 32,
.pllp = 0,
.pllq = 4,
.pllr = 2,
.pll_source = RCC_PLLCFGR_PLLSRC_HSE,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPREx_NODIV,
.ppre2 = RCC_CFGR_PPREx_NODIV,
.vos_scale = PWR_SCALE1,
.boost = false,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN,
.flash_waitstates = 3,
.ahb_frequency = 96e6,
.apb1_frequency = 96e6,
.apb2_frequency = 96e6,
},
{ /* 170MHz */
.pllm = 3,
.plln = 85,
.pllp = 0,
.pllq = 0, /* USB requires CRS at this speed. */
.pllr = 2,
.pll_source = RCC_PLLCFGR_PLLSRC_HSE,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPREx_NODIV,
.ppre2 = RCC_CFGR_PPREx_NODIV,
.vos_scale = PWR_SCALE1,
.boost = true,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN,
.flash_waitstates = 4,
.ahb_frequency = 170e6,
.apb1_frequency = 170e6,
.apb2_frequency = 170e6,
},
};
const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = {
{ /* 24MHz */
.pllm = 2,
.plln = 12,
.pllp = 0,
.pllq = 2,
.pllr = 4,
.pll_source = RCC_PLLCFGR_PLLSRC_HSE,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPREx_NODIV,
.ppre2 = RCC_CFGR_PPREx_NODIV,
.vos_scale = PWR_SCALE2,
.boost = false,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN,
.flash_waitstates = 1,
.ahb_frequency = 24e6,
.apb1_frequency = 24e6,
.apb2_frequency = 24e6,
},
{ /* 48MHz */
.pllm = 2,
.plln = 12,
.pllp = 0,
.pllq = 2,
.pllr = 2,
.pll_source = RCC_PLLCFGR_PLLSRC_HSE,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPREx_NODIV,
.ppre2 = RCC_CFGR_PPREx_NODIV,
.vos_scale = PWR_SCALE1,
.boost = false,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN,
.flash_waitstates = 1,
.ahb_frequency = 48e6,
.apb1_frequency = 48e6,
.apb2_frequency = 48e6,
},
{ /* 96MHz */
.pllm = 2,
.plln = 24,
.pllp = 0,
.pllq = 4,
.pllr = 2,
.pll_source = RCC_PLLCFGR_PLLSRC_HSE,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPREx_NODIV,
.ppre2 = RCC_CFGR_PPREx_NODIV,
.vos_scale = PWR_SCALE1,
.boost = false,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN,
.flash_waitstates = 3,
.ahb_frequency = 96e6,
.apb1_frequency = 96e6,
.apb2_frequency = 96e6,
},
{ /* 170MHz */
.pllm = 4,
.plln = 85,
.pllp = 0,
.pllq = 0, /* USB requires CRS at this speed. */
.pllr = 2,
.pll_source = RCC_PLLCFGR_PLLSRC_HSE,
.hpre = RCC_CFGR_HPRE_NODIV,
.ppre1 = RCC_CFGR_PPREx_NODIV,
.ppre2 = RCC_CFGR_PPREx_NODIV,
.vos_scale = PWR_SCALE1,
.boost = true,
.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN,
.flash_waitstates = 4,
.ahb_frequency = 170e6,
.apb1_frequency = 170e6,
.apb2_frequency = 170e6,
},
};
void rcc_osc_ready_int_clear(enum rcc_osc osc)
{
switch (osc) {
case RCC_HSI48:
RCC_CICR |= RCC_CICR_HSI48RDYC;
break;
case RCC_PLL:
RCC_CICR |= RCC_CICR_PLLRDYC;
break;
case RCC_HSE:
RCC_CICR |= RCC_CICR_HSERDYC;
break;
case RCC_HSI16:
RCC_CICR |= RCC_CICR_HSIRDYC;
break;
case RCC_LSE:
RCC_CICR |= RCC_CICR_LSERDYC;
break;
case RCC_LSI:
RCC_CICR |= RCC_CICR_LSIRDYC;
break;
}
}
void rcc_osc_ready_int_enable(enum rcc_osc osc)
{
switch (osc) {
case RCC_HSI48:
RCC_CIER |= RCC_CIER_HSI48RDYIE;
break;
case RCC_PLL:
RCC_CIER |= RCC_CIER_PLLRDYIE;
break;
case RCC_HSE:
RCC_CIER |= RCC_CIER_HSERDYIE;
break;
case RCC_HSI16:
RCC_CIER |= RCC_CIER_HSIRDYIE;
break;
case RCC_LSE:
RCC_CIER |= RCC_CIER_LSERDYIE;
break;
case RCC_LSI:
RCC_CIER |= RCC_CIER_LSIRDYIE;
break;
}
}
void rcc_osc_ready_int_disable(enum rcc_osc osc)
{
switch (osc) {
case RCC_HSI48:
RCC_CIER &= ~RCC_CIER_HSI48RDYIE;
break;
case RCC_PLL:
RCC_CIER &= ~RCC_CIER_PLLRDYIE;
break;
case RCC_HSE:
RCC_CIER &= ~RCC_CIER_HSERDYIE;
break;
case RCC_HSI16:
RCC_CIER &= ~RCC_CIER_HSIRDYIE;
break;
case RCC_LSE:
RCC_CIER &= ~RCC_CIER_LSERDYIE;
break;
case RCC_LSI:
RCC_CIER &= ~RCC_CIER_LSIRDYIE;
break;
}
}
int rcc_osc_ready_int_flag(enum rcc_osc osc)
{
switch (osc) {
case RCC_HSI48:
return ((RCC_CIFR & RCC_CIFR_HSI48RDYF) != 0);
case RCC_PLL:
return ((RCC_CIFR & RCC_CIFR_PLLRDYF) != 0);
case RCC_HSE:
return ((RCC_CIFR & RCC_CIFR_HSERDYF) != 0);
case RCC_HSI16:
return ((RCC_CIFR & RCC_CIFR_HSIRDYF) != 0);
case RCC_LSE:
return ((RCC_CIFR & RCC_CIFR_LSERDYF) != 0);
case RCC_LSI:
return ((RCC_CIFR & RCC_CIFR_LSIRDYF) != 0);
}
return 0;
}
void rcc_css_int_clear(void)
{
RCC_CICR |= RCC_CICR_CSSC;
}
int rcc_css_int_flag(void)
{
return ((RCC_CIFR & RCC_CIFR_CSSF) != 0);
}
bool rcc_is_osc_ready(enum rcc_osc osc)
{
switch (osc) {
case RCC_HSI48:
return RCC_CRRCR & RCC_CRRCR_HSI48RDY;
case RCC_PLL:
return RCC_CR & RCC_CR_PLLRDY;
case RCC_HSE:
return RCC_CR & RCC_CR_HSERDY;
case RCC_HSI16:
return RCC_CR & RCC_CR_HSIRDY;
case RCC_LSE:
return RCC_BDCR & RCC_BDCR_LSERDY;
case RCC_LSI:
return RCC_CSR & RCC_CSR_LSIRDY;
}
return false;
}
void rcc_wait_for_osc_ready(enum rcc_osc osc)
{
while (!rcc_is_osc_ready(osc));
}
void rcc_wait_for_sysclk_status(enum rcc_osc osc)
{
switch (osc) {
case RCC_PLL:
while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK) !=
RCC_CFGR_SWx_PLL);
break;
case RCC_HSE:
while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK) !=
RCC_CFGR_SWx_HSE);
break;
case RCC_HSI16:
while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK) !=
RCC_CFGR_SWx_HSI16);
break;
default:
/* Shouldn't be reached. */
break;
}
}
void rcc_osc_on(enum rcc_osc osc)
{
switch (osc) {
case RCC_HSI48:
RCC_CRRCR |= RCC_CRRCR_HSI48ON;
break;
case RCC_PLL:
RCC_CR |= RCC_CR_PLLON;
break;
case RCC_HSE:
RCC_CR |= RCC_CR_HSEON;
break;
case RCC_HSI16:
RCC_CR |= RCC_CR_HSION;
break;
case RCC_LSE:
RCC_BDCR |= RCC_BDCR_LSEON;
break;
case RCC_LSI:
RCC_CSR |= RCC_CSR_LSION;
break;
}
}
void rcc_osc_off(enum rcc_osc osc)
{
switch (osc) {
case RCC_HSI48:
RCC_CRRCR &= ~RCC_CRRCR_HSI48ON;
break;
case RCC_PLL:
RCC_CR &= ~RCC_CR_PLLON;
break;
case RCC_HSE:
RCC_CR &= ~RCC_CR_HSEON;
break;
case RCC_HSI16:
RCC_CR &= ~RCC_CR_HSION;
break;
case RCC_LSE:
RCC_BDCR &= ~RCC_BDCR_LSEON;
break;
case RCC_LSI:
RCC_CSR &= ~RCC_CSR_LSION;
break;
}
}
void rcc_css_enable(void)
{
RCC_CR |= RCC_CR_CSSON;
}
void rcc_css_disable(void)
{
RCC_CR &= ~RCC_CR_CSSON;
}
void rcc_set_sysclk_source(uint32_t clk)
{
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~(RCC_CFGR_SW_MASK << RCC_CFGR_SW_SHIFT);
RCC_CFGR = (reg32 | (clk << RCC_CFGR_SW_SHIFT));
}
void rcc_set_pll_source(uint32_t pllsrc)
{
uint32_t reg32;
reg32 = RCC_PLLCFGR;
reg32 &= ~(RCC_PLLCFGR_PLLSRC_MASK << RCC_PLLCFGR_PLLSRC_SHIFT);
RCC_PLLCFGR = (reg32 | (pllsrc << RCC_PLLCFGR_PLLSRC_SHIFT));
}
void rcc_set_ppre2(uint32_t ppre2)
{
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~(RCC_CFGR_PPRE2_MASK << RCC_CFGR_PPRE2_SHIFT);
RCC_CFGR = (reg32 | (ppre2 << RCC_CFGR_PPRE2_SHIFT));
}
void rcc_set_ppre1(uint32_t ppre1)
{
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~(RCC_CFGR_PPRE1_MASK << RCC_CFGR_PPRE1_SHIFT);
RCC_CFGR = (reg32 | (ppre1 << RCC_CFGR_PPRE1_SHIFT));
}
void rcc_set_hpre(uint32_t hpre)
{
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~(RCC_CFGR_HPRE_MASK << RCC_CFGR_HPRE_SHIFT);
RCC_CFGR = (reg32 | (hpre << RCC_CFGR_HPRE_SHIFT));
}
/**
* Reconfigures the main PLL for a HSE source.
* Any reserved bits are kept at their reset values.
* @param pllsrc Source for the main PLL input clock
* @param pllm Divider for the main PLL input clock
* @param plln Main PLL multiplication factor for VCO
* @param pllp Main PLL divider for ADC
* @param pllq Main PLL divider for QUADSPI, FDCAN, USB, SAI & I2S
* @param pllr Main PLL divider for main system clock
*/
void rcc_set_main_pll(uint32_t pllsrc, uint32_t pllm, uint32_t plln,
uint32_t pllp, uint32_t pllq, uint32_t pllr)
{
bool pllpen = (pllp != 0);
bool pllqen = (pllq != 0);
bool pllren = (pllr != 0);
pllm -= 1;
uint32_t pllpdiv = pllp;
pllp = (pllpdiv == 17);
if ((pllpdiv == 7) || (pllpdiv == 17)) {
pllpdiv = 0;
}
pllr = (pllr >> 1) - 1;
pllq = (pllq >> 1) - 1;
RCC_PLLCFGR = ((pllsrc & RCC_PLLCFGR_PLLSRC_MASK) << RCC_PLLCFGR_PLLSRC_SHIFT) |
((pllm & RCC_PLLCFGR_PLLM_MASK) << RCC_PLLCFGR_PLLM_SHIFT) |
((plln & RCC_PLLCFGR_PLLN_MASK) << RCC_PLLCFGR_PLLN_SHIFT) |
(pllpen ? RCC_PLLCFGR_PLLPEN : 0 ) |
(pllp ? RCC_PLLCFGR_PLLP_DIV17 : RCC_PLLCFGR_PLLP_DIV7) |
(pllqen ? RCC_PLLCFGR_PLLQEN : 0 ) |
((pllq & RCC_PLLCFGR_PLLQ_MASK) << RCC_PLLCFGR_PLLQ_SHIFT) |
(pllren ? RCC_PLLCFGR_PLLREN : 0 ) |
((pllr & RCC_PLLCFGR_PLLR_MASK) << RCC_PLLCFGR_PLLR_SHIFT) |
((pllpdiv & RCC_PLLCFGR_PLLPDIV_MASK) << RCC_PLLCFGR_PLLPDIV_SHIFT);
}
uint32_t rcc_system_clock_source(void)
{
/* Return the clock source which is used as system clock. */
return (RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK;
}
/**
* Setup clocks to run from PLL.
*
* The arguments provide the pll source, multipliers, dividers, all that's
* needed to establish a system clock.
*
* @param clock clock information structure.
*/
void rcc_clock_setup_pll(const struct rcc_clock_scale *clock)
{
/* Enable internal high-speed oscillator (HSI16). */
rcc_osc_on(RCC_HSI16);
rcc_wait_for_osc_ready(RCC_HSI16);
/* Select HSI16 as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SWx_HSI16);
/* Enable external high-speed oscillator (HSE). */
if (clock->pll_source == RCC_PLLCFGR_PLLSRC_HSE) {
rcc_osc_on(RCC_HSE);
rcc_wait_for_osc_ready(RCC_HSE);
}
/* Set the VOS scale mode */
rcc_periph_clock_enable(RCC_PWR);
pwr_set_vos_scale(clock->vos_scale);
if (clock->boost) {
pwr_enable_boost();
} else {
pwr_disable_boost();
}
/*
* Set prescalers for AHB, ADC, APB1, APB2.
* Do this before touching the PLL (TODO: why?).
*/
rcc_set_hpre(clock->hpre);
rcc_set_ppre1(clock->ppre1);
rcc_set_ppre2(clock->ppre2);
/* Disable PLL oscillator before changing its configuration. */
rcc_osc_off(RCC_PLL);
/* Configure the PLL oscillator. */
rcc_set_main_pll(clock->pll_source,
clock->pllm, clock->plln,
clock->pllp, clock->pllq, clock->pllr);
/* Enable PLL oscillator and wait for it to stabilize. */
rcc_osc_on(RCC_PLL);
rcc_wait_for_osc_ready(RCC_PLL);
/* Configure flash settings. */
if (clock->flash_config & FLASH_ACR_DCEN) {
flash_dcache_enable();
} else {
flash_dcache_disable();
}
if (clock->flash_config & FLASH_ACR_ICEN) {
flash_icache_enable();
} else {
flash_icache_disable();
}
flash_set_ws(clock->flash_waitstates);
/* Select PLL as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SWx_PLL);
/* Wait for PLL clock to be selected. */
rcc_wait_for_sysclk_status(RCC_PLL);
/* Set the peripheral clock frequencies used. */
rcc_ahb_frequency = clock->ahb_frequency;
rcc_apb1_frequency = clock->apb1_frequency;
rcc_apb2_frequency = clock->apb2_frequency;
/* Disable internal high-speed oscillator. */
if (clock->pll_source == RCC_PLLCFGR_PLLSRC_HSE) {
rcc_osc_off(RCC_HSI16);
}
}
/**
* Setup clocks with the HSE.
*
* @deprecated replaced by rcc_clock_setup_pll as a drop in replacement.
* @see rcc_clock_setup_pll which supports HSI16 as well as HSE, using the same
* clock structures.
*/
void rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock)
{
rcc_clock_setup_pll(clock);
}
/** Set clock source for 48MHz clock
*
* The 48 MHz clock is derived from one of the four following sources:
* - PLLQ VCO (RCC_CCIPR_CLK48_PLLQ)
* - HSI48 internal oscillator (RCC_CCIPR_CLK48_HSI48)
*
* @param clksel One of the definitions above
*/
void rcc_set_clock48_source(uint32_t clksel)
{
RCC_CCIPR &= ~(RCC_CCIPR_SEL_MASK << RCC_CCIPR_CLK48_SHIFT);
RCC_CCIPR |= (clksel << RCC_CCIPR_CLK48_SHIFT);
}
/**@}*/

27
libopencm3/lib/stm32/g4/vector_chipset.c Normal file
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@@ -0,0 +1,27 @@
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#include <libopencm3/cm3/scb.h>
static void pre_main(void)
{
/* Enable access to Floating-Point coprocessor. */
SCB_CPACR |= SCB_CPACR_FULL * (SCB_CPACR_CP10 | SCB_CPACR_CP11);
}