git subrepo clone https://github.com/libopencm3/libopencm3
subrepo: subdir: "libopencm3" merged: "f5813a54" upstream: origin: "https://github.com/libopencm3/libopencm3" branch: "master" commit: "f5813a54" git-subrepo: version: "0.4.3" origin: "???" commit: "???"
This commit is contained in:
68
libopencm3/lib/stm32/l4/Makefile
Normal file
68
libopencm3/lib/stm32/l4/Makefile
Normal file
@@ -0,0 +1,68 @@
|
||||
##
|
||||
## This file is part of the libopencm3 project.
|
||||
##
|
||||
## Copyright (C) 2015 Karl Palsson <karlp@tweak.net.au>
|
||||
##
|
||||
## This library is free software: you can redistribute it and/or modify
|
||||
## it under the terms of the GNU Lesser General Public License as published by
|
||||
## the Free Software Foundation, either version 3 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This library is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU Lesser General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU Lesser General Public License
|
||||
## along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
##
|
||||
|
||||
LIBNAME = libopencm3_stm32l4
|
||||
SRCLIBDIR ?= ../..
|
||||
|
||||
FP_FLAGS ?= -mfloat-abi=hard -mfpu=fpv4-sp-d16
|
||||
CC = $(PREFIX)gcc
|
||||
AR = $(PREFIX)ar
|
||||
TGT_CFLAGS = -Os \
|
||||
-Wall -Wextra -Wimplicit-function-declaration \
|
||||
-Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \
|
||||
-Wundef -Wshadow \
|
||||
-I../../../include -fno-common \
|
||||
-mcpu=cortex-m4 -mthumb $(FP_FLAGS) \
|
||||
-Wstrict-prototypes \
|
||||
-ffunction-sections -fdata-sections -MD -DSTM32L4
|
||||
TGT_CFLAGS += $(DEBUG_FLAGS)
|
||||
TGT_CFLAGS += $(STANDARD_FLAGS)
|
||||
ARFLAGS = rcs
|
||||
|
||||
OBJS += adc.o adc_common_v2.o adc_common_v2_multi.o
|
||||
OBJS += can.o
|
||||
OBJS += crc_common_all.o crc_v2.o
|
||||
OBJS += crs_common_all.o
|
||||
OBJS += dac_common_all.o dac_common_v1.o
|
||||
OBJS += dma_common_l1f013.o dma_common_csel.o
|
||||
OBJS += exti_common_all.o
|
||||
OBJS += flash.o flash_common_all.o flash_common_f.o flash_common_idcache.o
|
||||
OBJS += gpio_common_all.o gpio_common_f0234.o
|
||||
OBJS += i2c_common_v2.o
|
||||
OBJS += iwdg_common_all.o
|
||||
OBJS += lptimer_common_all.o
|
||||
OBJS += pwr.o
|
||||
OBJS += rcc.o rcc_common_all.o
|
||||
OBJS += rng_common_v1.o
|
||||
OBJS += rtc_common_l1f024.o
|
||||
OBJS += spi_common_all.o spi_common_v2.o
|
||||
OBJS += timer_common_all.o
|
||||
OBJS += usart_common_all.o usart_common_v2.o
|
||||
OBJS += quadspi_common_v1.o
|
||||
|
||||
OBJS += usb.o usb_control.o usb_standard.o usb_msc.o
|
||||
OBJS += usb_hid.o
|
||||
OBJS += usb_audio.o usb_cdc.o usb_midi.o
|
||||
OBJS += st_usbfs_core.o st_usbfs_v2.o
|
||||
OBJS += usb_dwc_common.o usb_f107.o
|
||||
|
||||
VPATH += ../../usb:../:../../cm3:../common
|
||||
VPATH += ../../ethernet
|
||||
|
||||
include ../../Makefile.include
|
||||
56
libopencm3/lib/stm32/l4/adc.c
Normal file
56
libopencm3/lib/stm32/l4/adc.c
Normal file
@@ -0,0 +1,56 @@
|
||||
/** @addtogroup adc_file ADC peripheral API
|
||||
@ingroup peripheral_apis
|
||||
|
||||
@author @htmlonly © @endhtmlonly 2016 Karl Palsson <karlp@tweak.net.au>
|
||||
|
||||
|
||||
LGPL License Terms @ref lgpl_license
|
||||
*/
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2016 Karl Palsson <karlp@tweak.net.au>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <libopencm3/stm32/adc.h>
|
||||
|
||||
/**@{*/
|
||||
|
||||
/**
|
||||
* Enable the ADC Voltage regulator
|
||||
* Before any use of the ADC, the ADC Voltage regulator must be enabled.
|
||||
* You must wait up to 10uSecs afterwards before trying anything else.
|
||||
* @param[in] adc ADC block register address base
|
||||
* @sa adc_disable_regulator
|
||||
*/
|
||||
void adc_enable_regulator(uint32_t adc)
|
||||
{
|
||||
ADC_CR(adc) |= ADC_CR_ADVREGEN;
|
||||
}
|
||||
|
||||
/**
|
||||
* Disable the ADC Voltage regulator
|
||||
* You can disable the adc vreg when not in use to save power
|
||||
* @param[in] adc ADC block register address base
|
||||
* @sa adc_enable_regulator
|
||||
*/
|
||||
void adc_disable_regulator(uint32_t adc)
|
||||
{
|
||||
ADC_CR(adc) &= ~ADC_CR_ADVREGEN;
|
||||
}
|
||||
|
||||
/**@}*/
|
||||
|
||||
207
libopencm3/lib/stm32/l4/flash.c
Normal file
207
libopencm3/lib/stm32/l4/flash.c
Normal file
@@ -0,0 +1,207 @@
|
||||
/** @defgroup flash_file FLASH peripheral API
|
||||
*
|
||||
* @ingroup peripheral_apis
|
||||
*
|
||||
* @brief <b>libopencm3 STM32L4xx FLASH</b>
|
||||
*
|
||||
* @version 1.0.0
|
||||
*
|
||||
* Benjamin Levine <benjamin@jesco.karoo.co.uk>
|
||||
*
|
||||
* @date 12 February 2016
|
||||
*
|
||||
* This library supports the FLASH memory controller in the STM32L4
|
||||
* series of ARM Cortex Microcontrollers by ST Microelectronics.
|
||||
*
|
||||
* For the STM32L4xx, accessing FLASH memory is described briefly in
|
||||
* section 3 of the STM32L4x6 Reference Manual.
|
||||
*
|
||||
* LGPL License Terms @ref lgpl_license
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2016 Benjamin Levine <benjamin@jesco.karoo.co.uk>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/**@{*/
|
||||
|
||||
#include <libopencm3/stm32/flash.h>
|
||||
|
||||
/** @brief Wait until Last Operation has Ended
|
||||
* This loops indefinitely until an operation (write or erase) has completed
|
||||
* by testing the busy flag.
|
||||
*/
|
||||
void flash_wait_for_last_operation(void)
|
||||
{
|
||||
while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY);
|
||||
}
|
||||
|
||||
/** @brief Clear the Programming Sequence Error Flag
|
||||
* This flag is set when incorrect programming configuration has been made.
|
||||
*/
|
||||
void flash_clear_pgserr_flag(void)
|
||||
{
|
||||
FLASH_SR |= FLASH_SR_PGSERR;
|
||||
}
|
||||
|
||||
/** Clear programming size error flag */
|
||||
void flash_clear_size_flag(void)
|
||||
{
|
||||
FLASH_SR |= FLASH_SR_SIZERR;
|
||||
}
|
||||
|
||||
/** @brief Clear the Programming Alignment Error Flag
|
||||
*/
|
||||
void flash_clear_pgaerr_flag(void)
|
||||
{
|
||||
FLASH_SR |= FLASH_SR_PGAERR;
|
||||
}
|
||||
|
||||
/** @brief Clear the Write Protect Error Flag
|
||||
*/
|
||||
void flash_clear_wrperr_flag(void)
|
||||
{
|
||||
FLASH_SR |= FLASH_SR_WRPERR;
|
||||
}
|
||||
|
||||
/** @brief Clear the Programming Error Status Flag
|
||||
*/
|
||||
void flash_clear_progerr_flag(void)
|
||||
{
|
||||
FLASH_SR |= FLASH_SR_PROGERR;
|
||||
}
|
||||
|
||||
/** @brief Clear All Status Flags
|
||||
* Program error, end of operation, write protect error, busy.
|
||||
*/
|
||||
void flash_clear_status_flags(void)
|
||||
{
|
||||
flash_clear_pgserr_flag();
|
||||
flash_clear_size_flag();
|
||||
flash_clear_pgaerr_flag();
|
||||
flash_clear_wrperr_flag();
|
||||
flash_clear_progerr_flag();
|
||||
flash_clear_eop_flag();
|
||||
}
|
||||
|
||||
/** @brief Lock the Option Byte Access
|
||||
* This disables write access to the option bytes. It is locked by default on
|
||||
* reset.
|
||||
*/
|
||||
void flash_lock_option_bytes(void)
|
||||
{
|
||||
FLASH_CR |= FLASH_CR_OPTLOCK;
|
||||
}
|
||||
|
||||
/** @brief Program a 64 bit word to FLASH
|
||||
*
|
||||
* This performs all operations necessary to program a 64 bit word to FLASH memory.
|
||||
* The program error flag should be checked separately for the event that memory
|
||||
* was not properly erased.
|
||||
*
|
||||
* @param[in] address Starting address in Flash.
|
||||
* @param[in] data Double word to write
|
||||
*/
|
||||
void flash_program_double_word(uint32_t address, uint64_t data)
|
||||
{
|
||||
/* Ensure that all flash operations are complete. */
|
||||
flash_wait_for_last_operation();
|
||||
|
||||
/* Enable writes to flash. */
|
||||
FLASH_CR |= FLASH_CR_PG;
|
||||
|
||||
/* Program the each word separately. */
|
||||
MMIO32(address) = (uint32_t)data;
|
||||
MMIO32(address+4) = (uint32_t)(data >> 32);
|
||||
|
||||
/* Wait for the write to complete. */
|
||||
flash_wait_for_last_operation();
|
||||
|
||||
/* Disable writes to flash. */
|
||||
FLASH_CR &= ~FLASH_CR_PG;
|
||||
}
|
||||
|
||||
/** @brief Program a Data Block to FLASH
|
||||
* This programs an arbitrary length data block to FLASH memory.
|
||||
* The program error flag should be checked separately for the event that
|
||||
* memory was not properly erased.
|
||||
* @param[in] address Starting address in Flash.
|
||||
* @param[in] data Pointer to start of data block.
|
||||
* @param[in] len Length of data block in bytes (multiple of 8).
|
||||
*/
|
||||
void flash_program(uint32_t address, uint8_t *data, uint32_t len)
|
||||
{
|
||||
for (uint32_t i = 0; i < len; i += 8) {
|
||||
flash_program_double_word(address+i, *(uint64_t*)(data + i));
|
||||
}
|
||||
}
|
||||
|
||||
/** @brief Erase a page of FLASH
|
||||
* @param[in] page (0 - 255 for bank 1, 256-511 for bank 2)
|
||||
*/
|
||||
void flash_erase_page(uint32_t page)
|
||||
{
|
||||
flash_wait_for_last_operation();
|
||||
|
||||
/* page and bank are contiguous bits */
|
||||
FLASH_CR &= ~((FLASH_CR_PNB_MASK << FLASH_CR_PNB_SHIFT) | FLASH_CR_BKER);
|
||||
if (page > 255) {
|
||||
FLASH_CR |= FLASH_CR_BKER;
|
||||
}
|
||||
FLASH_CR |= page << FLASH_CR_PNB_SHIFT;
|
||||
FLASH_CR |= FLASH_CR_PER;
|
||||
FLASH_CR |= FLASH_CR_START;
|
||||
|
||||
flash_wait_for_last_operation();
|
||||
FLASH_CR &= ~FLASH_CR_PER;
|
||||
}
|
||||
|
||||
/** @brief Erase All FLASH
|
||||
* This performs all operations necessary to erase all sectors in the FLASH
|
||||
* memory.
|
||||
*/
|
||||
void flash_erase_all_pages(void)
|
||||
{
|
||||
flash_wait_for_last_operation();
|
||||
|
||||
FLASH_CR |= FLASH_CR_MER1 | FLASH_CR_MER2;
|
||||
FLASH_CR |= FLASH_CR_START;
|
||||
|
||||
flash_wait_for_last_operation();
|
||||
FLASH_CR &= ~FLASH_CR_MER1 & ~FLASH_CR_MER2;
|
||||
}
|
||||
|
||||
/** @brief Program the Option Bytes
|
||||
* This performs all operations necessary to program the option bytes.
|
||||
* The option bytes do not need to be erased first.
|
||||
* @param[in] data value to be programmed.
|
||||
*/
|
||||
void flash_program_option_bytes(uint32_t data)
|
||||
{
|
||||
flash_wait_for_last_operation();
|
||||
|
||||
if (FLASH_CR & FLASH_CR_OPTLOCK) {
|
||||
flash_unlock_option_bytes();
|
||||
}
|
||||
|
||||
FLASH_OPTR = data;
|
||||
FLASH_CR |= FLASH_CR_OPTSTRT;
|
||||
flash_wait_for_last_operation();
|
||||
}
|
||||
/**@}*/
|
||||
|
||||
32
libopencm3/lib/stm32/l4/i2c.c
Normal file
32
libopencm3/lib/stm32/l4/i2c.c
Normal file
@@ -0,0 +1,32 @@
|
||||
/** @defgroup i2c_file I2C
|
||||
*
|
||||
* @ingroup STM32L4xx
|
||||
*
|
||||
* @brief <b>libopencm3 STM32L4xx I2C</b>
|
||||
*
|
||||
* @version 1.0.0
|
||||
*
|
||||
* @date 1 December 2016
|
||||
*
|
||||
* LGPL License Terms @ref lgpl_license
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <libopencm3/stm32/i2c.h>
|
||||
|
||||
75
libopencm3/lib/stm32/l4/pwr.c
Normal file
75
libopencm3/lib/stm32/l4/pwr.c
Normal file
@@ -0,0 +1,75 @@
|
||||
/** @defgroup pwr_file PWR peripheral API
|
||||
*
|
||||
* @ingroup peripheral_apis
|
||||
*
|
||||
* @brief <b>libopencm3 STM32L4xx Power Control</b>
|
||||
*
|
||||
* @version 1.0.0
|
||||
*
|
||||
* @author @htmlonly © @endhtmlonly 2016 Benjamin Levine <benjamin@jesco.karoo.co.uk>
|
||||
*
|
||||
* @date 4 March 2013
|
||||
*
|
||||
* This library supports the power control system for the
|
||||
* STM32L4 series of ARM Cortex Microcontrollers by ST Microelectronics.
|
||||
*
|
||||
* LGPL License Terms @ref lgpl_license
|
||||
*/
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2016 Benjamin Levine <benjamin@jesco.karoo.co.uk>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
/**@{*/
|
||||
#include <libopencm3/stm32/pwr.h>
|
||||
|
||||
void pwr_set_vos_scale(enum pwr_vos_scale scale)
|
||||
{
|
||||
uint32_t reg32;
|
||||
|
||||
reg32 = PWR_CR1;
|
||||
reg32 &= ~(PWR_CR1_VOS_MASK << PWR_CR1_VOS_SHIFT);
|
||||
switch (scale) {
|
||||
case PWR_SCALE1:
|
||||
reg32 |= (PWR_CR1_VOS_RANGE_1 << PWR_CR1_VOS_SHIFT);
|
||||
break;
|
||||
case PWR_SCALE2:
|
||||
reg32 |= (PWR_CR1_VOS_RANGE_2 << PWR_CR1_VOS_SHIFT);
|
||||
break;
|
||||
}
|
||||
PWR_CR1 = reg32;
|
||||
}
|
||||
|
||||
/** Disable Backup Domain Write Protection
|
||||
*
|
||||
* This allows backup domain registers to be changed. These registers are write
|
||||
* protected after a reset.
|
||||
*/
|
||||
void pwr_disable_backup_domain_write_protect(void)
|
||||
{
|
||||
PWR_CR1 |= PWR_CR1_DBP;
|
||||
}
|
||||
|
||||
/** Re-enable Backup Domain Write Protection
|
||||
*
|
||||
* This protects backup domain registers from inadvertent change.
|
||||
*/
|
||||
void pwr_enable_backup_domain_write_protect(void)
|
||||
{
|
||||
PWR_CR1 &= ~PWR_CR1_DBP;
|
||||
}
|
||||
|
||||
/**@}*/
|
||||
519
libopencm3/lib/stm32/l4/rcc.c
Normal file
519
libopencm3/lib/stm32/l4/rcc.c
Normal file
@@ -0,0 +1,519 @@
|
||||
/** @defgroup rcc_file RCC peripheral API
|
||||
*
|
||||
* @ingroup peripheral_apis
|
||||
*
|
||||
* @section rcc_l4_api_ex Reset and Clock Control API.
|
||||
*
|
||||
* @brief <b>libopencm3 STM32L4xx Reset and Clock Control</b>
|
||||
*
|
||||
* @author @htmlonly © @endhtmlonly 2016 Karl Palsson <karlp@tweak.net.au>
|
||||
*
|
||||
* @date 12 Feb 2016
|
||||
*
|
||||
* This library supports the Reset and Clock Control System in the STM32 series
|
||||
* of ARM Cortex Microcontrollers by ST Microelectronics.
|
||||
*
|
||||
* LGPL License Terms @ref lgpl_license
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2016 Karl Palsson <karlp@tweak.net.au>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/**@{*/
|
||||
#include <libopencm3/cm3/assert.h>
|
||||
#include <libopencm3/stm32/rcc.h>
|
||||
|
||||
/* Set the default clock frequencies after reset. */
|
||||
uint32_t rcc_ahb_frequency = 4000000;
|
||||
uint32_t rcc_apb1_frequency = 4000000;
|
||||
uint32_t rcc_apb2_frequency = 4000000;
|
||||
|
||||
void rcc_osc_ready_int_clear(enum rcc_osc osc)
|
||||
{
|
||||
switch (osc) {
|
||||
case RCC_PLL:
|
||||
RCC_CICR |= RCC_CICR_PLLRDYC;
|
||||
break;
|
||||
case RCC_HSE:
|
||||
RCC_CICR |= RCC_CICR_HSERDYC;
|
||||
break;
|
||||
case RCC_HSI16:
|
||||
RCC_CICR |= RCC_CICR_HSIRDYC;
|
||||
break;
|
||||
case RCC_MSI:
|
||||
RCC_CICR |= RCC_CICR_MSIRDYC;
|
||||
break;
|
||||
case RCC_LSE:
|
||||
RCC_CICR |= RCC_CICR_LSERDYC;
|
||||
break;
|
||||
case RCC_LSI:
|
||||
RCC_CICR |= RCC_CICR_LSIRDYC;
|
||||
break;
|
||||
case RCC_HSI48:
|
||||
RCC_CICR |= RCC_CICR_HSI48RDYC;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void rcc_osc_ready_int_enable(enum rcc_osc osc)
|
||||
{
|
||||
switch (osc) {
|
||||
case RCC_PLL:
|
||||
RCC_CIER |= RCC_CIER_PLLRDYIE;
|
||||
break;
|
||||
case RCC_HSE:
|
||||
RCC_CIER |= RCC_CIER_HSERDYIE;
|
||||
break;
|
||||
case RCC_HSI16:
|
||||
RCC_CIER |= RCC_CIER_HSIRDYIE;
|
||||
break;
|
||||
case RCC_MSI:
|
||||
RCC_CIER |= RCC_CIER_MSIRDYIE;
|
||||
break;
|
||||
case RCC_LSE:
|
||||
RCC_CIER |= RCC_CIER_LSERDYIE;
|
||||
break;
|
||||
case RCC_LSI:
|
||||
RCC_CIER |= RCC_CIER_LSIRDYIE;
|
||||
break;
|
||||
case RCC_HSI48:
|
||||
RCC_CIER |= RCC_CIER_HSI48RDYIE;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void rcc_osc_ready_int_disable(enum rcc_osc osc)
|
||||
{
|
||||
switch (osc) {
|
||||
case RCC_PLL:
|
||||
RCC_CIER &= ~RCC_CIER_PLLRDYIE;
|
||||
break;
|
||||
case RCC_HSE:
|
||||
RCC_CIER &= ~RCC_CIER_HSERDYIE;
|
||||
break;
|
||||
case RCC_HSI16:
|
||||
RCC_CIER &= ~RCC_CIER_HSIRDYIE;
|
||||
break;
|
||||
case RCC_MSI:
|
||||
RCC_CIER &= ~RCC_CIER_MSIRDYIE;
|
||||
break;
|
||||
case RCC_LSE:
|
||||
RCC_CIER &= ~RCC_CIER_LSERDYIE;
|
||||
break;
|
||||
case RCC_LSI:
|
||||
RCC_CIER &= ~RCC_CIER_LSIRDYIE;
|
||||
break;
|
||||
case RCC_HSI48:
|
||||
RCC_CIER &= ~RCC_CIER_HSI48RDYIE;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
int rcc_osc_ready_int_flag(enum rcc_osc osc)
|
||||
{
|
||||
switch (osc) {
|
||||
case RCC_PLL:
|
||||
return ((RCC_CIFR & RCC_CIFR_PLLRDYF) != 0);
|
||||
break;
|
||||
case RCC_HSE:
|
||||
return ((RCC_CIFR & RCC_CIFR_HSERDYF) != 0);
|
||||
break;
|
||||
case RCC_HSI16:
|
||||
return ((RCC_CIFR & RCC_CIFR_HSIRDYF) != 0);
|
||||
break;
|
||||
case RCC_MSI:
|
||||
return ((RCC_CIFR & RCC_CIFR_MSIRDYF) != 0);
|
||||
break;
|
||||
case RCC_LSE:
|
||||
return ((RCC_CIFR & RCC_CIFR_LSERDYF) != 0);
|
||||
break;
|
||||
case RCC_LSI:
|
||||
return ((RCC_CIFR & RCC_CIFR_LSIRDYF) != 0);
|
||||
break;
|
||||
case RCC_HSI48:
|
||||
return ((RCC_CIFR & RCC_CIFR_HSI48RDYF) != 0);
|
||||
break;
|
||||
}
|
||||
return false;
|
||||
|
||||
}
|
||||
|
||||
void rcc_css_int_clear(void)
|
||||
{
|
||||
RCC_CICR |= RCC_CICR_CSSC;
|
||||
}
|
||||
|
||||
int rcc_css_int_flag(void)
|
||||
{
|
||||
return ((RCC_CIFR & RCC_CIFR_CSSF) != 0);
|
||||
}
|
||||
|
||||
bool rcc_is_osc_ready(enum rcc_osc osc)
|
||||
{
|
||||
switch (osc) {
|
||||
case RCC_PLL:
|
||||
return RCC_CR & RCC_CR_PLLRDY;
|
||||
case RCC_HSE:
|
||||
return RCC_CR & RCC_CR_HSERDY;
|
||||
case RCC_HSI16:
|
||||
return RCC_CR & RCC_CR_HSIRDY;
|
||||
case RCC_MSI:
|
||||
return RCC_CR & RCC_CR_MSIRDY;
|
||||
case RCC_LSE:
|
||||
return RCC_BDCR & RCC_BDCR_LSERDY;
|
||||
case RCC_LSI:
|
||||
return RCC_CSR & RCC_CSR_LSIRDY;
|
||||
case RCC_HSI48:
|
||||
return RCC_CRRCR & RCC_CRRCR_HSI48RDY;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
void rcc_wait_for_osc_ready(enum rcc_osc osc)
|
||||
{
|
||||
while (!rcc_is_osc_ready(osc));
|
||||
}
|
||||
|
||||
void rcc_wait_for_sysclk_status(enum rcc_osc osc)
|
||||
{
|
||||
switch (osc) {
|
||||
case RCC_PLL:
|
||||
while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK)
|
||||
!= RCC_CFGR_SWS_PLL);
|
||||
break;
|
||||
case RCC_HSE:
|
||||
while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK)
|
||||
!= RCC_CFGR_SWS_HSE);
|
||||
break;
|
||||
case RCC_HSI16:
|
||||
while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK)
|
||||
!= RCC_CFGR_SWS_HSI16);
|
||||
break;
|
||||
case RCC_MSI:
|
||||
while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK)
|
||||
!= RCC_CFGR_SWS_MSI);
|
||||
break;
|
||||
default:
|
||||
/* Shouldn't be reached. */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void rcc_osc_on(enum rcc_osc osc)
|
||||
{
|
||||
switch (osc) {
|
||||
case RCC_PLL:
|
||||
RCC_CR |= RCC_CR_PLLON;
|
||||
break;
|
||||
case RCC_HSE:
|
||||
RCC_CR |= RCC_CR_HSEON;
|
||||
break;
|
||||
case RCC_HSI16:
|
||||
RCC_CR |= RCC_CR_HSION;
|
||||
break;
|
||||
case RCC_MSI:
|
||||
RCC_CR |= RCC_CR_MSION;
|
||||
break;
|
||||
case RCC_LSE:
|
||||
RCC_BDCR |= RCC_BDCR_LSEON;
|
||||
break;
|
||||
case RCC_LSI:
|
||||
RCC_CSR |= RCC_CSR_LSION;
|
||||
break;
|
||||
case RCC_HSI48:
|
||||
RCC_CRRCR |= RCC_CRRCR_HSI48ON;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void rcc_osc_off(enum rcc_osc osc)
|
||||
{
|
||||
switch (osc) {
|
||||
case RCC_PLL:
|
||||
RCC_CR &= ~RCC_CR_PLLON;
|
||||
break;
|
||||
case RCC_HSE:
|
||||
RCC_CR &= ~RCC_CR_HSEON;
|
||||
break;
|
||||
case RCC_HSI16:
|
||||
RCC_CR &= ~RCC_CR_HSION;
|
||||
break;
|
||||
case RCC_MSI:
|
||||
RCC_CR &= ~RCC_CR_MSION;
|
||||
break;
|
||||
case RCC_LSE:
|
||||
RCC_BDCR &= ~RCC_BDCR_LSEON;
|
||||
break;
|
||||
case RCC_LSI:
|
||||
RCC_CSR &= ~RCC_CSR_LSION;
|
||||
break;
|
||||
case RCC_HSI48:
|
||||
RCC_CRRCR &= ~RCC_CRRCR_HSI48ON;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void rcc_css_enable(void)
|
||||
{
|
||||
RCC_CR |= RCC_CR_CSSON;
|
||||
}
|
||||
|
||||
void rcc_css_disable(void)
|
||||
{
|
||||
RCC_CR &= ~RCC_CR_CSSON;
|
||||
}
|
||||
|
||||
void rcc_set_sysclk_source(uint32_t clk)
|
||||
{
|
||||
uint32_t reg32;
|
||||
|
||||
reg32 = RCC_CFGR;
|
||||
reg32 &= ~(RCC_CFGR_SW_MASK << RCC_CFGR_SW_SHIFT);
|
||||
RCC_CFGR = (reg32 | (clk << RCC_CFGR_SW_SHIFT));
|
||||
}
|
||||
|
||||
void rcc_set_pll_source(uint32_t pllsrc)
|
||||
{
|
||||
uint32_t reg32;
|
||||
|
||||
reg32 = RCC_PLLCFGR;
|
||||
reg32 &= ~(RCC_PLLCFGR_PLLSRC_MASK << RCC_PLLCFGR_PLLSRC_SHIFT);
|
||||
RCC_PLLCFGR = (reg32 | (pllsrc << RCC_PLLCFGR_PLLSRC_SHIFT));
|
||||
}
|
||||
|
||||
void rcc_set_ppre2(uint32_t ppre2)
|
||||
{
|
||||
uint32_t reg32;
|
||||
|
||||
reg32 = RCC_CFGR;
|
||||
reg32 &= ~(RCC_CFGR_PPRE2_MASK << RCC_CFGR_PPRE2_SHIFT);
|
||||
RCC_CFGR = (reg32 | (ppre2 << RCC_CFGR_PPRE2_SHIFT));
|
||||
}
|
||||
|
||||
void rcc_set_ppre1(uint32_t ppre1)
|
||||
{
|
||||
uint32_t reg32;
|
||||
|
||||
reg32 = RCC_CFGR;
|
||||
reg32 &= ~(RCC_CFGR_PPRE1_MASK << RCC_CFGR_PPRE1_SHIFT);
|
||||
RCC_CFGR = (reg32 | (ppre1 << RCC_CFGR_PPRE1_SHIFT));
|
||||
}
|
||||
|
||||
void rcc_set_hpre(uint32_t hpre)
|
||||
{
|
||||
uint32_t reg32;
|
||||
|
||||
reg32 = RCC_CFGR;
|
||||
reg32 &= ~(RCC_CFGR_HPRE_MASK << RCC_CFGR_HPRE_SHIFT);
|
||||
RCC_CFGR = (reg32 | (hpre << RCC_CFGR_HPRE_SHIFT));
|
||||
}
|
||||
|
||||
void rcc_set_main_pll(uint32_t source, uint32_t pllm, uint32_t plln, uint32_t pllp,
|
||||
uint32_t pllq, uint32_t pllr)
|
||||
{
|
||||
RCC_PLLCFGR = (RCC_PLLCFGR_PLLM(pllm) << RCC_PLLCFGR_PLLM_SHIFT) |
|
||||
(plln << RCC_PLLCFGR_PLLN_SHIFT) |
|
||||
(pllp) |
|
||||
(source << RCC_PLLCFGR_PLLSRC_SHIFT) |
|
||||
(pllq << RCC_PLLCFGR_PLLQ_SHIFT) |
|
||||
(pllr << RCC_PLLCFGR_PLLR_SHIFT) | RCC_PLLCFGR_PLLREN;
|
||||
}
|
||||
|
||||
uint32_t rcc_system_clock_source(void)
|
||||
{
|
||||
/* Return the clock source which is used as system clock. */
|
||||
return (RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the msi run time range.
|
||||
* Can only be called when MSI is either OFF, or when MSI is on _and_
|
||||
* ready. (RCC_CR_MSIRDY bit). @sa rcc_set_msi_range_standby
|
||||
* @param msi_range range number @ref rcc_cr_msirange
|
||||
*/
|
||||
void rcc_set_msi_range(uint32_t msi_range)
|
||||
{
|
||||
uint32_t reg = RCC_CR;
|
||||
reg &= ~(RCC_CR_MSIRANGE_MASK << RCC_CR_MSIRANGE_SHIFT);
|
||||
reg |= msi_range << RCC_CR_MSIRANGE_SHIFT;
|
||||
RCC_CR = reg | RCC_CR_MSIRGSEL;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set the msi range after reset/standby.
|
||||
* Until MSIRGSEl bit is set, this defines the MSI range.
|
||||
* Note that not all MSI range values are allowed here!
|
||||
* @sa rcc_set_msi_range
|
||||
* @param msi_range range number valid for post standby @ref rcc_csr_msirange
|
||||
*/
|
||||
void rcc_set_msi_range_standby(uint32_t msi_range)
|
||||
{
|
||||
uint32_t reg = RCC_CSR;
|
||||
reg &= ~(RCC_CSR_MSIRANGE_MASK << RCC_CSR_MSIRANGE_SHIFT);
|
||||
reg |= msi_range << RCC_CSR_MSIRANGE_SHIFT;
|
||||
RCC_CSR = reg;
|
||||
}
|
||||
|
||||
/** Enable PLL Output
|
||||
*
|
||||
* - P (RCC_PLLCFGR_PLLPEN)
|
||||
* - Q (RCC_PLLCFGR_PLLQEN)
|
||||
* - R (RCC_PLLCFGR_PLLREN)
|
||||
*
|
||||
* @param pllout One or more of the definitions above
|
||||
*/
|
||||
void rcc_pll_output_enable(uint32_t pllout)
|
||||
{
|
||||
RCC_PLLCFGR |= pllout;
|
||||
}
|
||||
|
||||
/** Set clock source for 48MHz clock
|
||||
*
|
||||
* The 48 MHz clock is derived from one of the four following sources:
|
||||
* - main PLL VCO (RCC_CCIPR_CLK48SEL_PLL)
|
||||
* - PLLSAI1 VCO (RCC_CCIPR_CLK48SEL_PLLSAI1Q)
|
||||
* - MSI clock (RCC_CCIPR_CLK48SEL_MSI)
|
||||
* - HSI48 internal oscillator (RCC_CCIPR_CLK48SEL_HSI48)
|
||||
*
|
||||
* @param clksel One of the definitions above
|
||||
*/
|
||||
void rcc_set_clock48_source(uint32_t clksel)
|
||||
{
|
||||
RCC_CCIPR &= ~(RCC_CCIPR_CLK48SEL_MASK << RCC_CCIPR_CLK48SEL_SHIFT);
|
||||
RCC_CCIPR |= (clksel << RCC_CCIPR_CLK48SEL_SHIFT);
|
||||
}
|
||||
|
||||
|
||||
/** Enable the RTC clock */
|
||||
void rcc_enable_rtc_clock(void)
|
||||
{
|
||||
RCC_BDCR |= RCC_BDCR_RTCEN;
|
||||
}
|
||||
|
||||
/** Disable the RTC clock */
|
||||
void rcc_disable_rtc_clock(void)
|
||||
{
|
||||
RCC_BDCR &= ~RCC_BDCR_RTCEN;
|
||||
}
|
||||
|
||||
/** Set the source for the RTC clock
|
||||
* @param[in] clk ::rcc_osc. RTC clock source. Only HSE/32, LSE and LSI.
|
||||
*/
|
||||
void rcc_set_rtc_clock_source(enum rcc_osc clk)
|
||||
{
|
||||
RCC_BDCR &= ~(RCC_BDCR_RTCSEL_MASK << RCC_BDCR_RTCSEL_SHIFT);
|
||||
|
||||
switch (clk) {
|
||||
case RCC_HSE:
|
||||
RCC_BDCR |= (RCC_BDCR_RTCSEL_HSEDIV32 << RCC_BDCR_RTCSEL_SHIFT);
|
||||
break;
|
||||
case RCC_LSE:
|
||||
RCC_BDCR |= (RCC_BDCR_RTCSEL_LSE << RCC_BDCR_RTCSEL_SHIFT);
|
||||
break;
|
||||
case RCC_LSI:
|
||||
RCC_BDCR |= (RCC_BDCR_RTCSEL_LSI << RCC_BDCR_RTCSEL_SHIFT);
|
||||
break;
|
||||
default:
|
||||
/* none selected */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Helper to calculate the frequency of a UART/I2C based on the apb and clksel value. */
|
||||
static uint32_t rcc_uart_i2c_clksel_freq_hz(uint32_t apb_clk, uint8_t shift) {
|
||||
uint8_t clksel = (RCC_CCIPR >> shift) & RCC_CCIPR_USARTxSEL_MASK;
|
||||
uint8_t hpre = (RCC_CFGR >> RCC_CFGR_HPRE_SHIFT) & RCC_CFGR_HPRE_MASK;
|
||||
switch (clksel) {
|
||||
case RCC_CCIPR_USARTxSEL_APB:
|
||||
return apb_clk;
|
||||
case RCC_CCIPR_USARTxSEL_SYS:
|
||||
return rcc_ahb_frequency * rcc_get_div_from_hpre(hpre);
|
||||
case RCC_CCIPR_USARTxSEL_HSI16:
|
||||
return 16000000U;
|
||||
}
|
||||
cm3_assert_not_reached();
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief Get the peripheral clock speed for the USART at base specified.
|
||||
* @param usart Base address of USART to get clock frequency for.
|
||||
*/
|
||||
uint32_t rcc_get_usart_clk_freq(uint32_t usart)
|
||||
{
|
||||
/* Handle values with selectable clocks. */
|
||||
if (usart == LPUART1_BASE) {
|
||||
return rcc_uart_i2c_clksel_freq_hz(rcc_apb2_frequency, RCC_CCIPR_LPUART1SEL_SHIFT);
|
||||
} else if (usart == USART1_BASE) {
|
||||
return rcc_uart_i2c_clksel_freq_hz(rcc_apb1_frequency, RCC_CCIPR_USART1SEL_SHIFT);
|
||||
} else if (usart == USART2_BASE) {
|
||||
return rcc_uart_i2c_clksel_freq_hz(rcc_apb1_frequency, RCC_CCIPR_USART2SEL_SHIFT);
|
||||
} else if (usart == USART3_BASE) {
|
||||
return rcc_uart_i2c_clksel_freq_hz(rcc_apb1_frequency, RCC_CCIPR_USART3SEL_SHIFT);
|
||||
} else if (usart == UART4_BASE) {
|
||||
return rcc_uart_i2c_clksel_freq_hz(rcc_apb1_frequency, RCC_CCIPR_UART4SEL_SHIFT);
|
||||
} else { /* USART5 */
|
||||
return rcc_uart_i2c_clksel_freq_hz(rcc_apb1_frequency, RCC_CCIPR_UART5SEL_SHIFT);
|
||||
}
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief Get the peripheral clock speed for the Timer at base specified.
|
||||
* @param timer Base address of TIM to get clock frequency for.
|
||||
*/
|
||||
uint32_t rcc_get_timer_clk_freq(uint32_t timer)
|
||||
{
|
||||
/* Handle APB1 timers, and apply multiplier if necessary. */
|
||||
if (timer >= TIM2_BASE && timer <= TIM7_BASE) {
|
||||
uint8_t ppre1 = (RCC_CFGR >> RCC_CFGR_PPRE1_SHIFT) & RCC_CFGR_PPRE1_MASK;
|
||||
return (ppre1 == RCC_CFGR_PPRE1_NODIV) ? rcc_apb1_frequency
|
||||
: 2 * rcc_apb1_frequency;
|
||||
} else {
|
||||
uint8_t ppre2 = (RCC_CFGR >> RCC_CFGR_PPRE2_SHIFT) & RCC_CFGR_PPRE2_MASK;
|
||||
return (ppre2 == RCC_CFGR_PPRE2_NODIV) ? rcc_apb2_frequency
|
||||
: 2 * rcc_apb2_frequency;
|
||||
}
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief Get the peripheral clock speed for the I2C device at base specified.
|
||||
* @param i2c Base address of I2C to get clock frequency for.
|
||||
*/
|
||||
uint32_t rcc_get_i2c_clk_freq(uint32_t i2c)
|
||||
{
|
||||
if (i2c == I2C1_BASE) {
|
||||
return rcc_uart_i2c_clksel_freq_hz(rcc_apb1_frequency, RCC_CCIPR_I2C1SEL_SHIFT);
|
||||
} else if (i2c == I2C2_BASE) {
|
||||
return rcc_uart_i2c_clksel_freq_hz(rcc_apb1_frequency, RCC_CCIPR_I2C2SEL_SHIFT);
|
||||
} else { /* I2C3 */
|
||||
return rcc_uart_i2c_clksel_freq_hz(rcc_apb1_frequency, RCC_CCIPR_I2C3SEL_SHIFT);
|
||||
}
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief Get the peripheral clock speed for the SPI device at base specified.
|
||||
* @param spi Base address of SPI device to get clock frequency for (e.g. SPI1_BASE).
|
||||
*/
|
||||
uint32_t rcc_get_spi_clk_freq(uint32_t spi) {
|
||||
if (spi == SPI1_BASE) {
|
||||
return rcc_apb2_frequency;
|
||||
} else {
|
||||
return rcc_apb1_frequency;
|
||||
}
|
||||
}
|
||||
/**@}*/
|
||||
27
libopencm3/lib/stm32/l4/vector_chipset.c
Normal file
27
libopencm3/lib/stm32/l4/vector_chipset.c
Normal file
@@ -0,0 +1,27 @@
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
|
||||
* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <libopencm3/cm3/scb.h>
|
||||
|
||||
static void pre_main(void)
|
||||
{
|
||||
/* Enable access to Floating-Point coprocessor. */
|
||||
SCB_CPACR |= SCB_CPACR_FULL * (SCB_CPACR_CP10 | SCB_CPACR_CP11);
|
||||
}
|
||||
Reference in New Issue
Block a user