Arti Zirk
244fdbc35c
subrepo: subdir: "libopencm3" merged: "f5813a54" upstream: origin: "https://github.com/libopencm3/libopencm3" branch: "master" commit: "f5813a54" git-subrepo: version: "0.4.3" origin: "???" commit: "???"
225 lines
8.9 KiB
C
225 lines
8.9 KiB
C
/** @defgroup anadig_defines ANADIG Defines
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*
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* @brief <b>Defined Constants and Types for the VF6xx Analog components
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* control digital interface</b>
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*
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* @ingroup VF6xx_defines
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*
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* @version 1.0.0
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*
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* @author @htmlonly © @endhtmlonly 2014
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* Stefan Agner <stefan@agner.ch>
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*
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* @date 01 July 2014
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*
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* LGPL License Terms @ref lgpl_license
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* */
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2014 Stefan Agner <stefan@agner.ch>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_ANADIG_H
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#define LIBOPENCM3_ANADIG_H
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/vf6xx/memorymap.h>
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/* --- ANADIG registers ---------------------------------------------------- */
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#define ANADIG_PLL3_CTRL MMIO32(ANADIG_BASE + 0x010)
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#define ANADIG_PLL7_CTRL MMIO32(ANADIG_BASE + 0x020)
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#define ANADIG_PLL2_CTRL MMIO32(ANADIG_BASE + 0x030)
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#define ANADIG_PLL2_SS MMIO32(ANADIG_BASE + 0x040)
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#define ANADIG_PLL2_NUM MMIO32(ANADIG_BASE + 0x050)
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#define ANADIG_PLL2_DENOM MMIO32(ANADIG_BASE + 0x060)
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#define ANADIG_PLL4_CTRL MMIO32(ANADIG_BASE + 0x070)
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#define ANADIG_PLL4_NUM MMIO32(ANADIG_BASE + 0x080)
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#define ANADIG_PLL4_DENOM MMIO32(ANADIG_BASE + 0x090)
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#define ANADIG_PLL6_CTRL MMIO32(ANADIG_BASE + 0x0A0)
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#define ANADIG_PLL6_NUM MMIO32(ANADIG_BASE + 0x0B0)
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#define ANADIG_PLL6_DENOM MMIO32(ANADIG_BASE + 0x0C0)
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#define ANADIG_PLL5_CTRL MMIO32(ANADIG_BASE + 0x0E0)
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#define ANADIG_PLL3_PFD MMIO32(ANADIG_BASE + 0x0F0)
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#define ANADIG_PLL2_PFD MMIO32(ANADIG_BASE + 0x100)
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#define ANADIG_REG_1P1 MMIO32(ANADIG_BASE + 0x110)
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#define ANADIG_REG_3P0 MMIO32(ANADIG_BASE + 0x120)
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#define ANADIG_REG_2P5 MMIO32(ANADIG_BASE + 0x130)
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#define ANADIG_ANA_MISC0 MMIO32(ANADIG_BASE + 0x150)
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#define ANADIG_ANA_MISC1 MMIO32(ANADIG_BASE + 0x160)
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#define ANADIG_ANADIG_DIGPROG MMIO32(ANADIG_BASE + 0x260)
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#define ANADIG_PLL1_CTRL MMIO32(ANADIG_BASE + 0x270)
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#define ANADIG_PLL1_SS MMIO32(ANADIG_BASE + 0x280)
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#define ANADIG_PLL1_NUM MMIO32(ANADIG_BASE + 0x290)
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#define ANADIG_PLL1_DENOM MMIO32(ANADIG_BASE + 0x2A0)
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#define ANADIG_PLL1_PFD MMIO32(ANADIG_BASE + 0x2B0)
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#define ANADIG_PLL_LOCK MMIO32(ANADIG_BASE + 0x2C0)
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/* --- ANADIG values -....-------------------------------------------------- */
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/* ANADIG_PLL3_CTRL: PLL3 Control Register (480MHz PLL of USB0) */
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#define ANADIG_PLL3_CTRL_LOCK (1 << 31)
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#define ANADIG_PLL3_CTRL_BYPASS (1 << 16)
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#define ANADIG_PLL3_CTRL_BYPASS_CLK_SRC (1 << 14)
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#define ANADIG_PLL3_CTRL_ENABLE (1 << 13)
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#define ANADIG_PLL3_CTRL_POWER (1 << 12)
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#define ANADIG_PLL3_CTRL_EN_USB_CLKS (1 << 6)
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#define ANADIG_PLL3_CTRL_DIV_SELECT (1 << 1)
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/* ANADIG_PLL7_CTRL: PLL7 Control Register (480MHz PLL of USB1) */
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#define ANADIG_PLL7_CTRL_LOCK (1 << 31)
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#define ANADIG_PLL7_CTRL_BYPASS (1 << 16)
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#define ANADIG_PLL7_CTRL_BYPASS_CLK_SRC (1 << 14)
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#define ANADIG_PLL7_CTRL_ENABLE (1 << 13)
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#define ANADIG_PLL7_CTRL_POWER (1 << 12)
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#define ANADIG_PLL7_CTRL_EN_USB_CLKS (1 << 6)
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#define ANADIG_PLL7_CTRL_DIV_SELECT (1 << 1)
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/* ANADIG_PLL2_CTRL: PLL2 Control Register (528MHz PLL) */
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#define ANADIG_PLL2_CTRL_LOCK (1 << 31)
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#define ANADIG_PLL2_CTRL_PFD_OFFSET_EN (1 << 18)
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#define ANADIG_PLL2_CTRL_DITHER_ENABLE (1 << 17)
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#define ANADIG_PLL2_CTRL_BYPASS (1 << 16)
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#define ANADIG_PLL2_CTRL_BYPASS_CLK_SRC (1 << 14)
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#define ANADIG_PLL2_CTRL_ENABLE (1 << 13)
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#define ANADIG_PLL2_CTRL_POWERDOWN (1 << 12)
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#define ANADIG_PLL2_CTRL_DIV_SELECT (1 << 1)
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/* ANADIG_PLL2_SS: PLL2 Spread Spectrum definition register */
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#define ANADIG_PLL2_SS_STOP_MASK (0xffff << 16)
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#define ANADIG_PLL2_SS_ENABLE (1 << 15)
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#define ANADIG_PLL2_SS_STEP_MASK 0x8fff
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/* ANADIG_PLL2_NUM: PLL2 Numerator definition register */
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#define ANADIG_PLL2_NUM_MFN_MASK 0x3fffffff
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/* ANADIG_PLL2_DENOM: PLL2 Denominator definition register */
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#define ANADIG_PLL2_DENOM_MFN_MASK 0x3fffffff
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/* ANADIG_PLL4_CTRL: PLL4 Control Register (audio PLL) */
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#define ANADIG_PLL4_CTRL_LOCK (1 << 31)
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#define ANADIG_PLL4_CTRL_PFD_OFFSET_EN (1 << 18)
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#define ANADIG_PLL4_CTRL_DITHER_ENABLE (1 << 17)
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#define ANADIG_PLL4_CTRL_BYPASS (1 << 16)
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#define ANADIG_PLL4_CTRL_BYPASS_CLK_SRC (1 << 14)
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#define ANADIG_PLL4_CTRL_ENABLE (1 << 13)
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#define ANADIG_PLL4_CTRL_POWERDOWN (1 << 12)
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#define ANADIG_PLL4_CTRL_DIV_SELECT_MASK (0x7f)
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/* ANADIG_PLL4_NUM: PLL4 Numerator definition register */
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#define ANADIG_PLL4_NUM_MFN_MASK 0x3fffffff
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/* ANADIG_PLL4_DENOM: PLL4 Denominator definition register */
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#define ANADIG_PLL4_DENOM_MFN_MASK 0x3fffffff
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/* ANADIG_PLL6_CTRL: PLL6 Control Register (video PLL) */
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#define ANADIG_PLL6_CTRL_LOCK (1 << 31)
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#define ANADIG_PLL6_CTRL_PFD_OFFSET_EN (1 << 18)
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#define ANADIG_PLL6_CTRL_DITHER_ENABLE (1 << 17)
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#define ANADIG_PLL6_CTRL_BYPASS (1 << 16)
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#define ANADIG_PLL6_CTRL_BYPASS_CLK_SRC (1 << 14)
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#define ANADIG_PLL6_CTRL_ENABLE (1 << 13)
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#define ANADIG_PLL6_CTRL_POWERDOWN (1 << 12)
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#define ANADIG_PLL6_CTRL_DIV_SELECT_MASK (0x7f)
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/* ANADIG_PLL6_NUM: PLL6 Numerator definition register */
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#define ANADIG_PLL6_NUM_MFN_MASK 0x3fffffff
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/* ANADIG_PLL6_DENOM: PLL6 Denominator definition register */
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#define ANADIG_PLL6_DENOM_MFN_MASK 0x3fffffff
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/* ANADIG_PLL5_CTRL: PLL5 Control Register (video PLL) */
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#define ANADIG_PLL5_CTRL_LOCK (1 << 31)
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#define ANADIG_PLL5_CTRL_PFD_OFFSET_EN (1 << 18)
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#define ANADIG_PLL5_CTRL_DITHER_ENABLE (1 << 17)
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#define ANADIG_PLL5_CTRL_BYPASS (1 << 16)
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#define ANADIG_PLL5_CTRL_BYPASS_CLK_SRC (1 << 14)
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#define ANADIG_PLL5_CTRL_ENABLE (1 << 13)
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#define ANADIG_PLL5_CTRL_POWERDOWN (1 << 12)
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#define ANADIG_PLL5_CTRL_DIV_SELECT_MASK (0x3)
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/* ANADIG_PLL_PFD: PLL1/PLL2/PLL3 PFD Clocks */
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#define ANADIG_PLL_PFD4_CLKGATE (1 << 31)
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#define ANADIG_PLL_PFD4_STABLE (1 << 30)
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#define ANADIG_PLL_PFD4_FRAC_SHIFT 24
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#define ANADIG_PLL_PFD4_FRAC_MASK (0x3f << 24)
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#define ANADIG_PLL_PFD3_CLKGATE (1 << 23)
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#define ANADIG_PLL_PFD3_STABLE (1 << 22)
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#define ANADIG_PLL_PFD3_FRAC_SHIFT 16
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#define ANADIG_PLL_PFD3_FRAC_MASK (0x3f << 16)
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#define ANADIG_PLL_PFD2_CLKGATE (1 << 15)
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#define ANADIG_PLL_PFD2_STABLE (1 << 14)
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#define ANADIG_PLL_PFD2_FRAC_SHIFT 8
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#define ANADIG_PLL_PFD2_FRAC_MASK (0x3f << 8)
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#define ANADIG_PLL_PFD1_CLKGATE (1 << 7)
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#define ANADIG_PLL_PFD1_STABLE (1 << 6)
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#define ANADIG_PLL_PFD1_FRAC_SHIFT 0
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#define ANADIG_PLL_PFD1_FRAC_MASK (0x3f << 0)
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/* AANADIG_ANA_MISC0: miscellaneous analog blocks */
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#define ANADIG_ANA_MISC0_OSC_XTALOK_EN (1 << 17)
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#define ANADIG_ANA_MISC0_OSC_XTALOK (1 << 16)
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#define ANADIG_ANA_MISC0_CLK_24M_IRC_XTAL_SEL (1 << 13)
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#define ANADIG_ANA_MISC0_STOP_MODE_CONFIG (1 << 12)
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#define ANADIG_ANA_MISC0_REFTOP_VBGUP (1 << 7)
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#define ANADIG_ANA_MISC0_REFTOP_SELBIASOFF (1 << 3)
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#define ANADIG_ANA_MISC0_REFTOP_LOWPOWER (1 << 2)
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#define ANADIG_ANA_MISC0_REFTOP_PWDVBGUP (1 << 1)
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#define ANADIG_ANA_MISC0_REFTOP_PWD (1 << 0)
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/* AANADIG_ANA_MISC0: miscellaneous analog blocks */
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#define ANADIG_ANA_MISC1_IRQ_ANA_BO (1 << 30)
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#define ANADIG_ANA_MISC1_IRQ_TEMPSENSE (1 << 29)
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#define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
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#define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
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/* AANADIG_ANA_DIGPROG: Digital Program register */
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#define ANADIG_ANADIG_DIGPROG_MAJOR_MASK (0xffff << 8)
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#define ANADIG_ANADIG_DIGPROG_MINOR_MASK (0xff << 0)
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/* ANADIG_PLL1_CTRL: PLL1 Control Register (video PLL) */
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#define ANADIG_PLL1_CTRL_LOCK (1 << 31)
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#define ANADIG_PLL1_CTRL_PFD_OFFSET_EN (1 << 18)
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#define ANADIG_PLL1_CTRL_DITHER_ENABLE (1 << 17)
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#define ANADIG_PLL1_CTRL_BYPASS (1 << 16)
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#define ANADIG_PLL1_CTRL_BYPASS_CLK_SRC (1 << 14)
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#define ANADIG_PLL1_CTRL_ENABLE (1 << 13)
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#define ANADIG_PLL1_CTRL_POWERDOWN (1 << 12)
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#define ANADIG_PLL1_CTRL_DIV_SELECT (1 << 1)
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/* ANADIG_PLL1_SS: PLL1 Spread Spectrum definition register */
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#define ANADIG_PLL1_SS_STOP_MASK (0xffff << 16)
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#define ANADIG_PLL1_SS_ENABLE (1 << 15)
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#define ANADIG_PLL1_SS_STEP_MASK 0x8fff
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/* ANADIG_PLL1_NUM: PLL1 Numerator definition register */
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#define ANADIG_PLL1_NUM_MFN_MASK 0x3fffffff
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/* ANADIG_PLL1_DENOM: PLL1 Denominator definition register */
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#define ANADIG_PLL1_DENOM_MFN_MASK 0x3fffffff
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/* ANADIG_PLL_LOCK: PLL Lock Register */
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#define ANADIG_PLL_LOCK_PLL1 (1 << 6)
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#define ANADIG_PLL_LOCK_PLL2 (1 << 5)
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#define ANADIG_PLL_LOCK_PLL4 (1 << 4)
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#define ANADIG_PLL_LOCK_PLL6 (1 << 3)
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#define ANADIG_PLL_LOCK_PLL5 (1 << 2)
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#define ANADIG_PLL_LOCK_PLL3 (1 << 1)
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#define ANADIG_PLL_LOCK_PLL7 (1 << 0)
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#endif
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