Arti Zirk
244fdbc35c
subrepo: subdir: "libopencm3" merged: "f5813a54" upstream: origin: "https://github.com/libopencm3/libopencm3" branch: "master" commit: "f5813a54" git-subrepo: version: "0.4.3" origin: "???" commit: "???"
352 lines
7.9 KiB
C
352 lines
7.9 KiB
C
/** @defgroup ccm_defines CCM Defines
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*
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* @brief <b>Defined Constants and Types for the VF6xx Common Clock Module</b>
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*
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* @ingroup VF6xx_defines
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*
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* @version 1.0.0
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*
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* @author @htmlonly © @endhtmlonly 2014
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* Stefan Agner <stefan@agner.ch>
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*
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* @date 30 June 2014
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*
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* LGPL License Terms @ref lgpl_license
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* */
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2014 Stefan Agner <stefan@agner.ch>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_CCM_H
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#define LIBOPENCM3_CCM_H
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/vf6xx/memorymap.h>
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/* --- CCM registers ------------------------------------------------------- */
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#define CCM_CCR MMIO32(CCM_BASE + 0x00)
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#define CCM_CSR MMIO32(CCM_BASE + 0x04)
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#define CCM_CCSR MMIO32(CCM_BASE + 0x08)
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#define CCM_CACRR MMIO32(CCM_BASE + 0x0C)
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#define CCM_CSCMR1 MMIO32(CCM_BASE + 0x10)
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#define CCM_CSCDR1 MMIO32(CCM_BASE + 0x14)
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#define CCM_CSCDR2 MMIO32(CCM_BASE + 0x18)
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#define CCM_CSCDR3 MMIO32(CCM_BASE + 0x1C)
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#define CCM_CSCMR2 MMIO32(CCM_BASE + 0x20)
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#define CCM_CTOR MMIO32(CCM_BASE + 0x28)
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#define CCM_CLPCR MMIO32(CCM_BASE + 0x2C)
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#define CCM_CISR MMIO32(CCM_BASE + 0x30)
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#define CCM_CIMR MMIO32(CCM_BASE + 0x34)
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#define CCM_CCOSR MMIO32(CCM_BASE + 0x38)
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#define CCM_CGPR MMIO32(CCM_BASE + 0x3C)
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#define CCM_CCGR(offset) MMIO32(CCM_BASE + 0x40 + (offset))
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#define CCM_CMEOR(ovrr) MMIO32(CCM_BASE + 0x70 + (4 * (ovrr)))
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#define CCM_CPPDSR MMIO32(CCM_BASE + 0x88)
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#define CCM_CCOWR MMIO32(CCM_BASE + 0x8C)
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#define CCM_CCPGR(pcgr) MMIO32(CCM_BASE + 0x90 + (4 * (pcgr)))
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/* --- CCM values -....----------------------------------------------------- */
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/* CCR: CCM Control Register */
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#define CCM_CCR_FIRC_EN (1 << 16)
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#define CCM_CCR_FXOSC_EN (1 << 12)
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#define CCM_CCR_OSCNT_MASK 0xff
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/* CSR: CCM Status Register */
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#define CCM_CSR_FXOSC_RDY (1 << 5)
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/* CCSR: CCM Clock Switcher Register */
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#define CCM_CCSR_PLL3_PFDN4_EN (1 << 31)
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#define CCM_CCSR_PLL3_PFDN3_EN (1 << 30)
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#define CCM_CCSR_PLL3_PFDN2_EN (1 << 29)
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#define CCM_CCSR_PLL3_PFDN1_EN (1 << 28)
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#define CCM_CCSR_DAP_EN (1 << 24)
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/* PLL1/PLL2 PFD SEL definition */
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#define CCM_CCSR_PLL2_PFD_CLK_SEL_SHIFT 19
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#define CCM_CCSR_PLL2_PFD_CLK_SEL_MASK (0x7 << 19)
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#define CCM_CCSR_PLL1_PFD_CLK_SEL_SHIFT 16
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#define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK (0x7 << 16)
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#define CCM_CCSR_PLL_PFD_CLK_SEL_MAIN 0x0
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#define CCM_CCSR_PLL_PFD_CLK_SEL_PFD1 0x1
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#define CCM_CCSR_PLL_PFD_CLK_SEL_PFD2 0x2
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#define CCM_CCSR_PLL_PFD_CLK_SEL_PFD3 0x3
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#define CCM_CCSR_PLL_PFD_CLK_SEL_PFD4 0x4
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#define CCM_CCSR_PLL2_PFDN4_EN (1 << 15)
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#define CCM_CCSR_PLL2_PFDN3_EN (1 << 14)
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#define CCM_CCSR_PLL2_PFDN2_EN (1 << 13)
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#define CCM_CCSR_PLL2_PFDN1_EN (1 << 12)
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#define CCM_CCSR_PLL1_PFDN4_EN (1 << 11)
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#define CCM_CCSR_PLL1_PFDN3_EN (1 << 10)
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#define CCM_CCSR_PLL1_PFDN2_EN (1 << 9)
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#define CCM_CCSR_PLL1_PFDN1_EN (1 << 8)
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#define CCM_CCSR_DDRC_CLK_SEL (1 << 7)
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#define CCM_CCSR_FAST_CLK_SEL (1 << 6)
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#define CCM_CCSR_SLOW_CLK_SEL (1 << 5)
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#define CCM_CCSR_SYS_CLK_SEL_SHIFT 0
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#define CCM_CCSR_SYS_CLK_SEL_MASK 0x7
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#define CCM_CCSR_SYS_CLK_SEL_FAST 0x0
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#define CCM_CCSR_SYS_CLK_SEL_SLOW 0x1
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#define CCM_CCSR_SYS_CLK_SEL_PLL2_PFD 0x2
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#define CCM_CCSR_SYS_CLK_SEL_PLL2 0x3
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#define CCM_CCSR_SYS_CLK_SEL_PLL1_PFD 0x4
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#define CCM_CCSR_SYS_CLK_SEL_PLL3 0x5
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/* CACRR: ARM Clock Root Register */
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#define CCM_CACRR_FLEX_CLK_DIV_SHIFT 22
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#define CCM_CACRR_FLEX_CLK_DIV_MASK (0x7 << 22)
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#define CCM_CACRR_PLL6_CLK_DIV (1 << 21)
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#define CCM_CACRR_PLL3_CLK_DIV (1 << 20)
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#define CCM_CACRR_PLL1_PFD_CLK_DIV_SHIFT 16
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#define CCM_CACRR_PLL1_PFD_CLK_DIV_MASK (0x3 << 16)
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#define CCM_CACRR_IPG_CLK_DIV_SHIFT 11
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#define CCM_CACRR_IPG_CLK_DIV_MASK (0x3 << 11)
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#define CCM_CACRR_PLL4_CLK_DIV_SHIFT 6
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#define CCM_CACRR_PLL4_CLK_DIV_MASK (0x7 << 6)
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#define CCM_CACRR_BUS_CLK_DIV_SHIFT 3
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#define CCM_CACRR_BUS_CLK_DIV_MASK (0x7 << 3)
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#define CCM_CACRR_ARM_CLK_DIV_SHIFT 0
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#define CCM_CACRR_ARM_CLK_DIV_MASK (0x7 << 0)
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/* --- Variable definitions ------------------------------------------------ */
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extern uint32_t ccm_core_clk;
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extern uint32_t ccm_platform_bus_clk;
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extern uint32_t ccm_ipg_bus_clk;
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enum ccm_clock_gate {
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/* AIPS0 */
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CG0_FLEXCAN0 = 0,
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CG1_RESERVED,
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CG2_RESERVED,
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CG3_RESERVED,
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CG4_DMA_MUX0,
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CG5_DMA_MUX1,
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CG6_RESERVED,
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CG7_UART0,
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CG8_UART1,
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CG9_UART2,
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CG10_UART3,
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CG11_RESERVED,
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CG12_SPI0,
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CG13_SPI1,
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CG14_RESERVED,
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CG15_SAI0,
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CG16_SAI1,
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CG17_SAI2,
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CG18_SAI3,
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CG19_CRC,
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CG20_USBC0,
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CG21_RESERVED,
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CG22_PDB,
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CG23_PIT,
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CG24_FTM0,
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CG25_FTM1,
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CG26_RESERVED,
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CG27_ADC0,
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CG28_RESERVED,
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CG29_TCON0,
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CG30_WDOG_A5,
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CG31_WDOG_M4,
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CG32_LPTMR,
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CG33_RESERVED,
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CG34_RLE,
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CG35_RESERVED,
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CG36_QSPI0,
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CG37_RESERVED,
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CG38_RESERVED,
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CG39_RESERVED,
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CG40_IOMUX,
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CG41_PORTA,
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CG42_PORTB,
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CG43_PORTC,
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CG44_PORTD,
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CG45_PORTE,
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CG46_RESERVED,
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CG47_RESERVED,
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CG48_ANADIG,
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CG49_RESERVED,
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CG50_SCSCM,
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CG51_RESERVED,
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CG52_RESERVED,
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CG53_RESERVED,
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CG54_RESERVED,
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CG55_RESERVED,
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CG56_DCU0,
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CG57_RESERVED,
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CG58_RESERVED,
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CG59_RESERVED,
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CG60_RESERVED,
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CG61_RESERVED,
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CG62_RESERVED,
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CG63_RESERVED,
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CG64_ASRC,
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CG65_SPDIF,
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CG66_ESAI,
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CG67_RESERVED,
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CG68_RESERVED,
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CG69_EWM,
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CG70_I2C0,
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CG71_I2C1,
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CG72_RESERVED,
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CG73_RESERVED,
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CG74_WKUP,
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CG75_CCM,
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CG76_GPC,
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CG77_VREG_DIG,
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CG78_RESERVED,
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CG79_CMU,
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CG80_NOTUSED,
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CG81_NOTUSED,
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CG82_NOTUSED,
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CG83_NOTUSED,
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CG84_NOTUSED,
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CG85_NOTUSED,
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CG86_NOTUSED,
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CG87_NOTUSED,
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CG88_NOTUSED,
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CG89_NOTUSED,
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CG90_NOTUSED,
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CG91_NOTUSED,
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CG92_NOTUSED,
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CG93_NOTUSED,
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CG94_NOTUSED,
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CG95_NOTUSED,
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/* AIPS1 */
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CG96_RESERVED,
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CG97_DMA_MUX2,
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CG98_DMA_MUX3,
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CG99_RESERVED,
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CG100_RESERVED,
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CG101_OTP_CTRL,
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CG102_RESERVED,
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CG103_RESERVED,
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CG104_RESERVED,
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CG105_UART4,
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CG106_UART5,
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CG107_RESERVED,
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CG108_SPI2,
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CG109_SPI3,
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CG110_DDRMC,
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CG111_RESERVED,
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CG112_RESERVED,
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CG113_SDHC0,
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CG114_SDHC1,
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CG115_RESERVED,
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CG116_USBC1,
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CG117_RESERVED,
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CG118_RESERVED,
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CG119_RESERVED,
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CG120_FTM2,
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CG121_FTM3,
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CG122_RESERVED,
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CG123_ADC1,
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CG124_RESERVED,
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CG125_TCON1,
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CG126_SEG_LCD,
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CG127_RESERVED,
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CG128_RESERVED,
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CG129_RESERVED,
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CG130_RESERVED,
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CG131_RESERVED,
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CG132_QSPI1,
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CG133_RESERVED,
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CG134_RESERVED,
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CG135_VADC,
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CG136_VDEC,
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CG137_VIU3,
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CG138_RESERVED,
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CG139_RESERVED,
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CG140_DAC0,
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CG141_DAC1,
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CG142_RESERVED,
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CG143_NOTUSED,
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CG144_ETH0_1588,
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CG145_ETH1_1588,
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CG146_RESERVED,
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CG147_RESERVED,
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CG148_FLEXCAN1,
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CG149_RESERVED,
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CG150_RESERVED,
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CG151_RESERVED,
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CG152_DCU1,
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CG153_RESERVED,
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CG154_RESERVED,
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CG155_RESERVED,
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CG156_RESERVED,
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CG157_RESERVED,
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CG158_RESERVED,
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CG159_RESERVED,
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CG160_NFC,
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CG161_RESERVED,
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CG162_RESERVED,
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CG163_RESERVED,
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CG164_RESERVED,
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CG165_RESERVED,
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CG166_I2C2,
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CG167_I2C3,
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CG168_ETH_L2,
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CG169_RESERVED,
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CG170_RESERVED,
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CG171_RESERVED,
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CG172_RESERVED,
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CG173_RESERVED,
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CG174_RESERVED,
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CG175_RESERVED,
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CG176_RESERVED,
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CG177_RESERVED,
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CG178_RESERVED,
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CG179_RESERVED,
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CG180_RESERVED,
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CG181_RESERVED,
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CG182_RESERVED,
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CG183_RESERVED,
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CG184_RESERVED,
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CG185_RESERVED,
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CG186_RESERVED,
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CG187_RESERVED,
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CG188_RESERVED,
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CG189_RESERVED,
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CG190_RESERVED,
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CG191_RESERVED
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};
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/* --- Function prototypes ------------------------------------------------- */
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#include <libopencm3/cm3/common.h>
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BEGIN_DECLS
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void ccm_clock_gate_enable(enum ccm_clock_gate gr);
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void ccm_clock_gate_disable(enum ccm_clock_gate gr);
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void ccm_calculate_clocks(void);
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END_DECLS
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#endif
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