201 lines
7.2 KiB
C
201 lines
7.2 KiB
C
/**
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* @defgroup usart_api USART peripheral API
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* @ingroup peripheral_apis
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* @brief <b>PAC55xxxx USART Driver</b>
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* @author @htmlonly © @endhtmlonly 2020 Kevin Stefanik <kevin@allocor.tech>
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* @date February 25, 2020
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*
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* This library supports the USART module in the PAC55xx SoC from Qorvo.
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/pac55xx/usart.h>
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#include <libopencm3/cm3/common.h>
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/**@{*/
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/** @brief USART Set Baudrate
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The baud rate is computed assuming a peripheral clock of 150MHz.
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@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
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@param[in] baud unsigned 32 bit. Baud rate specified in Hz.
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@return Actual baud rate.
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*/
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uint32_t usart_set_baudrate(uint32_t usart, uint32_t baud) {
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/* TODO Assumes 150MHz PCLK. Update this to ccs_get_peripheral_freq() like on other platforms */
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const uint32_t pclk = 150000000;
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uint32_t denom = (baud << 4); /* denominator is baud * 16. */
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uint32_t dlr = 0xFFFFu & ((pclk + denom / 2) / denom);
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USART_DLR(usart) = dlr;
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return pclk / (dlr << 4); /* Baud Rate = PCLK / (16 * UARTADLR) */
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}
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/** @brief USART Configure Line Control Register
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This register sets the data bits, stop bits, and parity
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@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
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@param[in] data_bits unsigned 8 bit. One of USART_DATABITS_5/6/7/8.
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@param[in] stop_bits unsigned 8 bit. One of USART_STOPBITS_1/1P5/2.
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@param[in] parity unsigned 8 bit. One of USART_PARITY_DISABLE/ODD/EVEN/FORCE1/FORCE0
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*/
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void usart_configure_lcr(uint32_t usart, uint8_t data_bits, uint8_t stop_bits,
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uint8_t parity) {
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USART_LCR(usart) = USART_LCR_WLS(data_bits)
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| ((stop_bits==USART_STOPBITS_2) ? USART_LCR_SBS : 0)
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| USART_LCR_PSELPEN(parity);
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}
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/** @brief Enable Break Control
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Enables break control bit that forces TX pin to logic low.
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@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
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*/
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void usart_break_enable(uint32_t usart) {
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USART_LCR(usart) |= USART_LCR_BCON;
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}
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/** @brief Disable Break Control
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Disables break control bit that forces TX pin to logic low.
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@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
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*/
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void usart_break_disable(uint32_t usart) {
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USART_LCR(usart) &= ~USART_LCR_BCON;
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}
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/** @brief Enable Enhanced Mode
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Enable enhanced mode to generate interrupts when FIFO thresholds in FCR are reached.
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@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
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*/
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void usart_enhanced_enable(uint32_t usart) {
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USART_EFR(usart) = USART_EFR_ENMODE;
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}
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/** @brief Disable Enhanced Mode
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Disable enhanced mode to generate interrupts when FIFO thresholds in FCR are reached.
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@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
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*/
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void usart_enhanced_disable(uint32_t usart) {
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USART_EFR(usart) &= ~USART_EFR_ENMODE;
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}
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/** @brief Enable FIFOs
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Enable both TX and RX FIFOs. This must be set before setting the trigger levels.
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@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
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*/
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void usart_fifo_enable(uint32_t usart) {
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USART_FCR(usart) |= USART_FCR_FIFOEN;
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}
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/** @brief Disable FIFOs
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Disable both TX and RX FIFOs.
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@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
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*/
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void usart_fifo_disable(uint32_t usart) {
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USART_FCR(usart) &= ~USART_FCR_FIFOEN;
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}
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/** Set the TX and RX FIFO depth. This function also enables the FIFOs if not already.
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@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
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@param[in] tx_depth unsigned 8 bit. One of USART_FIFO_TRIG_1/2/4/14CHAR.
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@param[in] rx_depth unsigned 8 bit. One of USART_FIFO_TRIG_1/2/4/14CHAR.
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*/
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void usart_set_fifo_depth(uint32_t usart, uint8_t tx_depth, uint8_t rx_depth) {
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USART_FCR(usart) |= USART_FCR_FIFOEN;
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USART_FCR(usart) = USART_FCR_TXTL(tx_depth) | USART_FCR_RXTL(rx_depth) | USART_FCR_FIFOEN;
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}
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/** @brief Write byte to TX FIFO
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@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
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@param[in] data unsigned 8 bit. Data to write to the TX FIFO.
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*/
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void usart_send(uint32_t usart, uint8_t data) {
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USART_THR(usart) = (uint32_t)data;
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}
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/** @brief Read byte from the RX FIFO
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@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
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@return Data read from the RX FIFO.
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*/
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uint8_t usart_recv(uint32_t usart) {
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return (uint8_t)USART_RBR(usart);
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}
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/** @brief Enable RX Interrupts
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Enable both the Receive Data Available and Character Timeout interrupts.
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@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
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*/
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void usart_enable_rx_interrupt(uint32_t usart) {
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USART_IER(usart) |= USART_IER_RBRIE;
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}
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/** @brief Disable RX Interrupts
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Disable both the Receive Data Available and Character Timeout interrupts.
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@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
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*/
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void usart_disable_rx_interrupt(uint32_t usart) {
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USART_IER(usart) &= ~USART_IER_RBRIE;
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}
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/** @brief Enable TX Interrupt
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Enable the TX Holding Register Empty interrupt.
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@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
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*/
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void usart_enable_tx_interrupt(uint32_t usart) {
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USART_IER(usart) |= USART_IER_THRIE;
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}
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/** @brief Disable TX Interrupt
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Disable the TX Holding Register Empty interrupt.
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@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
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*/
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void usart_disable_tx_interrupt(uint32_t usart) {
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USART_IER(usart) &= ~USART_IER_THRIE;
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}
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/** @brief Enable RX Line Status Interrupt
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Enable the RX Line Status interrupt.
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@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
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*/
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void usart_enable_rls_interrupt(uint32_t usart) {
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USART_IER(usart) |= USART_IER_RLSIE;
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}
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/** @brief Disable RX Line Status Interrupt
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Disable the RX Line Status interrupt.
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@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
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*/
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void usart_disable_rls_interrupt(uint32_t usart) {
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USART_IER(usart) &= ~USART_IER_RLSIE;
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}
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/** @brief Clear the TX FIFO
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Clears the TX FIFO. The bit is self-clearing.
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@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
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*/
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void usart_clear_tx_fifo(uint32_t usart) {
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USART_FCR(usart) |= USART_FCR_TXFIFORST;
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}
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/** @brief Clear the RX FIFO
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Clears the RX FIFO. The bit is self-clearing.
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@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base
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*/
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void usart_clear_rx_fifo(uint32_t usart) {
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USART_FCR(usart) |= USART_FCR_RXFIFORST;
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}
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/**@}*/
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