Arti Zirk
244fdbc35c
subrepo: subdir: "libopencm3" merged: "f5813a54" upstream: origin: "https://github.com/libopencm3/libopencm3" branch: "master" commit: "f5813a54" git-subrepo: version: "0.4.3" origin: "???" commit: "???"
500 lines
13 KiB
C
500 lines
13 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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/**
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* @defgroup rcc_file RCC
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*
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* @ingroup LM4Fxx
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*
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@author @htmlonly © @endhtmlonly 2012
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Alexandru Gagniuc <mr.nuke.me@gmail.com>
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* \brief <b>libopencm3 LM4F Clock control API</b>
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*
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* The LM$F clock API provides functionaliity for manipulating the system clock,
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* oscillator, and PLL. Functions are provided for fine-grained control of clock
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* control registers, while also providing higher level functionality to easily
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* configure the main system clock source.
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*
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* The following code snippet uses fine-grained mechanisms to configures the
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* chip to run off an external 16MHz crystal, and use the PLL to derive a clock
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* frequency of 80MHz.
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* @code{.c}
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* // A divisor of 5 gives us a clock of 400/5 = 80MHz
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* #define PLLDIV_80MHZ 5
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*
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* // Enable the main oscillator
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* rcc_enable_main_osc();
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*
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* // Make RCC2 override RCC
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* rcc_enable_rcc2();
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*
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* // Set XTAL value to 16MHz
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* rcc_configure_xtal(XTAL_16M);
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* // Set the oscillator source as the main oscillator
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* rcc_set_osc_source(OSCSRC_MOSC);
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* // Enable the PLL
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* rcc_pll_on();
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*
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* // Change the clock divisor
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* rcc_set_pll_divisor(PLLDIV_80MHZ);
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*
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* // We cannot use the PLL as a clock source until it locks
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* rcc_wait_for_pll_ready();
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* // Disable PLL bypass to derive the system clock from the PLL clock
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* rcc_pll_bypass_disable();
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*
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* // Keep track of frequency
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* lm4f_rcc_sysclk_freq = 80E6;
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* @endcode
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*
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* The same can be achieved by a simple call to high-level routines:
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* @code
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* // A divisor of 5 gives us a clock of 400/5 = 80MHz
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* #define PLLDIV_80MHZ 5
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*
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* rcc_sysclk_config(OSCSRC_MOSC, XTAL_16M, PLLDIV_80MHZ);
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* @endcode
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*
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* @{
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*/
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#include <libopencm3/lm4f/rcc.h>
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/**
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* @defgroup rcc_low_level Low-level clock control API
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@ingroup rcc_file
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* @{
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*/
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/**
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* \brief System clock frequency
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*
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* This variable is provided to keep track of the system clock frequency. It
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* should be updated every time the system clock is changed via the fine-grained
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* mechanisms. The initial value is 16MHz, which corresponds to the clock of the
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* internal 16MHz oscillator.
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*
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* High-level routines update the system clock automatically.
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* For read access, it is recommended to access this variable via
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* @code
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* rcc_get_system_clock_frequency();
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* @endcode
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*
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* If write access is desired (i.e. when changing the system clock via the
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* fine-grained mechanisms), then include the following line in your code:
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* @code
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* extern uint32_t lm4f_rcc_sysclk_freq;
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* @endcode
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*/
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uint32_t lm4f_rcc_sysclk_freq = 16000000;
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/**
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* \brief Configure the crystal type connected to the device.
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*
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* Configure the crystal type connected between the OSCO and OSCI pins by
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* writing the appropriate value to the XTAL field in SYSCTL_RCC. The PLL
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* parameters are automatically adjusted in hardware to provide a PLL clock of
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* 400MHz.
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*
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* @param[in] xtal predefined crystal type @see xtal_t
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*/
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void rcc_configure_xtal(enum xtal_t xtal)
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{
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uint32_t reg32;
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reg32 = SYSCTL_RCC;
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reg32 &= ~SYSCTL_RCC_XTAL_MASK;
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reg32 |= (xtal & SYSCTL_RCC_XTAL_MASK);
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SYSCTL_RCC = reg32;
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}
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/**
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* \brief Disable the main oscillator
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*
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* Sets the IOSCDIS bit in SYSCTL_RCC, disabling the main oscillator.
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*/
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void rcc_disable_main_osc(void)
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{
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SYSCTL_RCC |= SYSCTL_RCC_MOSCDIS;
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}
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/**
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* \brief Disable the internal oscillator
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*
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* Sets the IOSCDIS bit in SYSCTL_RCC, disabling the internal oscillator.
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*/
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void rcc_disable_interal_osc(void)
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{
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SYSCTL_RCC |= SYSCTL_RCC_IOSCDIS;
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}
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/**
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* \brief Enable the main oscillator
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*
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* Clears the MOSCDIS bit in SYSCTL_RCC, enabling the main oscillator.
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*/
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void rcc_enable_main_osc(void)
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{
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SYSCTL_RCC &= ~SYSCTL_RCC_MOSCDIS;
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}
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/**
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* \brief Enable the internal oscillator
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*
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* Clears the IOSCDIS bit in SYSCTL_RCC, enabling the internal oscillator.
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*/
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void rcc_enable_interal_osc(void)
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{
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SYSCTL_RCC &= ~SYSCTL_RCC_IOSCDIS;
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}
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/**
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* \brief Enable the use of SYSCTL_RCC2 register for clock control
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*
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* Enables the USERCC2 bit in SYSCTTL_RCC2. Settings in SYSCTL_RCC2 will
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* override settings in SYSCTL_RCC.
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* This function must be called before other calls to manipulate the clock, as
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* libopencm3 uses the SYSCTL_RCC2 register.
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*/
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void rcc_enable_rcc2(void)
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{
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SYSCTL_RCC2 |= SYSCTL_RCC2_USERCC2;
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}
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/**
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* \brief Power down the main PLL
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*
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* Sets the SYSCTL_RCC2_PWRDN2 in SYSCTL_RCC2 to power down the PLL.
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*
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* USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this
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* function.
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*/
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void rcc_pll_off(void)
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{
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SYSCTL_RCC2 |= SYSCTL_RCC2_PWRDN2;
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}
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/**
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* \brief Power up the main PLL
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*
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* Clears the PWRDN2 in SYSCTL_RCC2 to power on the PLL.
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*
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* USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this
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* function.
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*/
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void rcc_pll_on(void)
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{
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SYSCTL_RCC2 &= ~SYSCTL_RCC2_PWRDN2;
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}
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/**
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* \brief Set the oscillator source to be used by the system clock
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*
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* Set the clock source for the system clock.
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*
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* USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this
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* function.
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*/
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void rcc_set_osc_source(enum osc_src src)
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{
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uint32_t reg32;
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reg32 = SYSCTL_RCC2;
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reg32 &= ~SYSCTL_RCC2_OSCSRC2_MASK;
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reg32 |= (src & SYSCTL_RCC2_OSCSRC2_MASK);
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SYSCTL_RCC2 = reg32;
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}
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/**
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* \brief Disable the PLL bypass and use the PLL clock
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*
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* Clear BYPASS2 in SYSCTL_RCC2. The system clock is derived from the PLL
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* clock divided by the divisor specified in SYSDIV2.
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*
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* USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this
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* function.
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*/
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void rcc_pll_bypass_disable(void)
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{
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SYSCTL_RCC2 &= ~SYSCTL_RCC2_BYPASS2;
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}
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/**
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* \brief Enable the PLL bypass and use the oscillator clock
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*
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* Set BYPASS2 in SYSCTL_RCC2. The system clock is derived from the oscillator
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* clock divided by the divisor specified in SYSDIV2.
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*
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* USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this
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* function.
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*/
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void rcc_pll_bypass_enable(void)
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{
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SYSCTL_RCC2 |= SYSCTL_RCC2_BYPASS2;
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}
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/**
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* \brief Set the PLL clock divisor (from 400MHz)
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*
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* Set the binary divisor used to predivide the system clock down for use as the
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* timing reference for the PWM module. The divisor is expected to be a divisor
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* from 400MHz, not 200MHz. The DIV400 is also set.
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*
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* Specifies the divisor that used to generate the system clock from either the
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* PLL output or the oscillator source (depending on the BYPASS2 bit in
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* SYSCTL_RCC2). SYSDIV2 is used for the divisor when both the USESYSDIV bit in
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* SYSCTL_RCC is set.
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*
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* USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this
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* function.
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*
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* @param[in] div clock divisor to apply to the 400MHz PLL clock. It is the
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* caller's responsibility to ensure that the divisor will not create
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* a system clock that is out of spec.
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*/
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void rcc_set_pll_divisor(uint8_t div400)
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{
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uint32_t reg32;
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SYSCTL_RCC |= SYSCTL_RCC_USESYSDIV;
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reg32 = SYSCTL_RCC2;
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reg32 &= ~SYSCTL_RCC2_SYSDIV400_MASK;
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reg32 |= ((div400 - 1) << 22) & SYSCTL_RCC2_SYSDIV400_MASK;
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/* We are expecting a divider from 400MHz */
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reg32 |= SYSCTL_RCC2_DIV400;
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SYSCTL_RCC2 = reg32;
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}
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/**
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* \brief Set the PWM unit clock divisor
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*
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* Set the binary divisor used to predivide the system clock down for use as the
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* timing reference for the PWM module.
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*
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* @param[in] div clock divisor to use @see pwm_clkdiv_t
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*/
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void rcc_set_pwm_divisor(enum pwm_clkdiv div)
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{
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uint32_t reg32;
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reg32 = SYSCTL_RCC;
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reg32 &= ~SYSCTL_RCC_PWMDIV_MASK;
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reg32 |= (div & SYSCTL_RCC_PWMDIV_MASK);
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SYSCTL_RCC = reg32;
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}
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/**
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* \brief Power down the USB PLL
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*
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* Sets the USBPWRDN in SYSCTL_RCC2 to power down the USB PLL.
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*
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* USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this
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* function.
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*/
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void rcc_usb_pll_off(void)
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{
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SYSCTL_RCC2 |= SYSCTL_RCC2_USBPWRDN;
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}
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/**
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* \brief Power up the USB PLL
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*
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* Clears the USBPWRDN in SYSCTL_RCC2 to power on the USB PLL.
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*
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* USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this
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* function.
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*/
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void rcc_usb_pll_on(void)
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{
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SYSCTL_RCC2 &= ~SYSCTL_RCC2_USBPWRDN;
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}
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/**
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* \brief Wait for main PLL to lock
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*
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* Waits until the LOCK bit in SYSCTL_PLLSTAT is set. This guarantees that the
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* PLL is locked, and ready to use.
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*/
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void rcc_wait_for_pll_ready(void)
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{
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while (!(SYSCTL_PLLSTAT & SYSCTL_PLLSTAT_LOCK));
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}
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/**
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* @}
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*/
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/**
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* @defgroup rcc_high_level High-level clock control API
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@ingroup rcc_file
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* @{
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*/
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/**
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* \brief Change the PLL divisor
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*
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* Changes the divisor applied to the 400MHz PLL clock. The PLL must have
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* previously been configured by selecting an appropriate XTAL value, and
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* turning on the PLL. This function does not reconfigure the XTAL value or
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* oscillator source. It only changes the PLL divisor.
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*
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* The PLL is bypassed before modifying the divisor, and the function blocks
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* until the PLL is locked, then the bypass is disabled, before returning.
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*
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* @param [in] pll_div400 The clock divisor to apply to the 400MHz PLL clock.
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*/
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void rcc_change_pll_divisor(uint8_t pll_div400)
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{
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/* Bypass the PLL while its settings are modified */
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rcc_pll_bypass_enable();
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/* Change the clock divisor */
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rcc_set_pll_divisor(pll_div400);
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/* We cannot use the PLL as a clock source until it locks */
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rcc_wait_for_pll_ready();
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/* Disable PLL bypass to derive the system clock from the PLL clock */
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rcc_pll_bypass_disable();
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/* Update the system clock frequency for housekeeping */
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lm4f_rcc_sysclk_freq = (uint32_t)400E6 / pll_div400;
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}
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/**
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* \brief Get the system clock frequency
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*
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* @return System clock frequency in Hz
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*/
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uint32_t rcc_get_system_clock_frequency(void)
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{
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return lm4f_rcc_sysclk_freq;
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}
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/* Get the clock frequency corresponding to a given XTAL value */
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static uint32_t xtal_to_freq(enum xtal_t xtal)
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{
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const uint32_t freqs[] = {
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4000000, /* XTAL_4M */
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4096000, /* XTAL_4M_096 */
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4915200, /* XTAL_4M_9152 */
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5000000, /* ,XTAL_5M */
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5120000, /* XTAL_5M_12 */
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6000000, /* XTAL_6M */
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6144000, /* XTAL_6M_144 */
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7372800, /* XTAL_7M_3728 */
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8000000, /* XTAL_8M */
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8192000, /* XTAL_8M_192 */
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10000000, /* XTAL_10M */
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12000000, /* XTAL_12M */
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12288000, /* XTAL_12M_288 */
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13560000, /* XTAL_13M_56 */
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14318180, /* XTAL_14M_31818 */
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16000000, /* XTAL_16M */
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16384000, /* XTAL_16M_384 */
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18000000, /* XTAL_18M */
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20000000, /* XTAL_20M */
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24000000, /* XTAL_24M */
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25000000, /* XTAL_25M */
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};
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return freqs[xtal - XTAL_4M];
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}
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/**
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* \brief Configure the system clock source
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*
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* Sets up the system clock, including configuring the oscillator source, and
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* PLL to acheve the desired system clock frequency. Where applicable, The LM4F
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* clock API uses the new RCC2 register to configure clock parameters.
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*
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* Enables the main oscillator if the clock source is OSCSRC_MOSC. If the main
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* oscillator was previously enabled, it will not be disabled. If desired, it
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* can be separately disabled by a call to rcc_disable_main_osc().
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*
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* Configures the system clock to run from the 400MHz PLL with a divisor of
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* pll_div400 applied. If pll_div400 is 0, then the PLL is disabled, and the
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* system clock is configured to run off a "raw" clock. If the PLL was
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* previously powered on, it will not be disabled. If desired, it can de powered
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* off by a call to rcc_pll_off().
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*
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* @param [in] osc_src Oscillator from where to derive the system clock.
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* @param [in] xtal Type of crystal connected to the OSCO/OSCI pins
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* @param [in] pll_div400 The clock divisor to apply to the 400MHz PLL clock.
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* If 0, then the PLL is disabled, and the system runs
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* off a "raw" clock.
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*
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* @return System clock frequency in Hz
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*/
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void rcc_sysclk_config(enum osc_src src, enum xtal_t xtal, uint8_t pll_div400)
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{
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/*
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* We could be using the PLL at this point, or we could be running of a
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* raw clock. Either way, it is safer to bypass the PLL now.
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*/
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rcc_pll_bypass_enable();
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/* Enable the main oscillator, if needed */
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if (src == OSCSRC_MOSC) {
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rcc_enable_main_osc();
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}
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/* Make RCC2 override RCC */
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rcc_enable_rcc2();
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/* Set XTAL value to 16MHz */
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rcc_configure_xtal(xtal);
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/* Set the oscillator source */
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rcc_set_osc_source(src);
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if (pll_div400) {
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/* Enable the PLL */
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rcc_pll_on();
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/* Configure the PLL to the divisor we want */
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rcc_change_pll_divisor(pll_div400);
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} else {
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/* We are running off a raw clock */
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switch (src) {
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case OSCSRC_PIOSC:
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lm4f_rcc_sysclk_freq = 16000000;
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break;
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case OSCSRC_PIOSC_D4:
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lm4f_rcc_sysclk_freq = 4000000;
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break;
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case OSCSRC_MOSC:
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lm4f_rcc_sysclk_freq = xtal_to_freq(xtal);
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break;
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case OSCSRC_32K_EXT:
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lm4f_rcc_sysclk_freq = 32768;
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break;
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case OSCSRC_30K_INT: /* Fall through. */
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default:
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/*
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* We either are running off the internal 30KHz
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* oscillator, which is +- 50% imprecise, or we got a
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* bad osc_src parameter.
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*/
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lm4f_rcc_sysclk_freq = 0;
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}
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}
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}
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/**
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* @}
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* @}
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*/
|