95 lines
3.1 KiB
C
95 lines
3.1 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_CM3_ITM_H
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#define LIBOPENCM3_CM3_ITM_H
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/**
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* @defgroup cm_itm Cortex-M Instrumentation Trace Macrocell (ITM)
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* @ingroup CM3_defines
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* @{
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*/
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/* Those defined only on ARMv7 and above */
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#if !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__)
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#error "Instrumentation Trace Macrocell not available in CM0"
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#endif
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/* --- ITM registers ------------------------------------------------------- */
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/* Stimulus Port x (ITM_STIM<sz>(x)) */
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#define ITM_STIM8(n) (MMIO8(ITM_BASE + ((n)*4)))
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#define ITM_STIM16(n) (MMIO16(ITM_BASE + ((n)*4)))
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#define ITM_STIM32(n) (MMIO32(ITM_BASE + ((n)*4)))
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/* Trace Enable ports (ITM_TER[x]) */
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#define ITM_TER (&MMIO32(ITM_BASE + 0xE00))
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/* Trace Privilege (ITM_TPR) */
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#define ITM_TPR MMIO32(ITM_BASE + 0xE40)
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/* Trace Control (ITM_TCR) */
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#define ITM_TCR MMIO32(ITM_BASE + 0xE80)
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/* CoreSight Lock Status Register for this peripheral */
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#define ITM_LSR MMIO32(ITM_BASE + CORESIGHT_LSR_OFFSET)
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/* CoreSight Lock Access Register for this peripheral */
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#define ITM_LAR MMIO32(ITM_BASE + CORESIGHT_LAR_OFFSET)
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/* TODO: PID, CID */
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/* --- ITM_STIM values ----------------------------------------------------- */
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/* Bits 31:0 - Write to port FIFO for forwarding as software event packet */
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/* Bits 31:1 - RAZ */
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#define ITM_STIM_FIFOREADY (1 << 0)
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/* --- ITM_TER values ------------------------------------------------------ */
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/* Bits 31:0 - Stimulus port #N is enabled with STIMENA[N] is set */
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/* --- ITM_TPR values ------------------------------------------------------ */
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/*
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* Bits 31:0 - Bit [N] of PRIVMASK controls stimulus ports 8N to 8N+7
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* 0: User access allowed to stimulus ports
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* 1: Privileged access only to stimulus ports
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*/
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/* --- ITM_TCR values ------------------------------------------------------ */
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/* Bits 31:24 - Reserved */
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#define ITM_TCR_BUSY (1 << 23)
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#define ITM_TCR_TRACE_BUS_ID_MASK (0x3f << 16)
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/* Bits 15:10 - Reserved */
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#define ITM_TCR_TSPRESCALE_NONE (0 << 8)
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#define ITM_TCR_TSPRESCALE_DIV4 (1 << 8)
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#define ITM_TCR_TSPRESCALE_DIV16 (2 << 8)
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#define ITM_TCR_TSPRESCALE_DIV64 (3 << 8)
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#define ITM_TCR_TSPRESCALE_MASK (3 << 8)
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/* Bits 7:5 - Reserved */
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#define ITM_TCR_SWOENA (1 << 4)
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#define ITM_TCR_TXENA (1 << 3)
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#define ITM_TCR_SYNCENA (1 << 2)
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#define ITM_TCR_TSENA (1 << 1)
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#define ITM_TCR_ITMENA (1 << 0)
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/**@}*/
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#endif
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