156 lines
5.5 KiB
C
156 lines
5.5 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
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* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_CM3_SCS_H
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#define LIBOPENCM3_CM3_SCS_H
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/**
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* @defgroup cm_scs Cortex-M System Control Space
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* @ingroup CM3_defines
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* The System Control Space (SCS) is a memory-mapped 4KB address space that
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* provides 32-bit registers for configuration, status reporting and control.
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* The SCS registers divide into the following groups:
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* - system control and identification
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* - the CPUID processor identification space
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* - system configuration and status
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* - fault reporting
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* - a system timer, SysTick
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* - a Nested Vectored Interrupt Controller (NVIC)
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* - a Protected Memory System Architecture (PMSA)
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* - system debug.
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*
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* Most portions of the SCS are covered by their own header files, eg
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* systick.h, dwt.h, scb.h, itm.h, fpb.h
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* @{
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*/
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/** @defgroup cm_scs_registers SCS Registers
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* @ingroup cm_scs
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* @{
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*/
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/**
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* Debug Halting Control and Status Register (DHCSR).
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*
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* Purpose Controls halting debug.
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* Usage constraints: The effect of modifying the C_STEP or C_MASKINTS bit when
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* the system is running with halting debug enabled is UNPREDICTABLE.
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* Halting debug is enabled when C_DEBUGEN is set to 1. The system is running
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* when S_HALT is set to 0.
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* - When C_DEBUGEN is set to 0, the processor ignores the values of all other
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* bits in this register.
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* - For more information about the use of DHCSR see Debug stepping on page
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* C1-824.
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* Configurations Always implemented.
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*/
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#define SCS_DHCSR MMIO32(SCS_BASE + 0xDF0)
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/**
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* Debug Core Register Selector Register (DCRSR).
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*
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* Purpose With the DCRDR, the DCRSR provides debug access to the ARM core
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* registers, special-purpose registers, and Floating-point extension
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* registers. A write to DCRSR specifies the register to transfer, whether the
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* transfer is a read or a write, and starts the transfer.
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* Usage constraints: Only accessible in Debug state.
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* Configurations Always implemented.
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*
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*/
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#define SCS_DCRSR MMIO32(SCS_BASE + 0xDF4)
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/**
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* Debug Core Register Data Register (DCRDR)
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*
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* Purpose With the DCRSR, see Debug Core Register Selector Register, the DCRDR
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* provides debug access to the ARM core registers, special-purpose registers,
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* and Floating-point extension registers. The DCRDR is the data register for
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* these accesses.
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* - Used on its own, the DCRDR provides a message passing resource between an
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* external debugger and a debug agent running on the processor.
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* Note:
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* The architecture does not define any handshaking mechanism for this use of
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* DCRDR.
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* Usage constraints: See Use of DCRSR and DCRDR for constraints that apply to
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* particular transfers using the DCRSR and DCRDR.
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* Configurations Always implemented.
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*
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*/
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#define SCS_DCRDR MMIO32(SCS_BASE + 0xDF8)
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/**
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* Debug Exception and Monitor Control Register (DEMCR).
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*
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* Purpose Manages vector catch behavior and DebugMonitor handling when
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* debugging.
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* Usage constraints:
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* - Bits [23:16] provide DebugMonitor exception control.
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* - Bits [15:0] provide Debug state, halting debug, control.
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* Configurations Always implemented.
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*
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*/
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#define SCS_DEMCR MMIO32(SCS_BASE + 0xDFC)
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/**@}*/
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/* Debug Halting Control and Status Register (DHCSR) */
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#define SCS_DHCSR_DBGKEY 0xA05F0000
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#define SCS_DHCSR_C_DEBUGEN 0x00000001
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#define SCS_DHCSR_C_HALT 0x00000002
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#define SCS_DHCSR_C_STEP 0x00000004
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#define SCS_DHCSR_C_MASKINTS 0x00000008
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#define SCS_DHCSR_C_SNAPSTALL 0x00000020
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#define SCS_DHCSR_S_REGRDY 0x00010000
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#define SCS_DHCSR_S_HALT 0x00020000
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#define SCS_DHCSR_S_SLEEP 0x00040000
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#define SCS_DHCSR_S_LOCKUP 0x00080000
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#define SCS_DHCSR_S_RETIRE_ST 0x01000000
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#define SCS_DHCSR_S_RESET_ST 0x02000000
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/* Debug Core Register Selector Register (DCRSR) */
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#define SCS_DCRSR_REGSEL_MASK 0x0000001F
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#define SCS_DCRSR_REGSEL_XPSR 0x00000010
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#define SCS_DCRSR_REGSEL_MSP 0x00000011
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#define SCS_DCRSR_REGSEL_PSP 0x00000012
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/* Debug Exception and Monitor Control Register (DEMCR) */
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/* Bits 31:25 - Reserved */
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#define SCS_DEMCR_TRCENA (1 << 24)
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/* Bits 23:20 - Reserved */
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#define SCS_DEMCR_MON_REQ (1 << 19)
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#define SCS_DEMCR_MON_STEP (1 << 18)
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#define SCS_DEMCR_VC_MON_PEND (1 << 17)
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#define SCS_DEMCR_VC_MON_EN (1 << 16)
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/* Bits 15:11 - Reserved */
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#define SCS_DEMCR_VC_HARDERR (1 << 10)
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#define SCS_DEMCR_VC_INTERR (1 << 9)
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#define SCS_DEMCR_VC_BUSERR (1 << 8)
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#define SCS_DEMCR_VC_STATERR (1 << 7)
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#define SCS_DEMCR_VC_CHKERR (1 << 6)
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#define SCS_DEMCR_VC_NOCPERR (1 << 5)
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#define SCS_DEMCR_VC_MMERR (1 << 4)
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/* Bits 3:1 - Reserved */
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#define SCS_DEMCR_VC_CORERESET (1 << 0)
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/* CoreSight Lock Status Register for this peripheral */
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#define SCS_DWT_LSR MMIO32(SCS_DWT_BASE + 0xFB4)
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/* CoreSight Lock Access Register for this peripheral */
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#define SCS_DWT_LAR MMIO32(SCS_DWT_BASE + 0xFB0)
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/**@}*/
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#endif
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