371 lines
13 KiB
C
371 lines
13 KiB
C
/** @addtogroup usb_defines
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2015 Kuldeep Singh Dhaka <kuldeepdhaka9@gmail.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/usb/usbd.h>
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/**@{*/
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#define USB_CTRL MMIO32(USB_BASE + 0x000)
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#define USB_STATUS MMIO32(USB_BASE + 0x004)
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#define USB_IF MMIO32(USB_BASE + 0x008)
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#define USB_IFS MMIO32(USB_BASE + 0x00C)
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#define USB_IFC MMIO32(USB_BASE + 0x010)
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#define USB_IEN MMIO32(USB_BASE + 0x014)
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#define USB_ROUTE MMIO32(USB_BASE + 0x018)
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/* USB_CTRL */
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#define USB_CTRL_DMPUAP (1 << 1)
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/* USB_ROUTE */
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#define USB_ROUTE_DMPUPEN (1 << 2)
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#define USB_ROUTE_VBUSENPEN (1 << 1)
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#define USB_ROUTE_PHYPEN (1 << 0)
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/* Core Global Control and Status Registers */
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#define USB_OTG_BASE (USB_BASE + 0x3C000)
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#define USB_GOTGCTL MMIO32(USB_OTG_BASE + 0x000)
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#define USB_GOTGINT MMIO32(USB_OTG_BASE + 0x004)
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#define USB_GAHBCFG MMIO32(USB_OTG_BASE + 0x008)
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#define USB_GUSBCFG MMIO32(USB_OTG_BASE + 0x00C)
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#define USB_GRSTCTL MMIO32(USB_OTG_BASE + 0x010)
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#define USB_GINTSTS MMIO32(USB_OTG_BASE + 0x014)
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#define USB_GINTMSK MMIO32(USB_OTG_BASE + 0x018)
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#define USB_GRXSTSR MMIO32(USB_OTG_BASE + 0x01C)
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#define USB_GRXSTSP MMIO32(USB_OTG_BASE + 0x020)
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#define USB_GRXFSIZ MMIO32(USB_OTG_BASE + 0x024)
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#define USB_GNPTXFSIZ MMIO32(USB_OTG_BASE + 0x028)
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#define USB_GNPTXSTS MMIO32(USB_OTG_BASE + 0x02C)
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#define USB_GDFIFOCFG MMIO32(USB_OTG_BASE + 0x05C)
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#define USB_HPTXFSIZ MMIO32(USB_OTG_BASE + 0x100)
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#define USB_DIEPTXF(x) \
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MMIO32(USB_OTG_BASE + 0x104 + (4 * ((x) - 1)))
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/* Host-mode Control and Status Registers */
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#define USB_HCFG MMIO32(USB_OTG_BASE + 0x400)
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#define USB_HFIR MMIO32(USB_OTG_BASE + 0x404)
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#define USB_HFNUM MMIO32(USB_OTG_BASE + 0x408)
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#define USB_HPTXSTS MMIO32(USB_OTG_BASE + 0x410)
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#define USB_HAINT MMIO32(USB_OTG_BASE + 0x414)
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#define USB_HAINTMSK MMIO32(USB_OTG_BASE + 0x418)
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#define USB_HPRT MMIO32(USB_OTG_BASE + 0x440)
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#define USB_HCx_CHAR(x) \
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MMIO32(USB_OTG_BASE + 0x500 + ((x) * 0x20))
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#define USB_HCx_INT(x) \
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MMIO32(USB_OTG_BASE + 0x508 + ((x) * 0x20))
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#define USB_HCx_INTMSK(x) \
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MMIO32(USB_OTG_BASE + 0x50C + ((x) * 0x20))
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#define USB_HCx_TSIZ(x) \
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MMIO32(USB_OTG_BASE + 0x510 + ((x) * 0x20))
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#define USB_HCx_DMAADDR(x) \
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MMIO32(USB_OTG_BASE + 0x514 + ((x) * 0x20))
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/* Device-mode Control and Status Registers */
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#define USB_DCFG MMIO32(USB_OTG_BASE + 0x800)
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#define USB_DCTL MMIO32(USB_OTG_BASE + 0x804)
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#define USB_DSTS MMIO32(USB_OTG_BASE + 0x808)
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#define USB_DIEPMSK MMIO32(USB_OTG_BASE + 0x810)
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#define USB_DOEPMSK MMIO32(USB_OTG_BASE + 0x814)
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#define USB_DAINT MMIO32(USB_OTG_BASE + 0x818)
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#define USB_DAINTMSK MMIO32(USB_OTG_BASE + 0x81C)
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#define USB_DVBUSDIS MMIO32(USB_OTG_BASE + 0x828)
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#define USB_DVBUSPULSE MMIO32(USB_OTG_BASE + 0x82C)
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#define USB_DIEPEMPMSK MMIO32(USB_OTG_BASE + 0x834)
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#define USB_DIEPx_CTL(x) \
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MMIO32(USB_OTG_BASE + 0x900 + ((x) * 0x20))
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#define USB_DIEPx_INT(x) \
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MMIO32(USB_OTG_BASE + 0x908 + ((x) * 0x20))
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#define USB_DIEPx_TSIZ(x) \
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MMIO32(USB_OTG_BASE + 0x910 + ((x) * 0x20))
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#define USB_DIEP0CTL USB_DIEPx_CTL(0)
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#define USB_DIEP0TSIZ USB_DIEPx_TSIZ(0)
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#define USB_DIEP0INT USB_DIEPx_INT(0)
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#define USB_DOEPx_CTL(x) \
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MMIO32(USB_OTG_BASE + 0xB00 + ((x) * 0x20))
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#define USB_DOEPx_INT(x) \
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MMIO32(USB_OTG_BASE + 0xB08 + ((x) * 0x20))
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#define USB_DOEPx_TSIZ(x) \
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MMIO32(USB_OTG_BASE + 0xB10 + ((x) * 0x20))
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#define USB_DOEP0CTL USB_DOEPx_CTL(0)
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#define USB_DOEP0TSIZ USB_DOEPx_TSIZ(0)
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#define USB_DOEP0INT USB_DOEPx_INT(0)
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/* Power and clock gating control and status register */
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#define USB_PCGCCTL MMIO32(USB_OTG_BASE + 0xE00)
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/* Data FIFO */
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#define USB_FIFOxD(x) \
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(&MMIO32(USB_OTG_BASE + (((x) + 1) << 12)))
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/* Global CSRs */
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/* USB control registers (OTG_HS_GOTGCTL) */
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#define USB_GOTGCTL_BSVLD (1 << 19)
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#define USB_GOTGCTL_ASVLD (1 << 18)
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#define USB_GOTGCTL_DBCT (1 << 17)
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#define USB_GOTGCTL_CIDSTS (1 << 16)
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#define USB_GOTGCTL_DHNPEN (1 << 11)
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#define USB_GOTGCTL_HSHNPEN (1 << 10)
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#define USB_GOTGCTL_HNPRQ (1 << 9)
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#define USB_GOTGCTL_HNGSCS (1 << 8)
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#define USB_GOTGCTL_SRQ (1 << 1)
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#define USB_GOTGCTL_SRQSCS (1 << 0)
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/* AHB configuration register (USB_GAHBCFG) */
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#define USB_GAHBCFG_GLBLINTRMSK 0x0001
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#define USB_GAHBCFG_TXFELVL 0x0080
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#define USB_GAHBCFG_PTXFELVL 0x0100
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/* USB configuration register (USB_GUSBCFG) */
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#define USB_GUSBCFG_TOCAL 0x00000003
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#define USB_GUSBCFG_SRPCAP 0x00000100
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#define USB_GUSBCFG_HNPCAP 0x00000200
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#define USB_GUSBCFG_TRDT_MASK (0xf << 10)
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#define USB_GUSBCFG_TRDT_16BIT (0x5 << 10)
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#define USB_GUSBCFG_TRDT_8BIT (0x9 << 10)
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#define USB_GUSBCFG_NPTXRWEN 0x00004000
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#define USB_GUSBCFG_FHMOD 0x20000000
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#define USB_GUSBCFG_FDMOD 0x40000000
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#define USB_GUSBCFG_CTXPKT 0x80000000
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#define USB_GUSBCFG_PHYSEL (1 << 7)
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/* reset register (USB_GRSTCTL) */
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#define USB_GRSTCTL_AHBIDL (1 << 31)
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/* Bits 30:11 - Reserved */
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#define USB_GRSTCTL_TXFNUM_MASK (0x1f << 6)
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#define USB_GRSTCTL_TXFFLSH (1 << 5)
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#define USB_GRSTCTL_RXFFLSH (1 << 4)
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/* Bit 3 - Reserved */
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#define USB_GRSTCTL_FCRST (1 << 2)
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#define USB_GRSTCTL_HSRST (1 << 1)
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#define USB_GRSTCTL_CSRST (1 << 0)
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/* interrupt status register (USB_GINTSTS) */
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#define USB_GINTSTS_WKUPINT (1 << 31)
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#define USB_GINTSTS_SRQINT (1 << 30)
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#define USB_GINTSTS_DISCINT (1 << 29)
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#define USB_GINTSTS_CIDSCHG (1 << 28)
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/* Bit 27 - Reserved */
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#define USB_GINTSTS_PTXFE (1 << 26)
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#define USB_GINTSTS_HCINT (1 << 25)
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#define USB_GINTSTS_HPRTINT (1 << 24)
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/* Bits 23:22 - Reserved */
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#define USB_GINTSTS_IPXFR (1 << 21)
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#define USB_GINTSTS_INCOMPISOOUT (1 << 21)
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#define USB_GINTSTS_IISOIXFR (1 << 20)
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#define USB_GINTSTS_OEPINT (1 << 19)
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#define USB_GINTSTS_IEPINT (1 << 18)
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/* Bits 17:16 - Reserved */
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#define USB_GINTSTS_EOPF (1 << 15)
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#define USB_GINTSTS_ISOODRP (1 << 14)
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#define USB_GINTSTS_ENUMDNE (1 << 13)
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#define USB_GINTSTS_USBRST (1 << 12)
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#define USB_GINTSTS_USBSUSP (1 << 11)
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#define USB_GINTSTS_ESUSP (1 << 10)
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/* Bits 9:8 - Reserved */
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#define USB_GINTSTS_GONAKEFF (1 << 7)
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#define USB_GINTSTS_GINAKEFF (1 << 6)
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#define USB_GINTSTS_NPTXFE (1 << 5)
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#define USB_GINTSTS_RXFLVL (1 << 4)
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#define USB_GINTSTS_SOF (1 << 3)
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#define USB_GINTSTS_OTGINT (1 << 2)
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#define USB_GINTSTS_MMIS (1 << 1)
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#define USB_GINTSTS_CMOD (1 << 0)
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/* interrupt mask register (USB_GINTMSK) */
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#define USB_GINTMSK_MMISM 0x00000002
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#define USB_GINTMSK_OTGINT 0x00000004
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#define USB_GINTMSK_SOFM 0x00000008
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#define USB_GINTMSK_RXFLVLM 0x00000010
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#define USB_GINTMSK_NPTXFEM 0x00000020
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#define USB_GINTMSK_GINAKEFFM 0x00000040
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#define USB_GINTMSK_GONAKEFFM 0x00000080
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#define USB_GINTMSK_ESUSPM 0x00000400
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#define USB_GINTMSK_USBSUSPM 0x00000800
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#define USB_GINTMSK_USBRST 0x00001000
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#define USB_GINTMSK_ENUMDNEM 0x00002000
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#define USB_GINTMSK_ISOODRPM 0x00004000
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#define USB_GINTMSK_EOPFM 0x00008000
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#define USB_GINTMSK_EPMISM 0x00020000
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#define USB_GINTMSK_IEPINT 0x00040000
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#define USB_GINTMSK_OEPINT 0x00080000
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#define USB_GINTMSK_IISOIXFRM 0x00100000
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#define USB_GINTMSK_IISOOXFRM 0x00200000
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#define USB_GINTMSK_IPXFRM 0x00200000
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#define USB_GINTMSK_PRTIM 0x01000000
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#define USB_GINTMSK_HCIM 0x02000000
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#define USB_GINTMSK_PTXFEM 0x04000000
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#define USB_GINTMSK_CIDSCHGM 0x10000000
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#define USB_GINTMSK_DISCINT 0x20000000
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#define USB_GINTMSK_SRQIM 0x40000000
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#define USB_GINTMSK_WUIM 0x80000000
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/* Receive Status Pop Register (USB_GRXSTSP) */
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/* Bits 31:25 - Reserved */
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#define USB_GRXSTSP_FRMNUM_MASK (0xf << 21)
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#define USB_GRXSTSP_PKTSTS_MASK (0xf << 17)
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#define USB_GRXSTSP_PKTSTS_GOUTNAK (0x1 << 17)
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#define USB_GRXSTSP_PKTSTS_OUT (0x2 << 17)
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#define USB_GRXSTSP_PKTSTS_OUT_COMP (0x3 << 17)
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#define USB_GRXSTSP_PKTSTS_SETUP_COMP (0x4 << 17)
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#define USB_GRXSTSP_PKTSTS_SETUP (0x6 << 17)
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#define USB_GRXSTSP_DPID_MASK (0x3 << 15)
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#define USB_GRXSTSP_DPID_DATA0 (0x0 << 15)
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#define USB_GRXSTSP_DPID_DATA1 (0x2 << 15)
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#define USB_GRXSTSP_DPID_DATA2 (0x1 << 15)
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#define USB_GRXSTSP_DPID_MDATA (0x3 << 15)
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#define USB_GRXSTSP_BCNT_MASK (0x7ff << 4)
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#define USB_GRXSTSP_EPNUM_MASK (0xf << 0)
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/* general core configuration register (USB_GCCFG) */
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/* Bits 31:22 - Reserved */
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#define USB_GCCFG_NOVBUSSENS (1 << 21)
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#define USB_GCCFG_SOFOUTEN (1 << 20)
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#define USB_GCCFG_VBUSBSEN (1 << 19)
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#define USB_GCCFG_VBUSASEN (1 << 18)
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/* Bit 17 - Reserved */
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#define USB_GCCFG_PWRDWN (1 << 16)
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/* Bits 15:0 - Reserved */
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/* Device-mode CSRs */
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/* device control register (USB_DCTL) */
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/* Bits 31:12 - Reserved */
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#define USB_DCTL_POPRGDNE (1 << 11)
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#define USB_DCTL_CGONAK (1 << 10)
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#define USB_DCTL_SGONAK (1 << 9)
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#define USB_DCTL_SGINAK (1 << 8)
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#define USB_DCTL_TCTL_MASK (7 << 4)
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#define USB_DCTL_GONSTS (1 << 3)
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#define USB_DCTL_GINSTS (1 << 2)
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#define USB_DCTL_SDIS (1 << 1)
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#define USB_DCTL_RWUSIG (1 << 0)
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/* device configuration register (USB_DCFG) */
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#define USB_DCFG_DSPD 0x0003
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#define USB_DCFG_NZLSOHSK 0x0004
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#define USB_DCFG_DAD 0x07F0
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#define USB_DCFG_PFIVL 0x1800
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/* Device IN Endpoint Common Interrupt Mask Register (USB_DIEPMSK) */
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/* Bits 31:10 - Reserved */
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#define USB_DIEPMSK_BIM (1 << 9)
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#define USB_DIEPMSK_TXFURM (1 << 8)
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/* Bit 7 - Reserved */
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#define USB_DIEPMSK_INEPNEM (1 << 6)
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#define USB_DIEPMSK_INEPNMM (1 << 5)
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#define USB_DIEPMSK_ITTXFEMSK (1 << 4)
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#define USB_DIEPMSK_TOM (1 << 3)
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/* Bit 2 - Reserved */
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#define USB_DIEPMSK_EPDM (1 << 1)
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#define USB_DIEPMSK_XFRCM (1 << 0)
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/* Device OUT Endpoint Common Interrupt Mask Register (USB_DOEPMSK) */
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/* Bits 31:10 - Reserved */
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#define USB_DOEPMSK_BOIM (1 << 9)
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#define USB_DOEPMSK_OPEM (1 << 8)
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/* Bit 7 - Reserved */
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#define USB_DOEPMSK_B2BSTUP (1 << 6)
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/* Bit 5 - Reserved */
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#define USB_DOEPMSK_OTEPDM (1 << 4)
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#define USB_DOEPMSK_STUPM (1 << 3)
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/* Bit 2 - Reserved */
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#define USB_DOEPMSK_EPDM (1 << 1)
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#define USB_DOEPMSK_XFRCM (1 << 0)
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/* Device Control IN Endpoint 0 Control Register (USB_DIEP0CTL) */
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#define USB_DIEP0CTL_EPENA (1 << 31)
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#define USB_DIEP0CTL_EPDIS (1 << 30)
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/* Bits 29:28 - Reserved */
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#define USB_DIEP0CTL_SD0PID (1 << 28)
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#define USB_DIEP0CTL_SNAK (1 << 27)
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#define USB_DIEP0CTL_CNAK (1 << 26)
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#define USB_DIEP0CTL_TXFNUM_MASK (0xf << 22)
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#define USB_DIEP0CTL_STALL (1 << 21)
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/* Bit 20 - Reserved */
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#define USB_DIEP0CTL_EPTYP_MASK (0x3 << 18)
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#define USB_DIEP0CTL_NAKSTS (1 << 17)
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/* Bit 16 - Reserved */
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#define USB_DIEP0CTL_USBAEP (1 << 15)
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/* Bits 14:2 - Reserved */
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#define USB_DIEP0CTL_MPSIZ_MASK (0x3 << 0)
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#define USB_DIEP0CTL_MPSIZ_64 (0x0 << 0)
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#define USB_DIEP0CTL_MPSIZ_32 (0x1 << 0)
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#define USB_DIEP0CTL_MPSIZ_16 (0x2 << 0)
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#define USB_DIEP0CTL_MPSIZ_8 (0x3 << 0)
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/* Device Control OUT Endpoint 0 Control Register (USB_DOEP0CTL) */
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#define USB_DOEP0CTL_EPENA (1 << 31)
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#define USB_DOEP0CTL_EPDIS (1 << 30)
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/* Bits 29:28 - Reserved */
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#define USB_DOEP0CTL_SD0PID (1 << 28)
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#define USB_DOEP0CTL_SNAK (1 << 27)
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#define USB_DOEP0CTL_CNAK (1 << 26)
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/* Bits 25:22 - Reserved */
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#define USB_DOEP0CTL_STALL (1 << 21)
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#define USB_DOEP0CTL_SNPM (1 << 20)
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#define USB_DOEP0CTL_EPTYP_MASK (0x3 << 18)
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#define USB_DOEP0CTL_NAKSTS (1 << 17)
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/* Bit 16 - Reserved */
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#define USB_DOEP0CTL_USBAEP (1 << 15)
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/* Bits 14:2 - Reserved */
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#define USB_DOEP0CTL_MPSIZ_MASK (0x3 << 0)
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#define USB_DOEP0CTL_MPSIZ_64 (0x0 << 0)
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#define USB_DOEP0CTL_MPSIZ_32 (0x1 << 0)
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#define USB_DOEP0CTL_MPSIZ_16 (0x2 << 0)
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#define USB_DOEP0CTL_MPSIZ_8 (0x3 << 0)
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/* Device IN Endpoint Interrupt Register (USB_DIEPINTx) */
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/* Bits 31:8 - Reserved */
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#define USB_DIEP_INT_TXFE (1 << 7)
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#define USB_DIEP_INT_INEPNE (1 << 6)
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/* Bit 5 - Reserved */
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#define USB_DIEP_INT_ITTXFE (1 << 4)
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#define USB_DIEP_INT_TOC (1 << 3)
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/* Bit 2 - Reserved */
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#define USB_DIEP_INT_EPDISD (1 << 1)
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#define USB_DIEP_INT_XFRC (1 << 0)
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/* Device IN Endpoint Interrupt Register (USB_DOEPINTx) */
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/* Bits 31:7 - Reserved */
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#define USB_DOEP_INT_B2BSTUP (1 << 6)
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/* Bit 5 - Reserved */
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#define USB_DOEP_INT_OTEPDIS (1 << 4)
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#define USB_DOEP_INT_SETUP (1 << 3)
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/* Bit 2 - Reserved */
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#define USB_DOEP_INT_EPDISD (1 << 1)
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#define USB_DOEP_INT_XFRC (1 << 0)
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/* Device OUT Endpoint 0 Transfer Size Register (USB_DOEP0TSIZ) */
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/* Bit 31 - Reserved */
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#define USB_DIEP0TSIZ_STUPCNT_1 (0x1 << 29)
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#define USB_DIEP0TSIZ_STUPCNT_2 (0x2 << 29)
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#define USB_DIEP0TSIZ_STUPCNT_3 (0x3 << 29)
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#define USB_DIEP0TSIZ_STUPCNT_MASK (0x3 << 29)
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/* Bits 28:20 - Reserved */
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#define USB_DIEP0TSIZ_PKTCNT (1 << 19)
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/* Bits 18:7 - Reserved */
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#define USB_DIEP0TSIZ_XFRSIZ_MASK (0x7f << 0)
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/**@}*/ |