Arti Zirk
244fdbc35c
subrepo: subdir: "libopencm3" merged: "f5813a54" upstream: origin: "https://github.com/libopencm3/libopencm3" branch: "master" commit: "f5813a54" git-subrepo: version: "0.4.3" origin: "???" commit: "???"
217 lines
6.6 KiB
C
217 lines
6.6 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
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* Copyright (C) 2012 Fergus Noble <fergusnoble@gmail.com>
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* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/** @defgroup CM3_nvic_file NVIC
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*
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* @ingroup CM3_files
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*
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* @brief <b>libopencm3 Cortex Nested Vectored Interrupt Controller</b>
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*
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* @version 1.0.0
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*
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* @author @htmlonly © @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
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* @author @htmlonly © @endhtmlonly 2012 Fergus Noble
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* <fergusnoble@gmail.com>
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*
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* @date 18 August 2012
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*
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* Cortex processors provide 14 cortex-defined interrupts (NMI, usage faults,
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* systicks etc.) and varying numbers of implementation defined interrupts
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* (typically peripherial interrupts and DMA).
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*
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* @see Cortex-M3 Devices Generic User Guide
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* @see STM32F10xxx Cortex-M3 programming manual
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/**@{*/
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#include <libopencm3/cm3/nvic.h>
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#include <libopencm3/cm3/scb.h>
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/*---------------------------------------------------------------------------*/
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/** @brief NVIC Enable Interrupt
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*
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* Enables a user interrupt.
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*
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* @param[in] irqn Unsigned int8. Interrupt number @ref CM3_nvic_defines_irqs
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*/
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void nvic_enable_irq(uint8_t irqn)
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{
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NVIC_ISER(irqn / 32) = (1 << (irqn % 32));
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}
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/*---------------------------------------------------------------------------*/
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/** @brief NVIC Disable Interrupt
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*
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* Disables a user interrupt.
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*
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* @param[in] irqn Unsigned int8. Interrupt number @ref CM3_nvic_defines_irqs
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*/
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void nvic_disable_irq(uint8_t irqn)
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{
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NVIC_ICER(irqn / 32) = (1 << (irqn % 32));
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}
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/*---------------------------------------------------------------------------*/
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/** @brief NVIC Return Pending Interrupt
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*
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* True if the interrupt has occurred and is waiting for service.
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*
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* @param[in] irqn Unsigned int8. Interrupt number @ref CM3_nvic_defines_irqs
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* @return Boolean. Interrupt pending.
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*/
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uint8_t nvic_get_pending_irq(uint8_t irqn)
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{
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return NVIC_ISPR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief NVIC Set Pending Interrupt
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*
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* Force a user interrupt to a pending state. This has no effect if the
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* interrupt is already pending.
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*
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* @param[in] irqn Unsigned int8. Interrupt number @ref CM3_nvic_defines_irqs
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*/
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void nvic_set_pending_irq(uint8_t irqn)
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{
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NVIC_ISPR(irqn / 32) = (1 << (irqn % 32));
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}
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/*---------------------------------------------------------------------------*/
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/** @brief NVIC Clear Pending Interrupt
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*
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* Force remove a user interrupt from a pending state. This has no effect if
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* the interrupt is actively being serviced.
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*
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* @param[in] irqn Unsigned int8. Interrupt number @ref CM3_nvic_defines_irqs
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*/
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void nvic_clear_pending_irq(uint8_t irqn)
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{
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NVIC_ICPR(irqn / 32) = (1 << (irqn % 32));
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}
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/*---------------------------------------------------------------------------*/
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/** @brief NVIC Return Enabled Interrupt
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*
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* @param[in] irqn Unsigned int8. Interrupt number @ref CM3_nvic_defines_irqs
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* @return Boolean. Interrupt enabled.
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*/
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uint8_t nvic_get_irq_enabled(uint8_t irqn)
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{
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return NVIC_ISER(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0;
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}
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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/** @brief NVIC Set Interrupt Priority
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*
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* There are 16 priority levels only, given by the upper four bits of the
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* priority byte, as required by ARM standards. The priority levels are
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* interpreted according to the pre-emptive priority grouping set in the
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* SCB Application Interrupt and Reset Control Register (SCB_AIRCR), as done
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* in @ref scb_set_priority_grouping,
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* @param[in] irqn Interrupt number @ref CM3_nvic_defines_irqs
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* @param[in] priority Interrupt priority (0 ... 255 in steps of 16)
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*/
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#else
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/** NVIC Set Interrupt Priority.
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*
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* There are 4 priority levels only, given by the upper two bits of the
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* priority byte, as required by ARM standards. No grouping available.
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*
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* @param[in] irqn Interrupt number @ref CM3_nvic_defines_irqs
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* @param[in] priority Interrupt priority (0 ... 255 in steps of 16)
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*/
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#endif
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void nvic_set_priority(uint8_t irqn, uint8_t priority)
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{
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/* code from lpc43xx/nvic.c -- this is quite a hack and alludes to the
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* negative interrupt numbers assigned to the system interrupts. better
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* handling would mean signed integers. */
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if (irqn >= NVIC_IRQ_COUNT) {
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/* Cortex-M system interrupts */
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#if defined(__ARM_ARCH_6M__)
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/* ARM6M supports only 32bit word access to SHPR registers */
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irqn = (irqn & 0xF) - 4;
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uint8_t shift = (irqn & 0x3) << 3;
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uint8_t reg = irqn >> 2;
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SCB_SHPR32(reg) = ((SCB_SHPR32(reg) & ~(0xFFUL << shift)) |
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((uint32_t) priority) << shift);
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#else
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SCB_SHPR((irqn & 0xF) - 4) = priority;
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#endif
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} else {
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/* Device specific interrupts */
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#if defined(__ARM_ARCH_6M__)
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/* ARM6M supports only 32bit word access to IPR registers */
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uint8_t shift = (irqn & 0x3) << 3;
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uint8_t reg = irqn >> 2;
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NVIC_IPR32(reg) = ((NVIC_IPR32(reg) & ~(0xFFUL << shift)) |
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((uint32_t) priority) << shift);
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#else
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NVIC_IPR(irqn) = priority;
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#endif
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}
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}
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/* Those are defined only on CM3 or CM4 */
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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/*---------------------------------------------------------------------------*/
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/** @brief NVIC Return Active Interrupt
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*
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* Interrupt has occurred and is currently being serviced.
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*
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* @param[in] irqn Unsigned int8. Interrupt number @ref CM3_nvic_defines_irqs
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* @return Boolean. Interrupt active.
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*/
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uint8_t nvic_get_active_irq(uint8_t irqn)
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{
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return NVIC_IABR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief NVIC Software Trigger Interrupt
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*
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* Generate an interrupt from software. This has no effect for unprivileged
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* access unless the privilege level has been elevated through the System
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* Control Registers.
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*
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* @param[in] irqn Unsigned int16. Interrupt number (0 ... 239)
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*/
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void nvic_generate_software_interrupt(uint16_t irqn)
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{
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if (irqn <= 239) {
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NVIC_STIR |= irqn;
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}
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}
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#endif
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/**@}*/
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