Arti Zirk
244fdbc35c
subrepo: subdir: "libopencm3" merged: "f5813a54" upstream: origin: "https://github.com/libopencm3/libopencm3" branch: "master" commit: "f5813a54" git-subrepo: version: "0.4.3" origin: "???" commit: "???"
452 lines
16 KiB
C
452 lines
16 KiB
C
/** @defgroup dma_file DMA peripheral API
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@ingroup peripheral_apis
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@brief DMA library for the multi channel controller found in F0/1/3 & L/G parts.
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@author @htmlonly © @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
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This library supports the DMA Control System in the STM32 series of ARM Cortex
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Microcontrollers by ST Microelectronics.
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Up to two DMA controllers are supported. 12 DMA channels are allocated 7 to
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the first DMA controller and 5 to the second. Each channel is connected to
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between 3 and 6 hardware peripheral DMA signals in a logical OR arrangement.
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DMA transfers can be configured to occur between peripheral and memory in
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any combination including memory to memory. Circular mode transfers are
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also supported in transfers involving a peripheral. An arbiter is provided
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to resolve priority DMA requests. Transfers can be made with 8, 16 or 32 bit
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words.
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#include <libopencm3/stm32/dma.h>
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Reset
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The channel is disabled and configuration registers are cleared.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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*/
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void dma_channel_reset(uint32_t dma, uint8_t channel)
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{
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/* Disable channel and reset config bits. */
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DMA_CCR(dma, channel) = 0;
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/* Reset data transfer number. */
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DMA_CNDTR(dma, channel) = 0;
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/* Reset peripheral address. */
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DMA_CPAR(dma, channel) = 0;
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/* Reset memory address. */
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DMA_CMAR(dma, channel) = 0;
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/* Reset interrupt flags. */
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DMA_IFCR(dma) |= DMA_IFCR_CIF(channel);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Clear Interrupt Flag
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The interrupt flag for the channel is cleared. More than one interrupt for the
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same channel may be cleared by using the logical OR of the interrupt flags.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: @ref dma_ch
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@param[in] interrupts unsigned int32. Logical OR of interrupt numbers: @ref
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dma_if_offset
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*/
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void dma_clear_interrupt_flags(uint32_t dma, uint8_t channel,
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uint32_t interrupts)
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{
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/* Get offset to interrupt flag location in channel field */
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uint32_t flags = (interrupts << DMA_FLAG_OFFSET(channel));
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DMA_IFCR(dma) = flags;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Read Interrupt Flag
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The interrupt flag for the channel is returned.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: @ref dma_ch
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@param[in] interrupt unsigned int32. Interrupt number: @ref dma_if_offset
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@returns bool interrupt flag is set.
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*/
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bool dma_get_interrupt_flag(uint32_t dma, uint8_t channel, uint32_t interrupt)
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{
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/* get offset to interrupt flag location in channel field. */
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uint32_t flag = (interrupt << DMA_FLAG_OFFSET(channel));
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return ((DMA_ISR(dma) & flag) > 0);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Enable Memory to Memory Transfers
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Memory to memory transfers do not require a trigger to activate each transfer.
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Transfers begin immediately the channel has been enabled, and proceed without
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intervention.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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*/
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void dma_enable_mem2mem_mode(uint32_t dma, uint8_t channel)
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{
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DMA_CCR(dma, channel) |= DMA_CCR_MEM2MEM;
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DMA_CCR(dma, channel) &= ~DMA_CCR_CIRC;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Set Priority
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Channel Priority has four levels: low to very high. This has precedence over the
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hardware priority.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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@param[in] prio unsigned int32. Priority level @ref dma_ch_pri.
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*/
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void dma_set_priority(uint32_t dma, uint8_t channel, uint32_t prio)
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{
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DMA_CCR(dma, channel) &= ~(DMA_CCR_PL_MASK);
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DMA_CCR(dma, channel) |= prio;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Set Memory Word Width
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Set the memory word width 8 bits, 16 bits, or 32 bits. Refer to datasheet for
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alignment information if the source and destination widths do not match.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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@param[in] mem_size unsigned int32. Memory word width @ref dma_ch_memwidth.
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*/
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void dma_set_memory_size(uint32_t dma, uint8_t channel, uint32_t mem_size)
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{
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DMA_CCR(dma, channel) &= ~(DMA_CCR_MSIZE_MASK);
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DMA_CCR(dma, channel) |= mem_size;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Set Peripheral Word Width
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Set the peripheral word width 8 bits, 16 bits, or 32 bits. Refer to datasheet
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for alignment information if the source and destination widths do not match, or
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if the peripheral does not support byte or half-word writes.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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@param[in] peripheral_size unsigned int32. Peripheral word width @ref
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dma_ch_perwidth.
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*/
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void dma_set_peripheral_size(uint32_t dma, uint8_t channel,
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uint32_t peripheral_size)
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{
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DMA_CCR(dma, channel) &= ~(DMA_CCR_PSIZE_MASK);
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DMA_CCR(dma, channel) |= peripheral_size;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Enable Memory Increment after Transfer
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Following each transfer the current memory address is incremented by
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1, 2 or 4 depending on the data size set in @ref dma_set_memory_size. The
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value held by the base memory address register is unchanged.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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*/
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void dma_enable_memory_increment_mode(uint32_t dma, uint8_t channel)
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{
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DMA_CCR(dma, channel) |= DMA_CCR_MINC;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Disable Memory Increment after Transfer
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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*/
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void dma_disable_memory_increment_mode(uint32_t dma, uint8_t channel)
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{
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DMA_CCR(dma, channel) &= ~DMA_CCR_MINC;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Enable Peripheral Increment after Transfer
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Following each transfer the current peripheral address is incremented by
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1, 2 or 4 depending on the data size set in @ref dma_set_peripheral_size. The
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value held by the base peripheral address register is unchanged.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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*/
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void dma_enable_peripheral_increment_mode(uint32_t dma, uint8_t channel)
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{
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DMA_CCR(dma, channel) |= DMA_CCR_PINC;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Disable Peripheral Increment after Transfer
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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*/
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void dma_disable_peripheral_increment_mode(uint32_t dma, uint8_t channel)
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{
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DMA_CCR(dma, channel) &= ~DMA_CCR_PINC;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Enable Memory Circular Mode
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After the number of bytes/words to be transferred has been completed, the
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original transfer block size, memory and peripheral base addresses are
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reloaded and the process repeats.
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@note This cannot be used with memory to memory mode, which is explicitly
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disabled here.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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*/
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void dma_enable_circular_mode(uint32_t dma, uint8_t channel)
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{
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DMA_CCR(dma, channel) |= DMA_CCR_CIRC;
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DMA_CCR(dma, channel) &= ~DMA_CCR_MEM2MEM;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Enable Transfers from a Peripheral
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The data direction is set to read from a peripheral.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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*/
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void dma_set_read_from_peripheral(uint32_t dma, uint8_t channel)
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{
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DMA_CCR(dma, channel) &= ~DMA_CCR_DIR;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Enable Transfers from Memory
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The data direction is set to read from memory.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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*/
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void dma_set_read_from_memory(uint32_t dma, uint8_t channel)
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{
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DMA_CCR(dma, channel) |= DMA_CCR_DIR;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Enable Interrupt on Transfer Error
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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*/
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void dma_enable_transfer_error_interrupt(uint32_t dma, uint8_t channel)
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{
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DMA_CCR(dma, channel) |= DMA_CCR_TEIE;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Disable Interrupt on Transfer Error
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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*/
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void dma_disable_transfer_error_interrupt(uint32_t dma, uint8_t channel)
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{
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DMA_CCR(dma, channel) &= ~DMA_CCR_TEIE;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Enable Interrupt on Transfer Half Complete
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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*/
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void dma_enable_half_transfer_interrupt(uint32_t dma, uint8_t channel)
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{
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DMA_CCR(dma, channel) |= DMA_CCR_HTIE;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Disable Interrupt on Transfer Half Complete
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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*/
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void dma_disable_half_transfer_interrupt(uint32_t dma, uint8_t channel)
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{
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DMA_CCR(dma, channel) &= ~DMA_CCR_HTIE;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Enable Interrupt on Transfer Complete
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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*/
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void dma_enable_transfer_complete_interrupt(uint32_t dma, uint8_t channel)
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{
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DMA_CCR(dma, channel) |= DMA_CCR_TCIE;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Disable Interrupt on Transfer Complete
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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*/
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void dma_disable_transfer_complete_interrupt(uint32_t dma, uint8_t channel)
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{
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DMA_CCR(dma, channel) &= ~DMA_CCR_TCIE;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Enable
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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*/
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void dma_enable_channel(uint32_t dma, uint8_t channel)
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{
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DMA_CCR(dma, channel) |= DMA_CCR_EN;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Disable
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@note The DMA channel registers retain their values when the channel is
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disabled.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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*/
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void dma_disable_channel(uint32_t dma, uint8_t channel)
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{
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DMA_CCR(dma, channel) &= ~DMA_CCR_EN;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Set the Peripheral Address
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Set the address of the peripheral register to or from which data is to be
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transferred. Refer to the documentation for the specific peripheral.
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@note The DMA channel must be disabled before setting this address. This
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function has no effect if the channel is enabled.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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@param[in] address unsigned int32. Peripheral Address.
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*/
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void dma_set_peripheral_address(uint32_t dma, uint8_t channel, uint32_t address)
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{
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if (!(DMA_CCR(dma, channel) & DMA_CCR_EN)) {
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DMA_CPAR(dma, channel) = (uint32_t) address;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Set the Base Memory Address
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@note The DMA channel must be disabled before setting this address. This
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function has no effect if the channel is enabled.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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@param[in] address unsigned int32. Memory Initial Address.
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*/
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void dma_set_memory_address(uint32_t dma, uint8_t channel, uint32_t address)
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{
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if (!(DMA_CCR(dma, channel) & DMA_CCR_EN)) {
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DMA_CMAR(dma, channel) = (uint32_t) address;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Get the Transfer Block Size
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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@returns unsigned int16. Number of remaining data words to transfer (65535
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maximum).
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*/
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uint16_t dma_get_number_of_data(uint32_t dma, uint8_t channel)
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{
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return DMA_CNDTR(dma, channel);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief DMA Channel Set the Transfer Block Size
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@note The DMA channel must be disabled before setting this count value. The
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count is not changed if the channel is enabled.
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@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
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@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
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@param[in] number unsigned int16. Number of data words to transfer (65535
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maximum).
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*/
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void dma_set_number_of_data(uint32_t dma, uint8_t channel, uint16_t number)
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{
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DMA_CNDTR(dma, channel) = number;
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}
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/**@}*/
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