Arti Zirk
244fdbc35c
subrepo: subdir: "libopencm3" merged: "f5813a54" upstream: origin: "https://github.com/libopencm3/libopencm3" branch: "master" commit: "f5813a54" git-subrepo: version: "0.4.3" origin: "???" commit: "???"
575 lines
14 KiB
C
575 lines
14 KiB
C
/** @defgroup rcc_file RCC peripheral API
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*
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* @ingroup peripheral_apis
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* This library supports the Reset and Clock Control System in the STM32 series
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* of ARM Cortex Microcontrollers by ST Microelectronics.
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*
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* LGPL License Terms @ref lgpl_license
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*/
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#include <libopencm3/cm3/assert.h>
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#include <libopencm3/stm32/rcc.h>
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#include <libopencm3/stm32/pwr.h>
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#include <libopencm3/stm32/flash.h>
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/**@{*/
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uint32_t rcc_ahb_frequency = 16000000;
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uint32_t rcc_apb1_frequency = 16000000;
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uint32_t rcc_apb2_frequency = 16000000;
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// All PLL configurations without PLLM. PLLM should be set to the input clock
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// frequency in MHz.
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const struct rcc_clock_scale rcc_3v3[RCC_CLOCK_3V3_END] = {
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{ /* 216MHz */
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.plln = 432,
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.pllp = 2,
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.pllq = 9,
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.hpre = RCC_CFGR_HPRE_NODIV,
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.ppre1 = RCC_CFGR_PPRE_DIV4,
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.ppre2 = RCC_CFGR_PPRE_DIV2,
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.vos_scale = PWR_SCALE1,
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.overdrive = 1,
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.flash_waitstates = 7,
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.ahb_frequency = 216000000,
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.apb1_frequency = 54000000,
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.apb2_frequency = 108000000,
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},
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{ /* 168MHz */
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.plln = 336,
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.pllp = 2,
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.pllq = 7,
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.hpre = RCC_CFGR_HPRE_NODIV,
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.ppre1 = RCC_CFGR_PPRE_DIV4,
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.ppre2 = RCC_CFGR_PPRE_DIV2,
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.vos_scale = PWR_SCALE2,
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.overdrive = 1,
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.flash_waitstates = 5,
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.ahb_frequency = 168000000,
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.apb1_frequency = 42000000,
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.apb2_frequency = 84000000,
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},
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{ /* 120MHz */
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.plln = 240,
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.pllp = 2,
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.pllq = 5,
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.hpre = RCC_CFGR_HPRE_NODIV,
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.ppre1 = RCC_CFGR_PPRE_DIV4,
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.ppre2 = RCC_CFGR_PPRE_DIV2,
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.vos_scale = PWR_SCALE3,
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.overdrive = 0,
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.flash_waitstates = 3,
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.ahb_frequency = 120000000,
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.apb1_frequency = 30000000,
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.apb2_frequency = 60000000,
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},
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{ /* 72MHz */
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.plln = 144,
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.pllp = 2,
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.pllq = 3,
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.hpre = RCC_CFGR_HPRE_NODIV,
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.ppre1 = RCC_CFGR_PPRE_DIV4,
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.ppre2 = RCC_CFGR_PPRE_DIV2,
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.vos_scale = PWR_SCALE3,
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.overdrive = 0,
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.flash_waitstates = 2,
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.ahb_frequency = 72000000,
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.apb1_frequency = 18000000,
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.apb2_frequency = 36000000,
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},
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{ /* 48MHz */
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.plln = 192,
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.pllp = 4,
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.pllq = 4,
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.hpre = RCC_CFGR_HPRE_NODIV,
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.ppre1 = RCC_CFGR_PPRE_DIV2,
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.ppre2 = RCC_CFGR_PPRE_DIV2,
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.vos_scale = PWR_SCALE3,
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.overdrive = 0,
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.flash_waitstates = 1,
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.ahb_frequency = 48000000,
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.apb1_frequency = 24000000,
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.apb2_frequency = 24000000,
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},
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{ /* 24MHz */
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.plln = 192,
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.pllp = 8,
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.pllq = 4,
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.hpre = RCC_CFGR_HPRE_NODIV,
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.ppre1 = RCC_CFGR_PPRE_NODIV,
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.ppre2 = RCC_CFGR_PPRE_NODIV,
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.vos_scale = PWR_SCALE3,
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.overdrive = 0,
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.flash_waitstates = 0,
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.ahb_frequency = 24000000,
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.apb1_frequency = 24000000,
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.apb2_frequency = 24000000,
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}
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};
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void rcc_osc_ready_int_clear(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CIR |= RCC_CIR_PLLRDYC;
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break;
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case RCC_HSE:
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RCC_CIR |= RCC_CIR_HSERDYC;
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break;
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case RCC_HSI:
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RCC_CIR |= RCC_CIR_HSIRDYC;
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break;
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case RCC_LSE:
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RCC_CIR |= RCC_CIR_LSERDYC;
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break;
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case RCC_LSI:
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RCC_CIR |= RCC_CIR_LSIRDYC;
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break;
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}
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}
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void rcc_osc_ready_int_enable(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CIR |= RCC_CIR_PLLRDYIE;
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break;
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case RCC_HSE:
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RCC_CIR |= RCC_CIR_HSERDYIE;
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break;
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case RCC_HSI:
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RCC_CIR |= RCC_CIR_HSIRDYIE;
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break;
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case RCC_LSE:
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RCC_CIR |= RCC_CIR_LSERDYIE;
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break;
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case RCC_LSI:
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RCC_CIR |= RCC_CIR_LSIRDYIE;
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break;
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}
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}
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void rcc_osc_ready_int_disable(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CIR &= ~RCC_CIR_PLLRDYIE;
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break;
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case RCC_HSE:
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RCC_CIR &= ~RCC_CIR_HSERDYIE;
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break;
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case RCC_HSI:
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RCC_CIR &= ~RCC_CIR_HSIRDYIE;
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break;
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case RCC_LSE:
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RCC_CIR &= ~RCC_CIR_LSERDYIE;
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break;
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case RCC_LSI:
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RCC_CIR &= ~RCC_CIR_LSIRDYIE;
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break;
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}
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}
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int rcc_osc_ready_int_flag(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0);
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break;
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case RCC_HSE:
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return ((RCC_CIR & RCC_CIR_HSERDYF) != 0);
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break;
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case RCC_HSI:
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return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0);
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break;
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case RCC_LSE:
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return ((RCC_CIR & RCC_CIR_LSERDYF) != 0);
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break;
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case RCC_LSI:
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return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0);
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break;
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}
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cm3_assert_not_reached();
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}
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void rcc_css_int_clear(void)
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{
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RCC_CIR |= RCC_CIR_CSSC;
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}
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int rcc_css_int_flag(void)
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{
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return ((RCC_CIR & RCC_CIR_CSSF) != 0);
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}
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void rcc_wait_for_osc_ready(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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while ((RCC_CR & RCC_CR_PLLRDY) == 0);
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break;
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case RCC_HSE:
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while ((RCC_CR & RCC_CR_HSERDY) == 0);
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break;
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case RCC_HSI:
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while ((RCC_CR & RCC_CR_HSIRDY) == 0);
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break;
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case RCC_LSE:
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while ((RCC_BDCR & RCC_BDCR_LSERDY) == 0);
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break;
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case RCC_LSI:
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while ((RCC_CSR & RCC_CSR_LSIRDY) == 0);
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break;
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}
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}
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void rcc_wait_for_sysclk_status(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_PLL);
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break;
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case RCC_HSE:
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while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSE);
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break;
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case RCC_HSI:
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while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSI);
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break;
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default:
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/* Shouldn't be reached. */
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break;
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}
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}
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void rcc_osc_on(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CR |= RCC_CR_PLLON;
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break;
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case RCC_HSE:
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RCC_CR |= RCC_CR_HSEON;
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break;
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case RCC_HSI:
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RCC_CR |= RCC_CR_HSION;
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break;
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case RCC_LSE:
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RCC_BDCR |= RCC_BDCR_LSEON;
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break;
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case RCC_LSI:
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RCC_CSR |= RCC_CSR_LSION;
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break;
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}
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}
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void rcc_osc_off(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CR &= ~RCC_CR_PLLON;
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break;
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case RCC_HSE:
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RCC_CR &= ~RCC_CR_HSEON;
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break;
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case RCC_HSI:
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RCC_CR &= ~RCC_CR_HSION;
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break;
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case RCC_LSE:
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RCC_BDCR &= ~RCC_BDCR_LSEON;
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break;
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case RCC_LSI:
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RCC_CSR &= ~RCC_CSR_LSION;
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break;
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}
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}
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void rcc_css_enable(void)
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{
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RCC_CR |= RCC_CR_CSSON;
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}
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void rcc_css_disable(void)
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{
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RCC_CR &= ~RCC_CR_CSSON;
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}
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void rcc_set_sysclk_source(uint32_t clk)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~(RCC_CFGR_SW_MASK << RCC_CFGR_SW_SHIFT);
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RCC_CFGR = (reg32 | (clk << RCC_CFGR_SW_SHIFT));
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}
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void rcc_set_pll_source(uint32_t pllsrc)
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{
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uint32_t reg32;
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reg32 = RCC_PLLCFGR;
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reg32 &= ~(1 << 22);
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RCC_PLLCFGR = (reg32 | (pllsrc << 22));
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}
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void rcc_set_ppre2(uint32_t ppre2)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~(RCC_CFGR_PPRE2_MASK << RCC_CFGR_PPRE2_SHIFT);
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RCC_CFGR = (reg32 | (ppre2 << RCC_CFGR_PPRE2_SHIFT));
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}
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void rcc_set_ppre1(uint32_t ppre1)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~(RCC_CFGR_PPRE1_MASK << RCC_CFGR_PPRE1_SHIFT);
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RCC_CFGR = (reg32 | (ppre1 << RCC_CFGR_PPRE1_SHIFT));
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}
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void rcc_set_hpre(uint32_t hpre)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~(RCC_CFGR_HPRE_MASK << RCC_CFGR_HPRE_SHIFT);
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RCC_CFGR = (reg32 | (hpre << RCC_CFGR_HPRE_SHIFT));
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}
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void rcc_set_rtcpre(uint32_t rtcpre)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~(RCC_CFGR_RTCPRE_MASK << RCC_CFGR_RTCPRE_SHIFT);
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RCC_CFGR = (reg32 | (rtcpre << RCC_CFGR_RTCPRE_SHIFT));
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}
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void rcc_set_main_pll_hsi(uint32_t pllm, uint32_t plln, uint32_t pllp,
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uint32_t pllq)
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{
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RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) |
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(plln << RCC_PLLCFGR_PLLN_SHIFT) |
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(((pllp >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) |
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(pllq << RCC_PLLCFGR_PLLQ_SHIFT);
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}
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void rcc_set_main_pll_hse(uint32_t pllm, uint32_t plln, uint32_t pllp,
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uint32_t pllq)
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{
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RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) |
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(plln << RCC_PLLCFGR_PLLN_SHIFT) |
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(((pllp >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) |
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RCC_PLLCFGR_PLLSRC |
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(pllq << RCC_PLLCFGR_PLLQ_SHIFT);
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}
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uint32_t rcc_system_clock_source(void)
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{
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/* Return the clock source which is used as system clock. */
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return (RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK;
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}
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void rcc_clock_setup_hse(const struct rcc_clock_scale *clock, uint32_t hse_mhz)
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{
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uint8_t pllm = hse_mhz;
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/* Enable internal high-speed oscillator. */
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rcc_osc_on(RCC_HSI);
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rcc_wait_for_osc_ready(RCC_HSI);
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/* Select HSI as SYSCLK source. */
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rcc_set_sysclk_source(RCC_CFGR_SW_HSI);
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/* Enable external high-speed oscillator. */
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rcc_osc_on(RCC_HSE);
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rcc_wait_for_osc_ready(RCC_HSE);
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rcc_periph_clock_enable(RCC_PWR);
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pwr_set_vos_scale(clock->vos_scale);
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if (clock->overdrive) {
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pwr_enable_overdrive();
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}
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/*
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* Set prescalers for AHB, ADC, APB1, APB2.
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* Do this before touching the PLL (TODO: why?).
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*/
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rcc_set_hpre(clock->hpre);
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rcc_set_ppre1(clock->ppre1);
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rcc_set_ppre2(clock->ppre2);
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/* Disable PLL oscillator before changing its configuration. */
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rcc_osc_off(RCC_PLL);
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/* Configure the PLL oscillator. */
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rcc_set_main_pll_hse(pllm, clock->plln,
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clock->pllp, clock->pllq);
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/* Enable PLL oscillator and wait for it to stabilize. */
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rcc_osc_on(RCC_PLL);
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rcc_wait_for_osc_ready(RCC_PLL);
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/* Configure flash settings. */
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flash_set_ws(clock->flash_waitstates);
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flash_art_enable();
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flash_prefetch_enable();
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/* Select PLL as SYSCLK source. */
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rcc_set_sysclk_source(RCC_CFGR_SW_PLL);
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/* Wait for PLL clock to be selected. */
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rcc_wait_for_sysclk_status(RCC_PLL);
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/* Set the clock frequencies used. */
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rcc_ahb_frequency = clock->ahb_frequency;
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rcc_apb1_frequency = clock->apb1_frequency;
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rcc_apb2_frequency = clock->apb2_frequency;
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/* Disable internal high-speed oscillator. */
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rcc_osc_off(RCC_HSI);
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}
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void rcc_clock_setup_hsi(const struct rcc_clock_scale *clock)
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{
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uint8_t pllm = 16;
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/* Enable internal high-speed oscillator. */
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rcc_osc_on(RCC_HSI);
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rcc_wait_for_osc_ready(RCC_HSI);
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/* Select HSI as SYSCLK source. */
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rcc_set_sysclk_source(RCC_CFGR_SW_HSI);
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rcc_periph_clock_enable(RCC_PWR);
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pwr_set_vos_scale(clock->vos_scale);
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if (clock->overdrive) {
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pwr_enable_overdrive();
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}
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/*
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* Set prescalers for AHB, ADC, APB1, APB2.
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* Do this before touching the PLL (TODO: why?).
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*/
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rcc_set_hpre(clock->hpre);
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rcc_set_ppre1(clock->ppre1);
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rcc_set_ppre2(clock->ppre2);
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rcc_set_main_pll_hsi(pllm, clock->plln,
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clock->pllp, clock->pllq);
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/* Enable PLL oscillator and wait for it to stabilize. */
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rcc_osc_on(RCC_PLL);
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rcc_wait_for_osc_ready(RCC_PLL);
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/* Configure flash settings. */
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flash_set_ws(clock->flash_waitstates);
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flash_art_enable();
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flash_prefetch_enable();
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/* Select PLL as SYSCLK source. */
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rcc_set_sysclk_source(RCC_CFGR_SW_PLL);
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/* Wait for PLL clock to be selected. */
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rcc_wait_for_sysclk_status(RCC_PLL);
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/* Set the clock frequencies used. */
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rcc_ahb_frequency = clock->ahb_frequency;
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rcc_apb1_frequency = clock->apb1_frequency;
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rcc_apb2_frequency = clock->apb2_frequency;
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}
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static uint32_t rcc_usart_i2c_clksel_freq(uint32_t apb_clk, uint8_t shift) {
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uint8_t clksel = (RCC_DCKCFGR2 >> shift) & RCC_DCKCFGR2_UART1SEL_MASK;
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uint8_t hpre = (RCC_CFGR >> RCC_CFGR_HPRE_SHIFT) & RCC_CFGR_HPRE_MASK;
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switch (clksel) {
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case RCC_DCKCFGR2_UARTxSEL_PCLK:
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return apb_clk;
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case RCC_DCKCFGR2_UARTxSEL_SYSCLK:
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return rcc_ahb_frequency * rcc_get_div_from_hpre(hpre);
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case RCC_DCKCFGR2_UARTxSEL_HSI:
|
|
return 16000000U;
|
|
default:
|
|
cm3_assert_not_reached();
|
|
}
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief Get the peripheral clock speed for the USART at base specified.
|
|
* @param usart Base address of USART to get clock frequency for.
|
|
*/
|
|
uint32_t rcc_get_usart_clk_freq(uint32_t usart)
|
|
{
|
|
/* F7 is highly configurable, every USART can be configured in DCKCFGR2. */
|
|
if (usart == USART1_BASE) {
|
|
return rcc_usart_i2c_clksel_freq(rcc_apb2_frequency, RCC_DCKCFGR2_UART1SEL_SHIFT);
|
|
} else if (usart == USART2_BASE) {
|
|
return rcc_usart_i2c_clksel_freq(rcc_apb1_frequency, RCC_DCKCFGR2_UART2SEL_SHIFT);
|
|
} else if (usart == USART3_BASE) {
|
|
return rcc_usart_i2c_clksel_freq(rcc_apb1_frequency, RCC_DCKCFGR2_UART3SEL_SHIFT);
|
|
} else if (usart == UART4_BASE) {
|
|
return rcc_usart_i2c_clksel_freq(rcc_apb1_frequency, RCC_DCKCFGR2_UART4SEL_SHIFT);
|
|
} else if (usart == UART5_BASE) {
|
|
return rcc_usart_i2c_clksel_freq(rcc_apb1_frequency, RCC_DCKCFGR2_UART5SEL_SHIFT);
|
|
} else if (usart == USART6_BASE) {
|
|
return rcc_usart_i2c_clksel_freq(rcc_apb2_frequency, RCC_DCKCFGR2_USART6SEL_SHIFT);
|
|
} else if (usart == UART7_BASE) {
|
|
return rcc_usart_i2c_clksel_freq(rcc_apb1_frequency, RCC_DCKCFGR2_UART7SEL_SHIFT);
|
|
} else { /* UART8 */
|
|
return rcc_usart_i2c_clksel_freq(rcc_apb1_frequency, RCC_DCKCFGR2_UART8SEL_SHIFT);
|
|
}
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief Get the peripheral clock speed for the Timer at base specified.
|
|
* @param timer Base address of TIM to get clock frequency for.
|
|
*/
|
|
uint32_t rcc_get_timer_clk_freq(uint32_t timer)
|
|
{
|
|
/* Handle APB1 timer clocks. */
|
|
if (timer >= TIM2_BASE && timer <= TIM14_BASE) {
|
|
uint8_t ppre1 = (RCC_CFGR >> RCC_CFGR_PPRE1_SHIFT) & RCC_CFGR_PPRE1_MASK;
|
|
return (ppre1 == RCC_CFGR_PPRE_DIV_NONE) ? rcc_apb1_frequency
|
|
: 2 * rcc_apb1_frequency;
|
|
} else {
|
|
uint8_t ppre2 = (RCC_CFGR >> RCC_CFGR_PPRE2_SHIFT) & RCC_CFGR_PPRE2_MASK;
|
|
return (ppre2 == RCC_CFGR_PPRE_DIV_NONE) ? rcc_apb2_frequency
|
|
: 2 * rcc_apb2_frequency;
|
|
}
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief Get the peripheral clock speed for the I2C device at base specified.
|
|
* @param i2c Base address of I2C to get clock frequency for.
|
|
*/
|
|
uint32_t rcc_get_i2c_clk_freq(uint32_t i2c __attribute__((unused)))
|
|
{
|
|
if (i2c == I2C1_BASE) {
|
|
return rcc_usart_i2c_clksel_freq(rcc_apb1_frequency, RCC_DCKCFGR2_I2C1SEL_SHIFT);
|
|
} else if (i2c == I2C2_BASE) {
|
|
return rcc_usart_i2c_clksel_freq(rcc_apb1_frequency, RCC_DCKCFGR2_I2C2SEL_SHIFT);
|
|
} else if (i2c == I2C3_BASE) {
|
|
return rcc_usart_i2c_clksel_freq(rcc_apb1_frequency, RCC_DCKCFGR2_I2C3SEL_SHIFT);
|
|
} else { /* I2C4 */
|
|
return rcc_usart_i2c_clksel_freq(rcc_apb1_frequency, RCC_DCKCFGR2_I2C4SEL_SHIFT);
|
|
}
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/** @brief Get the peripheral clock speed for the SPI device at base specified.
|
|
* @param spi Base address of SPI device to get clock frequency for (e.g. SPI1_BASE).
|
|
*/
|
|
uint32_t rcc_get_spi_clk_freq(uint32_t spi) {
|
|
if (spi == SPI2_BASE || spi == SPI3_BASE) {
|
|
return rcc_apb1_frequency;
|
|
} else {
|
|
return rcc_apb2_frequency;
|
|
}
|
|
}
|
|
/**@}*/
|