Arti Zirk
244fdbc35c
subrepo: subdir: "libopencm3" merged: "f5813a54" upstream: origin: "https://github.com/libopencm3/libopencm3" branch: "master" commit: "f5813a54" git-subrepo: version: "0.4.3" origin: "???" commit: "???"
78 lines
2.0 KiB
C
78 lines
2.0 KiB
C
/** @defgroup rcc_file RCC Controller
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@brief <b>LM3S RCC Controller</b>
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@ingroup LM3Sxx
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@version 1.0.0
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@author @htmlonly © @endhtmlonly 2015
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Daniele Lacamera \<root at danielinux dot net\>
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@date 21 November 2015
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2015 Daniele Lacamera <root@danielinux.net>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdint.h>
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#include <libopencm3/lm3s/rcc.h>
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#include <libopencm3/cm3/sync.h>
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int rcc_clock_setup_in_xtal_8mhz_out_50mhz(void)
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{
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uint32_t rcc = RCC_RESET_VALUE;
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uint32_t rcc2 = RCC2_RESET_VALUE;
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/* Stage 0: Reset values applied */
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RCC_CR = rcc;
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RCC2_CR = rcc2;
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__dmb();
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/* Stage 1: Reset Oscillators and select configured values */
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RCC_CR = RCC_SYSDIV_50MHZ | RCC_PWMDIV_64 | RCC_XTAL_8MHZ_400MHZ | RCC_USEPWMDIV;
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RCC2_CR = (4 - 1) << RCC2_SYSDIV2_SHIFT;
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__dmb();
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/* Stage 2: Power on oscillators */
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rcc &= ~RCC_OFF;
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rcc2 &= ~RCC2_OFF;
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RCC_CR = rcc;
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RCC2_CR = rcc2;
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__dmb();
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/* Stage 3: Set USESYSDIV */
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rcc |= RCC_BYPASS | RCC_USESYSDIV;
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RCC_CR = rcc;
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__dmb();
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/* Stage 4: Wait for PLL raw interrupt */
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while ((RCC_RIS & RIS_PLLLRIS) == 0)
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;
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/* Stage 5: Disable bypass */
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rcc &= ~RCC_BYPASS;
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rcc2 &= ~RCC2_BYPASS;
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RCC_CR = rcc;
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RCC2_CR = rcc2;
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__dmb();
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return 0;
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}
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