Arti Zirk
244fdbc35c
subrepo: subdir: "libopencm3" merged: "f5813a54" upstream: origin: "https://github.com/libopencm3/libopencm3" branch: "master" commit: "f5813a54" git-subrepo: version: "0.4.3" origin: "???" commit: "???"
444 lines
13 KiB
C
444 lines
13 KiB
C
/** @addtogroup adc_file ADC peripheral API
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@ingroup peripheral_apis
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@version 1.0.0
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@author @htmlonly © @endhtmlonly 2009
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Edward Cheeseman <evbuilder@users.sourceforge.net>
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@author @htmlonly © @endhtmlonly 2012
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Ken Sarkies <ksarkies@internode.on.net>
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@date 18 August 2012
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This library supports the A/D Converter Control System in the STM32F1xx series
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of ARM Cortex Microcontrollers by ST Microelectronics.
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Devices can have up to three A/D converters each with their own set of
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registers. However all the A/D converters share a common clock which is
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prescaled from the APB2 clock by default by a minimum factor of 2 to a maximum
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of 8.
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Each A/D converter has up to 18 channels:
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@li On ADC1 the analog channels 16 and 17 are internally connected to the
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temperature
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sensor and V<sub>REFINT</sub>, respectively.
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@li On ADC2 the analog channels 16 and 17 are internally connected to
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V<sub>SS</sub>.
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@li On ADC3 the analog channels 9, 14, 15, 16 and 17 are internally connected
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to V<sub>SS</sub>.
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The conversions can occur as a one-off conversion whereby the process stops
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once conversion is complete. The conversions can also be continuous wherein a
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new conversion starts immediately the previous conversion has ended.
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Conversion can occur as a single channel conversion or a scan of a group of
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channels in either continuous or one-off mode. If more than one channel is
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converted in a scan group, DMA must be used to transfer the data as there is
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only one result register available. An interrupt can be set to occur at the end
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of conversion, which occurs after all channels have been scanned.
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A discontinuous mode allows a subgroup of group of a channels to be converted
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in bursts of a given length.
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Injected conversions allow a second group of channels to be converted
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separately from the regular group. An interrupt can be set to occur at the end
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of conversion, which occurs after all channels have been scanned.
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@section adc_api_ex Basic ADC Handling API.
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Example 1: Simple single channel conversion polled. Enable the peripheral clock
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and ADC, reset ADC and set the prescaler divider. Set dual mode to independent
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(default). Enable triggering for a software trigger.
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@code
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rcc_periph_clock_enable(RCC_ADC1);
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adc_power_off(ADC1);
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rcc_periph_reset_pulse(RST_ADC1);
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rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV2);
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adc_set_dual_mode(ADC_CR1_DUALMOD_IND);
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adc_disable_scan_mode(ADC1);
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adc_set_single_conversion_mode(ADC1);
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adc_set_sample_time(ADC1, ADC_CHANNEL0, ADC_SMPR_SMP_1DOT5CYC);
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adc_enable_external_trigger_regular(ADC1, ADC_CR2_EXTSEL_SWSTART);
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adc_power_on(ADC1);
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adc_reset_calibration(ADC1);
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adc_calibrate(ADC1);
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adc_start_conversion_regular(ADC1);
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while (! adc_eoc(ADC1));
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reg16 = adc_read_regular(ADC1);
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@endcode
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2009 Edward Cheeseman <evbuilder@users.sourceforge.net>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#include <libopencm3/stm32/adc.h>
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Power On
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If the ADC is in power-down mode then it is powered up. The application needs
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to wait a time of about 3 microseconds for stabilization before using the ADC.
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If the ADC is already on this function call has no effect.
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* NOTE Common with F37x
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@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
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*/
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void adc_power_on(uint32_t adc)
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{
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if (!(ADC_CR2(adc) & ADC_CR2_ADON)) {
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ADC_CR2(adc) |= ADC_CR2_ADON;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Start a Conversion Without Trigger
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This initiates a conversion by software without a trigger. The ADC needs to be
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powered on before this is called, otherwise this function has no effect.
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Note that this is not available in other STM32F families. To ensure code
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compatibility, enable triggering and use a software trigger source @see
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adc_start_conversion_regular.
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@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
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*/
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void adc_start_conversion_direct(uint32_t adc)
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{
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if (ADC_CR2(adc) & ADC_CR2_ADON) {
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ADC_CR2(adc) |= ADC_CR2_ADON;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Set Dual A/D Mode
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The dual mode uses ADC1 as master and ADC2 in a slave arrangement. This setting
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is applied to ADC1 only. Start of conversion when triggered can cause
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simultaneous conversion with ADC2, or alternate conversion. Regular and
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injected conversions can be configured, each one being separately simultaneous
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or alternate.
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Fast interleaved mode starts ADC1 immediately on trigger, and ADC2 seven clock
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cycles later.
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Slow interleaved mode starts ADC1 immediately on trigger, and ADC2 fourteen
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clock cycles later, followed by ADC1 fourteen cycles later again. This can only
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be used on a single channel.
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Alternate trigger mode must occur on an injected channel group, and alternates
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between the ADCs on each trigger.
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Note that sampling must not overlap between ADCs on the same channel.
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Dual A/D converter modes possible:
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@li IND: Independent mode.
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@li CRSISM: Combined regular simultaneous + injected simultaneous mode.
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@li CRSATM: Combined regular simultaneous + alternate trigger mode.
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@li CISFIM: Combined injected simultaneous + fast interleaved mode.
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@li CISSIM: Combined injected simultaneous + slow interleaved mode.
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@li ISM: Injected simultaneous mode only.
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@li RSM: Regular simultaneous mode only.
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@li FIM: Fast interleaved mode only.
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@li SIM: Slow interleaved mode only.
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@li ATM: Alternate trigger mode only.
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@param[in] mode Unsigned int32. Dual mode selection from @ref adc_cr1_dualmod
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*/
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void adc_set_dual_mode(uint32_t mode)
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{
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ADC1_CR1 |= mode;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Enable The Temperature Sensor
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This enables both the sensor and the reference voltage measurements on channels
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16 and 17.
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*/
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void adc_enable_temperature_sensor()
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{
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ADC_CR2(ADC1) |= ADC_CR2_TSVREFE;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Disable The Temperature Sensor
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Disabling this will reduce power consumption from the sensor and the reference
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voltage measurements.
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*/
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void adc_disable_temperature_sensor()
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{
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ADC_CR2(ADC1) &= ~ADC_CR2_TSVREFE;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Enable an External Trigger for Regular Channels
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This enables an external trigger for set of defined regular channels.
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For ADC1 and ADC2
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@li Timer 1 CC1 event
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@li Timer 1 CC2 event
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@li Timer 1 CC3 event
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@li Timer 2 CC2 event
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@li Timer 3 TRGO event
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@li Timer 4 CC4 event
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@li EXTI (TIM8_TRGO is also possible on some devices, see datasheet)
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@li Software Start
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For ADC3
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@li Timer 3 CC1 event
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@li Timer 2 CC3 event
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@li Timer 1 CC3 event
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@li Timer 8 CC1 event
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@li Timer 8 TRGO event
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@li Timer 5 CC1 event
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@li Timer 5 CC3 event
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@li Software Start
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@param[in] adc Unsigned int32. ADC block register address base @ref
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adc_reg_base.
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@param[in] trigger Unsigned int8. Trigger identifier @ref adc_trigger_regular_12
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for ADC1 and ADC2, or @ref adc_trigger_regular_3 for ADC3.
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*/
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void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger)
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{
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uint32_t reg32;
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reg32 = (ADC_CR2(adc) & ~(ADC_CR2_EXTSEL_MASK));
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reg32 |= (trigger);
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ADC_CR2(adc) = reg32;
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ADC_CR2(adc) |= ADC_CR2_EXTTRIG;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Disable an External Trigger for Regular Channels
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@param[in] adc Unsigned int32. ADC block register address base @ref
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adc_reg_base.
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*/
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void adc_disable_external_trigger_regular(uint32_t adc)
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{
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ADC_CR2(adc) &= ~ADC_CR2_EXTTRIG;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Enable an External Trigger for Injected Channels
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This enables an external trigger for set of defined injected channels.
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For ADC1 and ADC2
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@li Timer 1 TRGO event
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@li Timer 1 CC4 event
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@li Timer 2 TRGO event
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@li Timer 2 CC1 event
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@li Timer 3 CC4 event
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@li Timer 4 TRGO event
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@li EXTI (TIM8 CC4 is also possible on some devices, see datasheet)
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@li Software Start
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For ADC3
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@li Timer 1 TRGO event
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@li Timer 1 CC4 event
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@li Timer 4 CC3 event
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@li Timer 8 CC2 event
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@li Timer 8 CC4 event
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@li Timer 5 TRGO event
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@li Timer 5 CC4 event
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@li Software Start
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@param[in] adc Unsigned int32. ADC block register address base @ref
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adc_reg_base.
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@param[in] trigger Unsigned int8. Trigger identifier @ref
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adc_trigger_injected_12 for ADC1 and ADC2, or @ref adc_trigger_injected_3 for
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ADC3.
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*/
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void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger)
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{
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uint32_t reg32;
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reg32 = (ADC_CR2(adc) & ~(ADC_CR2_JEXTSEL_MASK)); /* Clear bits [12:14]
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*/
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reg32 |= (trigger);
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ADC_CR2(adc) = reg32;
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ADC_CR2(adc) |= ADC_CR2_JEXTTRIG;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Disable an External Trigger for Injected Channels
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@param[in] adc Unsigned int32. ADC block register address base @ref
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adc_reg_base.
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*/
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void adc_disable_external_trigger_injected(uint32_t adc)
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{
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ADC_CR2(adc) &= ~ADC_CR2_JEXTTRIG;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Initialize Calibration Registers
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This resets the calibration registers. It is not clear if this is required to be
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done before every calibration operation.
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@param[in] adc Unsigned int32. ADC block register address base @ref
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adc_reg_base.
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*/
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void adc_reset_calibration(uint32_t adc)
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{
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ADC_CR2(adc) |= ADC_CR2_RSTCAL;
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while (ADC_CR2(adc) & ADC_CR2_RSTCAL);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Calibration
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@deprecated replaced by adc_calibrate/_async/_is_calibrating
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The calibration data for the ADC is recomputed. The hardware clears the
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calibration status flag when calibration is complete. This function does not
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return until this happens and the ADC is ready for use.
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The ADC must have been powered down for at least 2 ADC clock cycles, then
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powered on. before calibration starts
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@param[in] adc Unsigned int32. ADC block register address base @ref
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adc_reg_base.
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*/
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void adc_calibration(uint32_t adc)
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{
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ADC_CR2(adc) |= ADC_CR2_CAL;
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while (ADC_CR2(adc) & ADC_CR2_CAL);
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}
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/**
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* Start the ADC calibration and immediately return.
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* @sa adc_calibrate
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* @sa adc_is_calibrate
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* @param adc ADC Block register address base @ref adc_reg_base
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*/
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void adc_calibrate_async(uint32_t adc)
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{
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ADC_CR2(adc) |= ADC_CR2_CAL;
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}
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/**
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* Is the ADC Calibrating?
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* @param adc ADC Block register address base @ref adc_reg_base
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* @return true if the adc is currently calibrating
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*/
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bool adc_is_calibrating(uint32_t adc)
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{
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return (ADC_CR2(adc) & ADC_CR2_CAL);
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}
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/**
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* Start ADC calibration and wait for it to finish.
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* The ADC must have been powered down for at least 2 ADC clock cycles, then
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* powered on before calibration starts
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* @param adc ADC Block register address base @ref adc_reg_base
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*/
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void adc_calibrate(uint32_t adc)
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{
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adc_calibrate_async(adc);
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while (adc_is_calibrating(adc));
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Set the Sample Time for a Single Channel
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The sampling time can be selected in ADC clock cycles from 1.5 to 239.5.
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@param[in] adc Unsigned int32. ADC block register address base @ref
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adc_reg_base.
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@param[in] channel Unsigned int8. ADC Channel integer 0..18 or from @ref
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adc_channel.
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@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg.
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* * NOTE Common with f2 and f37x and f4
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*/
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void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time)
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{
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uint32_t reg32;
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if (channel < 10) {
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reg32 = ADC_SMPR2(adc);
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reg32 &= ~(0x7 << (channel * 3));
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reg32 |= (time << (channel * 3));
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ADC_SMPR2(adc) = reg32;
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} else {
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reg32 = ADC_SMPR1(adc);
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reg32 &= ~(0x7 << ((channel - 10) * 3));
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reg32 |= (time << ((channel - 10) * 3));
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ADC_SMPR1(adc) = reg32;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Set the Sample Time for All Channels
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The sampling time can be selected in ADC clock cycles from 1.5 to 239.5, same
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for all channels.
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@param[in] adc Unsigned int32. ADC block register address base @ref
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adc_reg_base.
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@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg.
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* * NOTE Common with f2 and f37x and f4
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*/
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void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time)
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{
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uint8_t i;
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uint32_t reg32 = 0;
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for (i = 0; i <= 9; i++) {
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reg32 |= (time << (i * 3));
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}
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ADC_SMPR2(adc) = reg32;
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for (i = 10; i <= 17; i++) {
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reg32 |= (time << ((i - 10) * 3));
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}
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ADC_SMPR1(adc) = reg32;
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}
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/*---------------------------------------------------------------------------*/
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/**@}*/
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