Arti Zirk
244fdbc35c
subrepo: subdir: "libopencm3" merged: "f5813a54" upstream: origin: "https://github.com/libopencm3/libopencm3" branch: "master" commit: "f5813a54" git-subrepo: version: "0.4.3" origin: "???" commit: "???"
91 lines
2.5 KiB
C
91 lines
2.5 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2015 Karl Palsson <karlp@tweak.net.au>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/cm3/nvic.h>
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#include <libopencm3/stm32/crs.h>
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#include <libopencm3/stm32/gpio.h>
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#include <libopencm3/stm32/rcc.h>
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#include <libopencm3/stm32/syscfg.h>
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#include <stdio.h>
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#include "usb-gadget0.h"
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/* no trace on cm0 #define ER_DEBUG */
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#ifdef ER_DEBUG
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#define ER_DPRINTF(fmt, ...) \
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do { printf(fmt, ## __VA_ARGS__); } while (0)
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#else
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#define ER_DPRINTF(fmt, ...) \
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do { } while (0)
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#endif
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#include "trace.h"
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void trace_send_blocking8(int stimulus_port, char c)
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{
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(void)stimulus_port;
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(void)c;
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}
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int main(void)
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{
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/* LED for boot progress */
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rcc_periph_clock_enable(RCC_GPIOA);
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gpio_mode_setup(GPIOA, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO5);
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gpio_set(GPIOA, GPIO5);
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/* PLL from HSI16, just to exercise that code */
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struct rcc_clock_scale myclock = {
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.ahb_frequency = 32e6,
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.apb1_frequency = 32e6,
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.apb2_frequency = 32e6,
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.flash_waitstates = 1,
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.pll_source = RCC_CFGR_PLLSRC_HSI16_CLK, /* not even sure there's hse on l053 disco */
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/* .msi_range doesn't matter */
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.pll_mul = RCC_CFGR_PLLMUL_MUL4,
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.pll_div = RCC_CFGR_PLLDIV_DIV2,
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.hpre = RCC_CFGR_HPRE_NODIV,
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.ppre1 = RCC_CFGR_PPRE1_NODIV,
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.ppre2 = RCC_CFGR_PPRE2_NODIV,
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};
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rcc_clock_setup_pll(&myclock);
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/* HSI48 needs the vrefint turned on */
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rcc_periph_clock_enable(RCC_SYSCFG);
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SYSCFG_CFGR3 |= SYSCFG_CFGR3_ENREF_HSI48 | SYSCFG_CFGR3_EN_VREFINT;
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while (!(SYSCFG_CFGR3 & SYSCFG_CFGR3_REF_HSI48_RDYF));
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/* For USB, but can't use HSI48 as a sysclock on L0 */
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crs_autotrim_usb_enable();
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rcc_set_hsi48_source_rc48();
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rcc_osc_on(RCC_HSI48);
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rcc_wait_for_osc_ready(RCC_HSI48);
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usbd_device *usbd_dev = gadget0_init(&st_usbfs_v2_usb_driver,
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"stm32l053disco");
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ER_DPRINTF("bootup complete\n");
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gpio_clear(GPIOA, GPIO5);
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while (1) {
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gadget0_run(usbd_dev);
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}
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}
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