EK-104AA-TM-001 


VCBO2 
Video Subsystem 


Technical Manual 


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Prepared by Educational Services 
of Dig 


„ „ ee ee ee ee ee ee e ee ee ee 


1987 


aioe RINNE RECRUIT 


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February 
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OMNIBUS 


CONTENTS 


K AMMA MSAMAAMAMAMAAMA MLM AMMAN IRANASE INSISTS MHA E RIES A AMIRI ANNAN S RASS 


Page 
PREFACE 


CHAPTER 1 GENERAL DESCRIPTION 


INTRODUCTION. „„ 
BASE MODE 
FOUR- PLANE MODUL 
PRINCIPAL FEATURES OF THE VCBO2 VIDEO SUBSYSTEM.... 
OPERATIONAL DESCRIPTI UU. 
Multiplane Suppolhuhh hh 
Viewport Suppohſwmꝶue et.. 
Ras te roo s 
Programmable Modes. 
Video Processor Data Manipulation 

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. Address Processor chip Registers. g 112 
e Video Processor chip Registers I-14 
1.6 APPLICATIONS 550k 454 ͥ K 
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„ Font Storage and Acces ũꝑꝙ47ß. 1-15 
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„ Character Attributes . 1-16 
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CHAPTER 2 CONFIGURATIONS AND INSTALLATION 
2 C ( ee bee Me eRe ee ]⁵¾»—AAA ³ ⁰ ..gũgĩmA 
22 SYSTEM CONFIGURATION. <044.44454.00045405 ² A es ee 
252 System Componente 323 
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Contents 


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Basic Address 
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Transfers 
Per formanſne 
Application to Tek k 
Font Storage and Acces. 
Normal Text .sccscccuscnensenevceneesses 
Variable-Pitch Teck. 
Rotated and Scaled Texckkttt.. 
Character Attributes 
Application to Graphics and Additional 
Suppforrkr rr 
Pines and Feet ers. 
Shading of Vectors - Linear 
PA ² ·¹.¹AA m ROO RS 
Fill Mode — Polyq ons 
POLYGON Fleck.. 
Oobjecttss e Bw a a 
ADDRESS PROCESSOR AND VIDEO PROCESSOR CHIP 
REGISTERS AND COMMAND ssi . 
Address Proc 
Address Processor Chip Registers 
Addres 35 Processor Chip Commands. 
Video Processor Chip (I/D Bus) Commands.. 
Video Processor Chip Registers 
Instruction/Data Bus Instructions 
Physical Configuration 
Address Processor Chip Pig... 
Video Processor Chip Pins 
Initialization.. 


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Address Processor Chip Addresses 
Gate Array Addresses. 
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Bitmap- to- Processor Transfers 
Display List Transfers 
Interrupt Controller 
CULSOF logie EH Oe eS 
Display List Data and Commands 
Display List Date. 
JMPT @ ADDRESS Commanede 
PTB NWORDS CommA@nd..cccccscveevreceevene 
Other Display List Commands 
Register Descriptions 
Control and Status Register 
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PROGRAMMING INFORMATIO 


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Physical Description..... 
Pack bal bs Pin Numbering.. 


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24-35 
„4-36 
. 4-38 
0 4-39 
. 4-42 
» 0 4~42 
. . 4-46 


Contents 


ü Ph 


85 
— 
les 


2-Axis Processor/Bitmap Transfers... 4-49 
ADDRESS PROCESSOR CHIP DESCRIPTIO WU... 4-49 
Coordinate Sys tees 450 
Address Processor chip Commands 4-50 
Ras terop Sem odes ew cess caanee GH 50 
Processor/Bitmap TranSferS..ccccevecveveveees e453 
VIDEO PROCESSOR CHIP DESCRIPTION. o ee ee ass 
2-Ax is Address ing Modlvlee .. ũ dq 4-36 
“Axis Register Loads ̃ ˙. 457 


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CHAPTER 5 DIAGNOSTICS 


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OVERVIEW. oc ccc eee ee ee meee eee eH ERED O REESE 
OPERATION. cece reer . 
IMPLEMENTATION. «ccc lll 
Per formanſts/e 
Compat ibilittꝶ „„ 
Hardware Faillue rr 
Unexpected Traoa s 
Power Failure s «„“ 
Restrictions „6 „„ „446 
DIAGNOSTIC OPERATIONAL REQUIREMENTS. ..eeeceeeeee 


HaAVAwALV es. cece ee eee em ee eee eee eee & 


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2 SOf( ware. EHH HEE HERE HE ORES 

FUNCTIONAL DESCRIPTI(ClU¶UUUUllllllll . 

Power-Up Self- Tess... 

1 Parameters Passed and Retur nec 

oe VCB02 DiagnoStic LEDS. . 
3 
4 


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Register Access and Data Test. 
Template RAM Tee. 
8 Address Processor Test. 
6 Address Processor and Video Processor 

Initialization Tce. 
Update Video Processor Enable Chip 8 
k ⁵ ↄ . ĩ 
Bitmap Memory ETC AA. re ee ee as bee 
9 Right Scroll PP ⅛˙¹àAʃ ey Cree ee ee cee 


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iene as Input Devices F330 aie Ok ae eee ee 
Calling Sequence 31 
cons sole f! ²”-n.. ²³⅛⁵²udü ery tre ed | 
Put Character Polli 519 
put Character 52 
Ger eee Knee d eee dade eee esa wor?’ 
5 VCBO2 ROM and Console Bus Reset 52 
nable VCBO2 ROM and Console Reset 52 

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9 Keyboard rue hatt ²˙ oe ee 5ae 0727 
we. Software SErviClreecccesesencsececcccsevenssee dual 
VCBO2 170 Space CSR Address ee ‚ ee ene ere ee a 


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APPENDIX A 


2 


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PPENDIX B 


U.S. 


Row and Column 


TCT 
Multinational Font Table 
Keycode Translate Character. 
Parameters... 
CSR Base. 


VCBO2 Memory 
Wait 1 Millisecond...... 


022.1 


GENERAL 
Master/Sl 


Q22-BUS 


SIGNAL ASS 


DATA TRANSFER BUS 
Bus CY le Protocol. 


Devi 


DIRECT MEMORY ACCE 


DMA 


DMA. 


0 


B 

DMA Guidelines. 
INTERRUPTS ...eee0 
Priority. 
Interrupt Protocol.. 


Device 


022-Bus 


CONTROL 


4~Level 
FUNCTIONS 


ae 


we 


i 


i 


. 


Space 


BUS SPECIFICATION 


ce 55 


ee 
Son « 


Protocol » ew 
Block Mode 
DATBI 


°° * ® th 


* * © e 


o © w & 


n e e e, 


e n en 


+ ¢ n ® 


Interr 


e ¢ © & 


Memory Refresh.. 


Halt... 
Initia 
Power 


lization. 
Status... 


F 
B POR 3 F 
~Up/Down Protocol 
CHARACTERISTICS. 
Load Definition..... 
120-Ohm Q22-—Bus 


Power 
022-BUS 


Dr 


ELECTRICAL 


iverS..e. 


Receivers.. 
Termination, 
Interconnecting Wiring. 


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DESCRIPTION. wesc 
ave Relationship. 
IGNMENTS 
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Backplane Wir ing. 


Intra- Backplane Bus 


Wiring 


Power and Ground +‘ * e e * wo oe +e & w& 
SYSTEM CONFIGURATIONS... .ceees 
Power Supply Loading. 


MODULE CONTACT FINGER IDENTIFICATION 
LK201 KEYBOARD SPECIFICATION 


GENERAL DESCRIPTION....... 
DESCRIPTION 0% ee ae 


PHYSICAL 


BLOCK DIAGRAM DESCRIPTION. 


Keyboard Scanning 


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.B-4 
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Contents 


CPP 


2 Control of Audio Transducer and Indicators. B-4 
ee Keyboard Firmware Functionnn 8-4 
3 Functions Not Changed by the System's Central 
%%% ꝰ ↄ ¶œ/ũ binkoenaee ee ckatuaweasaen Dee 
Bede sue Functions Changed by the System's Central 
!( . p we wwe bNOd Cae ae ee D6 
„ Firmware Functions That Can Be Changed.........B-6 
DETAILED KEYBOARD CIRCUIT DESCRIPTION. W.... B- 
KReybodta: M4trix SCanningi.<24.0 46-054 ͤ K 8 
Audio Transducer Control Circuit 812 
Indicator (LED) Control Circuit 3 813 
Reyooard Communications. [4 
Keyboard Transmit. dee A614 
Keyboard Receive Mode.wcccccccseccsseensesarest@l4 
Reset Signal for the 8051 Microprocessor........B-15 
Hardware Keyboard Identification (I). 8-15 
/ ae edo 06044049 Cowen eee PLS 
KEYBOARD PROGRAMMING. .ccsscnsecsncvesenveneavees eal 
Keyboard Layout and Key Identification 8-15 
%)) Wut ee 0s OUR SS DS ORS Orb E We 4 eB OR OY ²˙ eä Oe 
Special Considerations Regarding Auto-Repeat..B-21 
Special Considerations Regarding Down/Up 


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Auto~Repeat CCC . . F 23 
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Keyboard~to-System Module Protocol 
KEyCoce Transm SSloOiias. n. 5 
Special Code Transmission 8-25 
POWEr-"UP TRANS SS ,,,, 8 
system Module-to- Keyboard Protocol... 8-27 
.. NED ORS EMER ORES RSC OUD TES 
PaAkä nete) OWS OR è 28 
Periphere 28 
Mode: Seb. ne,, e esa vaceoe Dead 
special ensiderst ions... oe coho tee ec a5 
EXYOr Hand] iNG ss ꝙ !PU ͤ ͤ 4. we oe ̃ ꝗ³˙·1 ³˙¹¹¹mAͤ ͤ ͤ 35 
Ron Locked en 8edakoce sb 36 
RAS el.,! ONS oe eee EDT OS 
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Sa,, ĩ⁵ð . CADE OT 
CHARACTER. lf¶ĩ] ] 2½]́ /m1)ʒ s ³ AA x 
CHARACTER. SET , ð ͤ y 
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APPENDIX C MOUSE SPECIFICATION 


Cc. 1 GENERAL. DESCRIPTION 644 . 8 4 Ga CF 
rr. ð y eee wea 

1 System HooK U ̃ꝰð²ꝛi..“...;õ M ¶ y MEDS 
a2 Installing/Removing the Mouse Ball 0 


Contents 


ane 


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& 3 * 
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7 


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USING THE 
MOUSE SPECIFICATIONS. 
Signal/Power Cable. 
Spurious Outputs... 
ELECTRICAL N 
Inter face 


ie 


BS 


Bo 


MOUSE OPE 
Serial 


% 
“es 


of Mo ul ey Een 
Self 


Summary 
Power-Up 
Report 
Respons 
PROGRAMMING 
Initiali 
Increment 
2 


Test 


tal Stream 
Button US 
Tablet 


DIGITIZING TABLET 


GENERAL DESCRI 
ELECTRICAL SPEC 
COMMUNICATION SPE 
Serial Interface 
Electrical Sign 
Tablet Position 
TABLET 
ed ane 


PT 
CI 
4 


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4 FI 


2 


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1 
Aae e . 
Self-Tes 
Default Cond 
Report Synch 
Recovery from 
Summary of Dic 
PERFORMANCE SPEC 
CC 
Accuracy 
Spurious Outputs... 
Response Time 
Initializat ion 
ENVIRONMENTAL 


.. 
Bee 


O O 


fe WN 


le 


GLOSSARY 


MOUSE. eee ee: 


Signal Leve 
Power and Voltage Cons 


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Mode. 
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hronizat ion 
Invalid Comman 
gitizing Tabl 
SIFICATIONS 


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SPECIFICATIONS 


° 
ra 
V 
Interface Operation 
Report Forma 
Operating Modes. 

l Commands, 


e % 


„ 
Re poor rr. 
OPERATION AND COMMANDS 


and Ident 
8 
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CONSIDERATIONS.. 
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SPECIFICATION 


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5 
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3 


_Contents 


FIGURES 
Figure No. Title Page 
~ VCB02 Base Module e ̃ 646K E SS ew ew 
— VCB0O02 Base Module, Block Diagrae n 
— VCBO2 4—-Plane Module (M7169)))))) : 1 
— VCB02 4-Plane Module, Block Diadqr ann 1 
— VCB02 Video Subsystem, Block Diagram 1 
— VCB02 Video . 4- Plane Conf iqurat ion. 2 
— VCB02 Video Subsystem 8-Plane Configuration. 2“ 
— a Backplane oon / ð x 
— BAIL23 Backplane ont gars inn 2 
— VCHO2-B Cable ohnen ꝛð 


VSBO02 - Cable Conneet long 33 


2 AJ AP AD 
4 
Dp hme pe | 


VCB02 Connections in a BA123 Enclosure 2 
— Scroll chip Select Load Format — Command 140. 3 
— Scroll Chip Select Load Format - Dwñaa ta 3 
— Update Chip Select Load Format — Command 160H......3- 
— Update Chip Select Load Format ~ Dñ² ata 3 
— Color Map Data. l,. ð 
— O22-BuS 1/0 PAG6 0:08 66 We OOOO STONER ES OOS BORO O™ 
— Q22—-Bus Memory Spacke e 3 
“ Register Mapping. ggg „3 


i 


I/O Page CSR Read VCB02 ID Code Formate... 


WWWWW WW WWW SS rns ie eee Re 
1 gas ri | 

Hee M O- A M PWN OR O8 
S S = HOU RWN 


31 

10 Write Memory Base Register Format 31 
—11 Memory CSR Read Video Readback Register Format....3-l 
-12 Memory CSR Write Format for the Control Write 

Cn ]˙;˙¾]œT Un]... ꝛð! 
3-13 VCB02 Video Subsystem, Block Dñiag ran. 3-14 
3-14 Memory Cycles during one Sens 
3-15 Region Configuration Erampflee 220 
316 Address Processor Chip Data Path 3-28 
3-17 Example of Destination Ras ters 3-29 
3~18 Example of Fast and Slow Vectors that Duplicate 

Pi x SOR OU 
319 Example of Fast and Slow Vectors that Leave 


BOLO S 44 4 a6 OS SWE ] Vüè7gd ði̊i CEA W OA ASEREESO~OL 
Ai Tↄnnn. DEES MS HOO SD 
Video Processor Rasterop, Block Diagram....eeee000 3736 
Text Scaling and Rotation Examples. 3-44 
VOCTOlU . ² ꝗ ↄ ¶ Y ᷣ Seas 
%%% ͤ—ͤf lf 
Bxanple: of ohr ene 6ee 6 saad eee weve ores 
Command Register FOrmatcocsescvacnevessreseveenees dul 
I/D Bus Video Processor Register Load Command 

Formaãſſ . 4377 
328 I/D Bus Z-Axis Video Processor Register Load 


11 


i 


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11 
G 


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open ]²] ] ] ↄ T we 
3-29 I/D Bus External Register Load Command Format.....3-77 
3-30 Rasterop Command Format 3-78 
3-31 Processor-to-Bitmap X-Mode Command Format. 379 
3-32 Bitmap-to-Processor X-Mode Command Format.. 3-80 
3~33 Processor-to- Bitmap Z-Mode Command Format.. 3-81 


xi 


Conte ents — 


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RK 11 


Bi 
Cancel 
Video 
Fo 

Vi 


Processor 
! u ð “ TT ĩðVd OE SS RR 


deo Processor Chip Z-Axis 


VUE 


Command 
Chip Regis 


ter 


Load 


Register 


tmap-to- Processor z-Mode Command Format. 
. P /ͤ ³·o ewes eae wee eo 
Ins 


Load 


INSEFUCTION ena. Reese eae eee 
External Register Load Instruction Format. 


No 


l 


5 Ins 


Write 


Freien FOTMAC ce son eacsews 
(Two Interleaved Instructions) 


one e e +e e * eH ee oH he Oe oe he oe e e hh eh e e KK He He Hh e He HW H 


Read In 
Cycle 
agen for 


DMA Ad. 


Display Li 


JMPT e 


PTB NWORDS 


Number 


CSR 
DMA 
DMA 
DMA 
DMA 


Cursor 
Cursor 


Interrupt Regist 


Memory 


DMA Gate 
te 
Template 
Template 
Template RAM Read, 


DMA Ga 


Register Bi 

Address 
Address 
Byte Counter Regi. ster 3 
Byte Counter 
FIFO Register Bitma 


Ire Ss 


ADDRESS 


of WOLOS) « 46.46 eww BSR OE K 
Other Display List COMMANGS 640 ee eae a Ges 


Counter Register 


Counter Regis 


ap 
X Position Re 
Y Position 
Base Regis 


Array Pin Diagram 


if 


ter 2 
Bitmap..«.. 
Register 4 Bitmap.... 


Tm a 


Bitmap. 
Bitmap. 


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Cyc 1 TIm ng 


Address 
Address 
Address 


Processor 
Processor 


Processor Read, 


Write Cycle Timing... 
Read Cycle Timing.... 


Cycle /// A ³² MA A 


222 - Bus 
922 —- Bus 
22 -Bus 
Q22~Bus 
Video 


VCBO2 


Off-Screen 


Timing, 
Timing, 
Timing, 
e 


Master- Ho- 8 
ee ter DIN 
aster DOUT 


and Vis 


Slave-to-Mas ster 
Cycle 

CY le 
Subs CC 
Multiplane Bitmap Memory Organization 
ible Memory..sseees 


Rasterop Functional Model...... 
Rasterop Operand FO -W. 


. and 


„ . Mapping 


88 
Address 


500 Ende 


Address Translation 


Scrolling Regions. 


Mee a 


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gister Bitmap and Algor 
Register Bitmap..... 
er BItma dd. 

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Array Pin Diagram (Top View). 
(Bottom View) 
RAM Write Cycle Timing. 
RAM Read Cycle Timing 
Address Processor Wri 


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for Memory Read Instruction Format 
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3-163 
» 24-2 
24-3 
04-4 
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. 49 
004-9 
„411 
„411 
~ 4-13 


Contents 


GVVVVVVVVVVVVVVVVVVVVVVVVEETEXEEEXXETXXXXXXXXTTXXX Gauge 


4—11 source 2 Address Computation (Tiling Disabled) 4-13 
4~12 Index Registers for 2-Pixel Down-Scrolling........4-15 
4—13 Address Processor and video Processor chips, 
/ ðV VA... ð eee ee akeee 
4—14 Address Processor Chip Data F Io 4 
4—15 Video Processor Data Flow (Screen Refresh/ 
ö ² ⁰²wm.ꝛ]⁰]¹ ü wae a 0 whe ]ĩ¾Ü6ͥ aa ĩ³»26- wee 
4-16 / h odd ¹ « aa Ae EROS OSE OD 
4~177 Operand Routing eee, x 2 1 
4-18 JJ) ĩÄ et Chee mA ww es 
4—19 / ↄ ↄ ð . ³ꝛ1. . ĩ ⁰˙¹¹ ⁰· eke 
4-20 77. 0 ²²ĩ ⁊ J ee SEs ⁊ͤ K ⁵²sðͤ ͥũm . 


4-2] Pimple RAShCr OD 15 6.424264 daw ewes ews oem Bee coer ou 
4~22 RASPGrOp 00% ⁵ 1508 stands eae welsh es Bese ewer 
4—23 Source Scaled Up by a Factor of TWO oOo 4-31 
4224 Source Scaled Down by a Factor of TWO. 44-32 
4-25 PCs ⁵ ß 3 
4-26 Mapping of Source 2 to bestinat ion 434 
4-27 Simplified Rasterop Modell 4-36 


4~28 J ↄ ²⁵VTTT...... VA ⅛ dv. x 7²ꝛ»˙ ½ aw wks oT 
4—29 POlVGCn. Fill Model 2-5-5204 ͤ ͤh ĩͤ v 
4-30 Bdge Vectors ere, ⅛ 
4~31 IIC ²³ĩ]Ü¹ʃ¹r¹w-A ͤr·ę .ů: t; eov ea eae OO 
4232 Filled Area Continuation Showing Doubl ing.. 4-41 
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437 BI tmap-to- Processor Mapping (General case ꝗ . 4-45 
4-38 Processor~to-Bitmap Mapping 446 
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LK 201 Keyboard Layouũꝶt . 3611 
Audio Transducer (Beeper) Control Circuit. 12 
Indicator (LED) Control Circuit... 813 
Keyboard Transmit and Receive Character Format....B-14 
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Indicator (LED) Parameer!k 38831 
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Audio Volume Par ameter᷑r̃-r 31 
Setting Key Transmission MoOdl!zaerr 8-33 
Setting Auto- Repeat Rate Buffer Association.......B-34 
Setting Auto-Repeat Rate Buffer ValueS...........-B-34 
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Contents 


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TABLES 


Table No. Title Page 


i 


BA23/BA123 Enclosure Workstation Configurations....2-2 
Backplane Slot. ss lannenes?s:?l! 2 
Base Module Switch-Pack settings. 214 
Common Intermodule Connection nns 215 
Intermodule Connections (First 4—-Plane Module) 2-16 
Intermodule Connections (Second 4-Plane Module) 2-17 
Input/Output Interconnect Signals. 217 
Multiplexed MEMAD<10:0> Bits. 3 
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Gate Array Address Dñecod ing 333 
Interrupt Register Vector Bits 02 and 033. 3 
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Bitmap N Addresses „12 
Horizontal Scan Line Pixel Values 5-15 

Color Map Register Green Pixel Value W 

Color Map Register Red Pixel Value Test 5-17 

Color Map Register Blue Pixel Value Test 5-17 

Bus Reset and Reset Defaults 5-21 

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Keyboard Matrix (LKZ OI-AA! )ʒj .. 89 
Keyboard Functional Divisioun. 4. 3-16 
Keycode Translation ahl 
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Special Codes Below 64 (Decimal) ..ccucveeveevneernasb 20 
CONMENG "TYPES es J cei ee ?ũñ ẽ]““) 228 
Peripheral Commands in fexadecin all. 3-30 
Command Function Representation 3-31 
MoGe ere ] ⅛ ðxü 
Keyboard Division Default Modes. 8-37 
Default Rates in Auto- Repeat Buffers . 37 
Multinational Character Set Keyboards. . B-38 
Mouse Connector Pin Assignment s/ Functions . 04 
Mouse Command Summary C7 
Tablet Cable Connector Signal Assiqnmen ts. . 
Summary of Tablet CommandS...ccscecvaneseseseccenessL™ 


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_PREFACE 


This manual provides detailed technical information on the 
features, specifications, configurations, installation, fun ctions, 
logic programming, and diagnostics of the VCB02 video subsystem 

as insta lled in a VAXstation II/GPX workstation system 
environment. It is intended for use by original equipment 
manufacturers (OEMs) and internal/external corporate end-users 


1 
| * 


The manual has five chapters, four appendices, and a glossary. 
ae Chapter 1, General Description, provides an overview of 
the VCBO02 video subsystem's features and specifications. 


® Chapter 2, Configurations and Installation, 5 the 
VCB02 video subsystem implementation in a MicroVAX color 
ae workstation configuration, and includes an 
stallation section. 


ae 


5 Chapter 3, Functional Description, describes the 
functional characteristics of major logic elements in 
VCB02 video subsystem — the address processor and vid 
processor chips, timing generator, bitmap memory, leis ga 
array (CMOS), template RAM, keyboard/mouse/ table 
circuitry, Q22-Bus interface, and video output path 


8 


. Chapter 4, Programming Information, describes how common 
drawing operations (for example, text, graphics, 
functions, and windowing) are implemented on the VCBO2 
video subsystem. Examples are included wherever needed. 
VCBO 2 drawing modes, DMA use and program input 
(mouse/tablet support) are also examined. 


@ Chapter 5, Diagnostics, describes the diagnostic programs 
that apply to VCB02 video subsystem fault is solation, and 
includes a summary of error types, indicator locations, 
display messages, anc suggested remedial actions. 


85 Appendix A, Q22-Bus Specification, oo. the Q22-Bus, 
which interfaces the VCB02 video subsystem 


* Appendix B, LK201 Keyboard Specification, describes the 
device's characteristics, and its programmable functi 


Preface 


c CCC 


RELATED 


Appendix Cc, Mouse Specification, describes the 
characteristics of the supplied 3-button circular mouse. 


Appendix D, Digitizing Tablet Specification, describes the 
characteristics of the optional, ll-inch square, 
digitizing tablet, which comes with a 2-button stylus and 
4 button puck, 


The Glossary defines many important terms used in this 
manual. 


DOCUMENTATION 


For a list of related documentation, see Appendix 2 of either the 
VAXstation II/GPX Owner’s Manual, BA123 Enclosure (EK-105AA-OM), 


or the 


(EK-106: 


xViii 


VAXstation II/GPX Owner’s Manual, BA23 Enclosure 


AA-OM) . 


CHAPTER 1 
GENERAL DESCRIPTION 


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1.1 INTRODUCTION 

The VCB02 video subsystem consists of a base module and one or two 
4~plane modules. These provide a high-performance, 
high-resolution, full-page DMA color video subsystem based on the 
Q22-Bus. This raster scan video subsystem is capable of 4— or 
8-plane color video memory display on a MicroVAX workstation. Both 
MicroVMS and ULTRIX-32w operating system support is provided. 

The MicroVAX workstation is a single-user, stand-alone, 32-bit 
workstation. A standard system includes three megabytes of memory, 
a 19—inch color or monochrome monitor, a mouse, a keyboard, a 
loading device, anda fixed disk drive. Each of the two versions 
of the MicroVAX workstation (BA23 and BA123 enclosures) includes a 
VCBO02 video subsystem of either 2 modules (4-plane) or 3 modules 
(8-plane). The 8-plane subsystem provides 1024 (horizontal) X 864 
(vertical) pixel resolution of displayed graphics and text. The 
2~module, 4- plane VCBO2 video subsystem allows simultaneous 
displays of up to 16 colors or shades of gray; the 3-module, 
8-plane subsystem allows up to 256. 


The base module and 4-plane module communicate through a cabling 
scheme to provide a basic configuration of 4-planes (16 colors 
from a palette of 16.7 million), with an upgrade path to 8-planes 
(256 colors from a palette of 16.7 million). 


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Figure 1-2 is a block diagram of the base module's major hardware 
components: 


= 


Address processor (DC323) chip 

DMA gate array 

Template RAM for display list and cursor support 
Q22~Bus interface transceivers 

Serial I/O bus and address interface 

Console emulation/diagnostic ROM 

Subsystem timing generator 

Color bitmap 8-plane video output path 
Digital-to-analog (D/A) converters 

Video shifter and cursor multiplexer 

Cable connector for I/O interface and memory upgrade 
Communications input (keyboard/mouse/tablet) 


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Figure 1-2 VCBO02 Base Module, Block Diagram 


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General De cription 


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The 4-plane module (M7168) shown in Figure 1-3 provides the 
hardware for 4-planes of full-page video memory, which is 
connected to the base module by a 50-pin ribbon cable. Two 
versions of this cable allow the base module to be connected to 
one or two 4-pla odules for a 4-plane or 8-plane color MicroVAX 


1.3 FOUR- PLANE MODULE 
2 
1 


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Figure 1-3 VCB02 4-Plane Module (M7168) 


General Description 


UR 


workstation. Figure 1-4 is a block diagram of the 4-plane module's 
major hardware components: 


Four video processor (DC322) chips 

4- planes of video memory (2 pages per plane) 
Subsystem support logic 

Video shifter 

Cable connector for base module interface 


8 


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Figure 1-4 VCB02 4-Plane Module, Block Diagram 


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General Description 


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1. 
The veBo2 video . em contains the following operational 
elements, shown in Figure Loe 


ss Processor Responsible for functions common to 

ip (DC323) planes, such as: local processor 
interaction, all rasterop computations, 
bitmap address generation, clippinc 
screen refresh, scroll control, 
monitor synchronization generation 
address processor chip „ 
bitmap address bus ( 
addresses for screen refre an 
and updates), and the instruction/date 
(I/D) interconnect to „ and 
control the video process i 


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® Video Processor Provides the 3 path and control 
Chip (DC322) elements uniqu to each 1 such 

data FIFOs 5 refresh and scrolli 
barrel shifter for bit alignment, a 
unit with data and mask registers 
memory modification, Z-axis adc 
logic, and a control store RAM to 
video processor chip operations 1 
rasterops. The video processor chips are 
controlled by the I/D eee 
exchange data with the bitmap memories on 
the memory bus, and provide screen 
refresh data on the video output bus 


® Bitmap Memory Each plane consists of 1 KxX1K X 2 
pixels. This allows both on- screen and 
off-screen drawing to occur. 


® Video Output Provide a color map, video shift 
circuits, registers, and digital-to- 
analog converters for driving the 
monitor. 


a Timing Circuits Provide required system and memory 
cl oc ks te 


General Description 


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Figure 1-5 VCB02 Video Subsystem, Block Diagram 


daumen ed 


General Description 


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„ Multiplane Support 

The VCB02 video subsystem uses the multiple video processor chips 
and bitmap memories to provide multiple memory planes for color, 
without any performance penalty for additional planes. It also has 
several other provisions to support manipulation of multiple 
planes. 


1. A chip select mechanism controls which video processor 
chips (planes) will participate in bitmap update 
operations; a related mechanism controls participation in 
scrolling. 


2. Z-axis (color variation) data transfers are provided to 
allow data to be exchanged between the MicroVAX CPU and 
the bitmap on the basis of a color value for each pixel, 
rather than exchanging the data for each plane separately. 
This form of data transfer can also be sed to 
Simultaneously load the color registers in all video 
processor chips. Z-axis transfers accommodate the use of 
low-resolution planes. 


Leone Viewport Support 

The VCBO Z video subsystem provides scrolling and clipping support 
for rectangular viewports. Scrolling is coupled to screen refresh, 
and moves all the data in an arbitrary rectangle (limited to 4 
pixel boundaries, horizontally) up, down, left, or right by 1 to 
15 pixels (or more) in a single frame time. The incoming edge of 
the scrolled region is filled with a programmable color; or, a 
mode is available that clears the entire region to a color. 


Scrolling uses memory cycles that would otherwise be available for 
updating the bitmap. Therefore, the speed of rasterops drops to 


about one-third of its nonscrolling value when the whole screen is 
being scrolled. Down-scrolling actually moves the entire 
nonscrolling image (outside the scrolling rectangle) up, 


offsetting the entire screen to compensate. When down-scrolling of 
any region is in progress, rasterops are slowed to one-third 
speed, as if the whole screen were scrolling. 


Clipping prevents updates from writing outside an arbitrary 
rectangle (same horizontal limitation as above, pending pass 3. 
address processor results). This rectangle may be the same as, or 
different from, the scrolling rectangle. Updates may occur 
concurrently with scrolling. This is facilitated by the addition 
of an index value to all update addresses. Indexes are changed 
with scrolling to represent where data has moved in the bitmap, 
which allows new updates to follow the scrolling image already in 
the bitmap. 


General Description 


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7 upda he the bitmap memory are performed by basic sterops 
or variou special rasterop modes. During rasterops, ce. address 
processor Shae provides all memory address calculation, and the 
ideo processor chips provide all data modification. If no 
ling, rotation, or reflection of t 
rce is required in a rasterop, the VCB02 video subsystem 
omatically operates in fast mode. In fast mode, multiple pixels 
ng the X-axis are operated on simultaneously. Otherwise, the 
92 video subsystem able in ey mode, processing only one 
pixel at 3 time. Fas mode operates 16 times faster than slow 


-he horizontal axis of the 


1 Programmable Modes — Processor/bitmap transfers (not 
ally modes, | commands) transfer images between the MicroVAX 
CPU bus and the bitmap. These transfers work very much like 
rasterops, except that there is either a source or a destination 
in the bitmap, not both. Also, the data transferred to/from the 
MicroVAX CPU bus is a stream of words through a read/write 1/0 
register the MicroVAX CPU or DMA may access. There are two 
transfer modes: 


‘ie 


e plane, with the adjacent 

representing 9 pixels in the X-axis. 

This type of transfer always operates in fast mode. Full 

indexing and shifting are available when transferring from 

pins bitmap. But, when data is transferred to the bitmap 

the MicroVAX CPU bus, the data must already be 

gned with bitmap memory words because there is no 
‘ter in the address processor chip. 


1. X-mode transfers each Hane (size depends on the memory 
configuration) to/from a singl é 
bits in a word 
£ 


2. Zz-mode (color variation) transfers each word containing 
the bits representing the color of each pixel to/from the 
bitmap. This type of transfer always operates in slow 
mode, but writes all planes at the same time. Indexing is 
always available in this mode. 

Lede owe Video Processor Data Manipulation —— The video processor 

chips contain the data path for each plane of the bitmap. During 

source reads from the bitmap, a shifter aligns the data with the 

.xels _in the destination. This shifter is controlled 

tomatically by the address processor chip. Data that is read 

iring source reads may be broadcast to other video processor 
jips or the address processor chip on the I/D interconnect (one 
deo 5 may broadcast), or may be retained in the video 

‘ocessor chip. 


processor chip or received from the I/D 
2d in any of three registers for use 
2, The source register provides 1 input 

16 ion 185 unit; the other input is the old 
nation. ‘data. The e of the logic unit selects, on a 
r-pixel basis, a foreground or background color to form 
tination data. The new destination data is masked by the 


2 


General Description 


CCC nene 


combined outputs of the two mask registers, which, like the source 
register, are loaded with a constant or during a source read. 
Masked bits return the old destination data instead of the new 
data to the bitmap. Either of the masks can be complemented, and 
the combined outputs adjusted so that only complete groups of bits 
are changed in low-resolution planes. A complementer and 
resolution logic are available for the source register. 


Data manipulations are controlled by two sets of indirect 
registers that are selectable from the address processor chip. The 
control store RAM specifies the data transfers that occur on each 
Source or destination cycle. Four logic function registers specify 
the Logic and mask operation to be performed during the 
destination cycle. Having four function registers allows two 
orthogonal functions to be preprogrammed in the video processor 
chips. 


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3 Performance —— Destination-only and single-so 
stination rasterops are compute- bound at 1 cycle every 2 
cycle writes 1 pixel in slow mode, or 1 word (16 bits) i 
mode. Therefore, 500 K pixels/s are written in slow mode ar 
pixels/s are written in fast mode. 


1.5.4 Private Memory 

To achieve rasterop performance, parallel multiplane operation, 
and to support scrolling, the bit-mapped memory operated upon by 
the VCB02 video subsystem must be on a private bus accessible to 
the processor only through the chip set. In the VCB02 video 
Subsystem address space, as much off-screen memory as displayable 
memory is provided in each plane to support occluding viewports. 
With DMA~assisted processor-to-bitmap and bitmap-to-processor 
transfers in either X- or Z~mode, the need for direct processor 
access to the bitmap is diminished. 


Le SD MicroVAX CPU-to-Address/Video Processor Chip Interface 
The MicroVAX CPU controls the address/video processor chips 
through the MicroVAX CPU bus on the address processor chip. This 
bus consists of 16 bidirectional data lines, 6 address lines, and 
some control lines. The address processor chip has 58 registers 
(mostly write-only) that can be accessed directly by the MicroVAX 
CPU. Alternatively, the registers can be loaded through an 
indirect register address counter. Address processor chip 
registers are manipulated directly. The following operations are 
also provided. 


1. Video processor chip registers are loaded with explicit 
I/D interconnect instructions. The chip select register 
must be loaded to select the video processor chips that 
are to receive the data; this register is the I/D 
interconnect. 


2. To invoke a rasterop, the MicroVAX CPU loads the required 
video processor and address processor chip registers 
(unless unchanged by previous use), and starts the update 
with a rasterop command. 


General Description 


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SE 


3. Processor/bitmap transfers are similar to rasterops, 
except that the data is sent to or accepted from the 
address processor chip. 


4. The cancel command terminates any update operation in 
progress and clears all rasterop status. 


wi 


. Scrolling is started by loading the address processor chip 
scroll constant register. All address processor and video 
processor scroll parameter registers must have been 
previously loaded. Separate I/D command, data and chip 
select registers are provided for loading scroll 
parameters into the video processor chips without 
disturbing any update that might be in progress. 


A status register reports the progress of various processes in the 
address processor chip. Any or all of the status bits can be 
enabled to generate a request on either of two pins. (One pin is 
reserved for DMA requests, the second is used for interrupts.) 
Scroll status provides a top-of-frame flag to load scroll 
parameters, a programmable flag that will be set when the 
refresh/scroll process passes any point on the screen to 
synchronize region updates, and a bottom-of-frame flag to start 
any vertical blank activities. Rasterop and I/D status indicates 
when various parameters and data may be loaded to minimize 
waiting. Clipping status reports when some rasterops are clipped 
or not clipped. 


1 Address Processor Chip Registers — The following are 
control, scroll, rasterop, and configuration registers of the 
address processor chip. 


CONTROL REGISTERS 


Address Counter Indirect access to address processor 
registers used during DMA 


Status Readable scroll, rasterop, I/D, and 
clipping status 


Request Enable Status bit masks for interrupt outputs 
Interrupt Enable 


I/D Data Data transfer register 
Command Update command register 
SCROLL REGISTERS 


Most of the scroll parameter registers are double~buffered to 
allow a whole frame time to load new scroll data. 


Scroll X Min 
Scroll X Max 
Scroll x Min 
Scroll Y Max 


Pause 


Y Scroll Constant 
E Offset 


I/D Scroll Data 
I/D Scroll Command 


RASTEROP REGISTERS 


Pending X Index 
Pending Y Index 
New X Index 
New Y Index 
Old X Index 
Old Y Index 


Clip X Min 
Clip X Max 
Clip 1 Min 
Clip Y Max 


Mode 


Fast Source 1 DX 
Slow Source 1 DY 


Source IX Origin 
Source 1 Origin 


Destination X Origin 
Destination Y Origin 


Fast Destination DX 
Fast Destination DY 
Slow Destination Dx 
Slow Destination DY 


Fast Scale 
Slow Scale 


Source 2 X Origin 
Source 2 Y Origin 


source 2 Height and 
Width 


Error 1 
Error 2 


General Description 


scroll region boundaries 


Programmable frame position status return 


Vertical scroll control 


I/D path for scroll control 


Index values for update control while 
scrolling 


Update region boundaries 


Rasterop mode control 


Source 1 rectangular extent 


Source 1 origin 


Destination origin 


Destination parallelogram extent 


Source 1 destination scale factors 


Source 2 origin 


source 2 rectangular extent (powers of 2 
only) 


Optional error control for vector 
generators 


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CONFIGURATION REGISTERS 


General Description 


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1.6 APP 


LICATIONS 
The following applications provide examples of implementing common 
drawing operations using the VCB02 video subsystem. 


Normal rasterops are used to write characters. Common text 
procedures are described below. 


1.6.1.1 Font Storage and Access -~ Fonts are 
undisplayed portion of the bitmap. Ordinarily, a fo 
only in one plane and is transmitted from that oie 
others when a character is written. This result ) 7 8 
that appear in one (foreground) color written on a background of 
another color, as is normally . TE V or 
gray-scale characters (for anti- he f 
can be stored across many planes. 
off-screen portion of the VCBO2 bi 


4.2 Normal Text -- A display of 5 
fixed-pitch text might use the following s i 
address „ sor and video processor chips. 1. thos 

1ally changing between characters need to be upc 
alization. 


ings 


1. The 5 region is initié 
indexes, and resolution mode. 


„ The video processor chi 
enable broadcast of the 
containing the font to all 


p control store RAMs 
character data from 
other planes. 


K chip mode register and the v ee 


3. The address process 
processor chip logic 
are set for some of 


O 


unctions, foreground, and backgrou 
2 desired character attributes, 


0 
7 
th 
urce 1 origin (& and Y) is set to the start of the 
irae 5 to be transferred. 


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See 
. 
— 
2 hw 
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8 
e 
— 


5. The destinat 
screen locat 
edge vectors 


(Xx and 1) is set to the ired 
irst character, The destination 
lel to the X and Y axes. 


ct c 


£ 
re set ae 


nr 
. 


The scale registers are set for scale factors of 1. 


General Description 


scion ta A a iSO ea SINC REO RAND GeO ß eT ein ia SN NN NAA 


lowing operations can now be performed to write each 
r in a string. 


1. The MicroVAX CPU loads the command register in tl r 
processor chip to start a source 1/ destination rasterop. 


bee 


for the address processor chip to finish the 
4 3 n phase of the rasterop (but while the 
acter still being written), the local processor can 
ad the source and destination origins and the command 
a that the next character can start immediately upon 
completion of the first. 


aiting 
10 


a 


„ After w i 
initializat 
ale 1 

210 


15 
ent 
wa 


3 0 T h 1 oe Ci Ce ce e 1 


pr 8 e until the text is exhausted or an 
attribute change is 


required. 


Ac ing the destination po ition (and possibly width) produces 
variable-pitch text (p roporti a spacing). 


1.6.1.3 Character Attributes -~ To set the character attributes, 

appropriate address processor and video processor chip registers 

are loaded. Only the registers for those attributes that actually 
change between strings need to be loaded. The following list 
describes the intended implementation of attributes. 

1. Reverse — Reverse is a specific case of a more general 
class of attributes that modifies the logic function 
being performed on the destination data. Two bits are 
provided in the address processor chip command word to 
address one of the four logic unit function registers in 
the video processor chips. 


= 


Underline — Underlines can be drawn as a vector of the 
desired thickness, and linear pattern mode can be used if 
a dashed or other patterned underline is desired. 


33 e 
(0 not 
U 


ke — Overstrike may be accomplished by loa 
5E 5 
ee £ 


ding 

loading) the destination origin and the use of OR 

netions. 

4. Invisible -- The pen up bit in the address processor chip 
mode register may be used to disable writing; otherwise, 
the MicroVAX CPU omits text strings that are invisible. If 
erasure of the nvisible area is desired, this must be 
performed explici 


ption 


General Descri 


5. Intensity, Color, and Blink — These are Z-axis (color 
variation) parameters implemented through the color map. 
To enable writing the appropriate color in the bitmap 
planes, a Z-axis load of the video processor chip 
foreground and/or background registers would be performed. 
Source data would then be passed through a video processor 
chip mask register to accomplish overstrike writing, or 
through the source register to accomplish replace mode 
writing. Otherwise, blink is performed by periodic writing 
to the bitmap. 


6. Subscript and Superscript -- These character offsets are 
obtained by appropriate loading of the destination origin 
registers. 


7. Size, Italics, and Rotation — Any size, italic slope, or 
rotation is available by setting the destination edge 
vectors and the scale factors, and providing appropriate 
destination origin update. 


1458982 Graphics 
Most graphics functions use basic rasterops. Linear patterns, 
polygon fill and flood use the additional rasterop modes. 


1.6.2.1 Vectors — Solid color vectors are plotted as specific 
parallelograms, without any source operations. The 


foreground/background registers in the video processor chips are 
loaded with constants according to the desired color. The start 
point is loaded into the destination origin registers; one edge 
vector is set to the DX and DY of the desired vector; the other 
edge vector is set to the width of the desired vector (and 
perpendicular to the first edge); and the rasterop command is 
loaded. Curves must be formed from a string of straight vectors or 
points. 


Vectors may be shaded in one of two ways: 


1. Inclusion of a first source set for linear pattern mode 
provides linear patterns (like dashed lines, bullets, or 
Stripes) that align themselves with the direction of a 
vector. 


2. Inclusion of a second source set for tile mode provides 
tile patterns that are “uncovered" under the path of the 
vector. 


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address 
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General 


ee ee 


1.6.2.3 Polygon Flood — In contrast to a fill operation, a flood 
operation colors or textures the interior of an area. The address 
processor chip provides no explicit support for a polygon flood 
function. This function requires the path of writing in the bitmap 
to be conditional on the previous contents of the ee In the 
hardware, the path of writing is controlled by address 
processor chip, but only the video processor: chi Rive 
memory data. A flood operation is implemented in 
way. 


ips 

the 

1. The local processor/bitmap transfer facility reads a scan 
of the bitmap. 


2. Each returned pixel value is checked for a match again 
set of boundary colors, and a count is maintained of 
pixels received. 


ai 
aioe 
Sea 


3. Each time a match is found, the processor/bitmap transfe 
is terminated by a cancel command to the address processc 
chip. 

t 


4. A vector s the desired pixels on the scan with a 


rite 
color or mre ern. 


can 


* 
se 


The flood algorithm then eae to a 
51 


point on the next s 
or continues at a previous seed point 


hts 
1.6.2.4 Objects — oe ety rasterops can be used to move 
objects or windows on the screen. In a multiplane environment, 
rectangles can be copied by moving the pixels in all planes, in 
parallel, to new locations in the same planes. 


To move a simple object, that is, to alter only the de 

pixels within the boundary of the object, the hardware 
distinguishes between the object and the background. This can be 
done by defining the foreground of the object in one plane This 
area is then transmitted to the other planes during the raster rop 
as a mask that prevents the alteration of background pixels. 
Otherwise, the second source (with fill mode, if desired) can be 
used to copy the object from off screen, with clipping to the 
destination shape. 


destination 


＋ 


ts (ones specified 
lor to them at the 
imilar to that for 


only by a foreground shape), and assign ac 
time they are moved. This type of operation is 
the writing of text. 


It is also possible to move monochromatic objec 
co 
8 


ie 


CHAPTER 2 
CONFIGURATIONS AND INSTALLATION 


siete RN RRR RHO 


iii aE Re NNN 


Zel GENERAL 
This chapter describes the configuration and installation of the 
VCBO2 video subsystem in a MicroVAX workstation. With the a 
subsystem, the workstation can display graphics and text wi 
(horizontal) X 864 (vertical) pixel resolution on 
monitor in color or shades of gray. The VCBO2 video 
consists of two modules: the base module and the ‘plane 
shown interconnected in Figure 2-1. The open-end modular 
the VCBO02 subsystem allows expansion to an 8-plane video 
with the addition of another 4-plane module, as shown 
2-2. 


50. RE CABL LE 


20-WIRE CABLE 
4 COLOR | 


Figure 2-1 VCB02 Video Subsystem 4-Plane Configuration 


ety 


50. o WIE CABLE COMM OUT 


ee enen nbi dureh 


ie sas ee wrden A NURS 


beet 


A- PLANE MODULE 


B02 BASE MODULE 

ADDRESS CHIP 

2, DMA GATE ARRAY 
(CMOS) 

3. TEMPLATE RAM 

4. CO LOR MAP 


cS neden ole 


50 WIRE CABLE 


ARO eee uh wn hem meme 


SP AKORRAOIDLERARTHEMONINONNIERNINRI, 


20-W!RE CABLE 


AERIS TASB HRD ARI TROLS OU HE SN UR SRN 


Figure 2-2 VCB02 Video Subsystem 8~Plane 


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Slot Module Des eC PELOn. Rows 


Configurations and Installation 


ad 


25251 * e 
Table 2-2 lists the backplane slot assignments for the system 
modules of 9 9 bie BA23 and BA123 enclosures. 


acer deen, sega edi ue ebene, tS OUSIDE SS SSCL EATEN IAHR 


en aue . e ATI IS CORRES en 


4 17606 AA MicroVAX II CPU ~ (KA630- AA) A~D 
2 M7608-AA 2 Mbyte Memory (M5630-BA) A~D Quad 
3 M9047 Grant card A~B Dual 
4 M7504 DEONA Ethernet interface A-B Dual 
5 M7169 VCBO02 base module (see Note 3) A~D Quad 


6 M7168 VCB02 4-plane module (see Note 


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le (see Note 3) A- Quad 


8 M7513 RODX3 disk controller =D Dual 


— . e p e REI SHINN cance 


Lae 


„„ notes apply equally to the BA23 and BA123 
a 1 e de . 


— 
— 
9 9 


1. KA630-AA — The quad-height KA630-AA (MicroVAX II with FPU ane 
1 Mbyte of memory) module must be insté ile din the first 0 
of the backplane. The A-B rows of this slot are connect 

the O22-Bus, its C- rows are 5 to the CD 

interconnect. 


„ MS630-BA — The quad-height MS630-BA (2 Mbyte memory) module 
requires a full slot in the backplane. The slot must have the 
CD interconnect available and be adjacent to the MicroVAX CPU, 
which limits the memory module to slot 2. 


VCB02 — The video subsystem modules can be installed 
of slots 5 through 8, but occupy adjacent slots because of 
intermodule cable length. 


2 


4. RODX3 -- The dual-height RQDX3 interface module must be 
nstalled in a Q22-Bus slot in the backplane. 


Configurations and Installation 


a ae ee 


ROO 


2.2.1.1 BA23 Enclosure — The BA23 enclosure Supports the 4-plane 
monochrome color graphics MicroVAX workstation. It has the 
Following components. 


6 


230 W power supply 

8-slot backplane 

) l or 2 5. 25-inch storage units 

e Rear I/O distribution panel 

a Front control panel and assembly 


The 8~slot BA23 backplane is configured as shown in Figure 2-3. 
(See also the notes to Table 2-2.) 


1.2 BA123 Enclosure — The BA123 enclosure supports the 4- or 
ane monochrome/color graphics MicroVAX workstation. It has the 
following components. 


460 W power sup 
L2-slot backplan 
Up to 4 5.25-i 
Rear I/O distri 
Front control ned 


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The 12~slot BA12: 


„ is configured as shown in Figure 2-4, 
(See also the note 


to Table 2-2.) 


2.2.1.3 KA630-AA CPU Module — The quad-heigh 
module has the following components and functions. 


. 
2 
if 
i a as 
— 
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® MicroVAX II processor chip 

a Floating Point Unit chip 

. Q22-Bus interface (See Appendix A.) 
0 222 - Bus map for DMA transfers 

® 1 Mbyte of on-board memory 


® Addresses up to 16 megabytes of physical memory 


a 64~Kbyte boot PROM 


. 10 ms interval timer interrupts enabled by the internal 
processor register 


The KA630-AA module supports the following subset of the VAX data 
types: byte, word, longword, quadword, character string, and 
variable-length bit field The floating point unit supports 
FEloating, dfloating, and gfloating. Support for the remaining VAX 
data types can be provided via macrocode emulation. 


2-4 


Configurations and Installation 


MMC TTT MZ MAMMA p NN TENN een tise 


si RE 


8-SLOT BACKPLANE 


M7606-AA (KA630-AA) | } SLOT1 
M7608-AA (MS630-BA} } slore 


nee 


EMPTY | mg047GRANT | SLOTS 


° 4 re as ee 
_M9047 GRANT | ™M7504DEQNA_ | SLOT 4 


"M7169 VCBO2 BASE MODULE | SLOTS 


M 70 68 vc 802 4 PLANE MODUL E SLOT 6 


ais iis a i i CCC 


7513 RQDX3 | EMPTY Stor? 


| | sLoTs 
MR-16456 


Figure 2-3 BA23 Backplane Configuration 


12-SLOT BACKPLANE 


c | B i A 


i 
oe 


M7606-AA (KA630-AA) | SLOT 1 


M7608-AA 3 BA) | SLOT 2 


e OTA 


EMPTY 


— 


EMPTY 


RE 


M9047 G RANT SLOT 3 


| “M7504 DEQNA stor 4 
"17169 VCBO2. BASE MODULE |} SLOTS 

ae enone once —— 

M7168 VCBO2 4. PLANE MODULE SLOT 6 


M7168 VCBO2 5 PLANE MODULE SLOT 7 


us RODx3 9 EMPTY | stor s 


—— —_ SLOT 9 
N o = SLOT 10 
CW 1 SLOT 11 
—_— | | SLOT 12 


M9058 | RESERVED | stot 13 


RP A? 


Figure 2-4 BA123 Backplane Configuration 


Configurations and Installation 


oss NNR US SUC LLL LLL NLL r ASRS AASVSA AAAS AAAI ADDERS N NANA AANA NSS NNN SN estan eewneenienanoNaSNeNNi 


The KA630-AA module implements the Following subset of the VAX 
instruction set: integer and logical, address, variable-length bit 
field, control, procedure call, miscellaneous, queue, MOVC3/MOVC5, 


e 


1 


and operating system support. Floating point is implemented with 
an optional floating point chip. The remaining VAX instructions 
are implemented via macrocode emulation. (The MicroVAX CPU chip 
provides microcode assists for the emulation of the character 
ee decimal string, EDITPC and CRC instructions.) The KA63O AA 

dule also provides a demand paged memory management unit that is 
fully compatible with VAX memory management. 


MS630 Memory Expansion Module -- The MS630 series of 


ory modules use the loca 1 memory interconnect, which consists 
the CD interconnect and a cable, to create a direct path with 
the MicroVAX II CPU. This allows much faster memory access because 
the memory responds 
routing through the 


3 directly to the MicroVAX CPU instead o 
922— BUS. 


trol and self-identifi 
Jules are en Tf 0 
occupy the next slot 
tired). A second MS630 
ete For detailed 5 
ation IT/GPX Technical ‘Manual, ' 


module are used in various 


ver sion Storage Module Height Module No. 


1.5 VCB0 2 Video Subsystem — The VCB02 video subsystem is 
ilable in two versions: A-plane and 8-plane. Both versions are 
ble of — and color operation. The BAZ 3 enclosure 
tation system supports the 4- plane VCBOZ video subsystem, 

the BA123 8 re workstation system supports both the 4 
and 8-plane versions. Each video subsystem Supports two RS232 
serial ports. The LK20 
VSXXX~AA mouse or the opt 
other. 


keyboard uses one port, and either the 


1 
lonal VSXXX-AB digitizing tablet uses the 


The VCBO2-B module se 
4-plane module (two « 
cable, used for colo 
VR290 color monitor. The 
operation, connects the enclo 


et option comprises a base module and a 
quad- height modules total) The BC182Z2—10 
r operation, connects the enclosure to the 

BC18P-10 cable, used for qray- shade 
Sure to the VR260 monochrome monitor. 


Configurations and Insta 11ation 


c DONE iii innit iene anit seaicAaii Mop 


ac e 


The VCBO02-C module set option comprises a base module and two 
4-plane modules (three quad-height modules total). The BC18Z-10 
cable, used for color operation, connects the enclosure to the 
VR290 color monitor. The BC18P-10 cable, used for gray~shade 
operation, connects the enclosure to the VR260 monochrome monitor. 


VCB02 Video Interfaces 

The VCBO2 subsystems are Q22-Bus options. Performance is enhanced 
by the use of the VCBO2 DMA gate array, which allows data to be 
transferred quickly between the host system and the VCBO2 bitmap. 


. Base Module The VCBO2 base module supports the 
system/user interface and either 4 or 
8 planes of full-page video memory. 


* 4-Plane Module The VCBO 2 4- plane module supports 4 
planes of video memory connected to the 
base module through a 50-pin ribbon 
cable. Two versions of this cable allow 
the base module to be connected to one or 
two 4-plane modules for 4- or 8-plane 
color systems. A separate 20-pin cable is 
used for control signals between’ the 
4-plane module and the base module. 


ae 2.1.6 Mass Storage -- The following mass storage devices can be 
used in configuring the color graphics workstation system. 


2 RODX3 Controller The dual-height RODX3 controller module 
is the inter face to the RX diskette and 
RD Winchester disk drives. It is a direct 
memory access (DMA) interface and uses 
mass storage control protocol (MSCP). 


2 RX50-M Diskett The RX50-M dual diskette drive uses 
5 5. 25-inch diskettes. Each diskette can 
store 400 Kbytes of data. For more 

information, refer to the VAXstat: 

LI/ GPX Technical Manual, BA123_ Enc slosure 


ee meld se spe 


(AZ-GNFAA-MN) . 


« RD53 Fixed Disk The RD53 Winchester fixed disk drive 
Drive contains a 5.25-inch disk with a 71 Mbyte 
formatted capacity. For more information, 

refer to the VAXstation II/GPX Technical 


a noe. 


Manual, BA123 Enclosure (RZ -~GNFAA-MN) . 


* TK50 Tape Drive The TK50 streaming tape subsystem uses 
tape cartridges, each with a formatted 
capacity of approximately 100 Mbytes. 


Configurations and Installation 


NANAK 


iii iS ai oii io iba OE nH SNARES ROHR DAU TN OFAN OU 


2.2.1.7 Ethernet Controller (DEONA) Module — The dual- height 
DEQNA module is the interface between the print station and the 
Ethernet network. It allows data packets (ranging from 46 to 1500 
bytes) to be transferred over the Ethernet network at a rate of 10 
Mbytes/s. 


2.2.1.8 Monitors — Two types of system monitors are offered with 
MicroVAX workstations: 


0 VR260 Monochrome The VR260 monitor measures 19 inches 
Monitor diagonally. It is capable of displaying 
1024 (horizontal) X 864 (vertical) pixels 
on its screen. The monochrome video BNC 
input is connected to the BA23 enclosure 
by the BC18P-10 monochrome cable. The 
monitor is a 100-120/220-240 V, 50/60 Hz 
ac unit, and uses less than 65 W of 
power. 


0 VR 290 Color Monitor The VR290 monitor measures 19 inches 
diagonally. It is capable of displaying 
1024 (horizontal) X 864 (vertical) pixels 
on its screen. The red, green, and blue 
BNC inputs are connected to the BA123 
enclosure by the BC18Z~-10 color cable. 
The monitor is a 100-120/220-240 V, 50/60 
Hz ac unit, and uses less than 150 W of 
power. 


2.2.1.9 Monitor Cables -~ Two cables are used in configuring the 
two versions of the MicroVAX workstations: 


6 BA23 Enclosure —— The BC18P-10 monochrome video monitor 
cable, 3m (10 ft) long, connects the enclosure to the 
VR260 monochrome monitor. 


. BA123 Enclosure — The BC18Z-10 color video monitor cable, 
3m (10 ft) long, connects the enclosure to the VR290 color 
moni tor. 


2.2. 1. 10 LK201 Keyboard — The LK201 keyboard uses the ful l-duplex 
RS 232 serial port on the VCBO2 option. The keyboard's 105 keys are 
divided into four groupings: normal typing keys, editing keys, a 
numeric keypad, and special function keys. The keyboard also has a 
small speaker, four light-emitting diodes (LEDs), and associated 
electronic circuitry. A 1.9 m (6 ft) coiled cable connects the 
keyboard to a dedicated 4-pin MICRO-DIN connector on the monitor's 
rear panel. Refer to Appendix B for keyboard specifications. 


2. 2. 1.11 Mouse —— The VSXXX-AA 3-button circular mouse is a 
hand-held, ergonomically designed input device connected to the 
monitor by a 1.5 m (5 ft) cable. The mouse's signals are passed to 
the RS232 serial port on the VCBO2 base module for display on the 
monitor's screen. Refer to Appendix C for mouse specifications. 


Configurations and Installa on 


ß . iN i Cia 


in 


2.2. 2 Options 


2.2.2.1 Additional Memory — You can add additional memory to the 
system by using a combination of the MS630 series of memory option 
modules. The MS630-AA, -BA, and —BB modules offer 1 Mbyte, 2 
Mbytes, and 4 Mbytes of memory, respectively. 


2. 2. 2. 2 Optional Tape Storage — The TK50 streaming tape drive 
allows use of tape cartridges, each with a capacity of 100 Mbytes, 
to be used in MicroVAX workstation systems. In the BA23 enclosure 
workstation, the TK50 tape drive can be substituted for the RX50 
diskette drive, with Digital's software/diagnostics available to 
support the system. The BA123 enclosure workstation accepts the 
TK50 tape drive in addition to the RX50 diskette drive, allowing 
the system to use both methods of removable media. 


2.2. 2. 3 Digitizing Tablet —— The SXXX-AB digitizing tablet 
option consists of a 27.5 cm (11 in) square panier. a 4~button 
puck, and a 2-button stylus. The tablet is connected by its 1.5 m 
(5 ft) power/signal cable to the monitor's R5232 serial port, 
replacing the mouse's cable connection. Refer to Appendix D for 
tablet specifications. 


2.2.2. 4 Printers — Three printers are offered as options for 
MicroVAX workstations: 


® LA50 -- 50 character/s impact printer 
a LA210 — 100 character/s impact printer 
& LNO3-AA — 333 character/s (8 page/min) laser printer. 


Refer to the VAXstation II/GPX Technical Manual, BA123 Er 


(AZ-GNFAA-MN) for ~configuration/interfacing Procedures 
printers. 


closure 
for these 


2.2.2.5 Communication Devices -- 


® DZQ11 Asynchronous This dual~-height module has four 
Multiplexer asynchronous serial lines that conform to 
RS232 and RS423-A interface standards. 

The module can be used to support printer 

options and full-duplex modem operations. 


® DMV11 Synchronous This quad-height module supports full- 
Controller and half-duplex operations, 5 
point, multipoint communications and 

DMA. 


sissies GN 


Installation 


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Configurations and Installation 


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2.4 VCB02 VIDEO SUBSYSTEM INSTALLATION 


The VCB02 video subsystem is shipped as an integral part of the 
assembled MicroVAX workstation system, and therefore, requires no 
customer installation. However, if the VCBO2 subsystem is an 
add-on to an existing workstation, or requires servicing or 
replacement, you will find its removal/replacement procedures in 
the appropriate BA23 or BA123 Enclosure Maintenance Guide. The 


VCBO02 connections, backplane slot insertion, and switch- pack 
on the VCBO2 base module (M7169) settings are given here to 
supplement the procedures in the Maintenance Guides. 


Figure 2-5 shows the cable connections for the VCBO2-B video 
Subsystem (4-planes). 


Figure 2-6 shows the cable connections for the VCB02~C video 
Subsystem (8- planes). 


1 27 
i 


@ shows the connections of an 8-plane configured system 
installed in the 


backplane of a BA123 enclosure. 


NOTE 
Consult the removal/replacement 
procedures in the appropriate System 
Maintenance Guide before attempting to 
service or replace the VCB0O2 video 


subsystem. 
Table 2-3 lists the VCBO02 base module switch-pack settings. (See 
Figure 1-1.) 


VCBO2 
BASE MODULE 


TORS 


15 CONDUC 


(M7169) 


PART NO. 


50 CONDUC “TORS 


Figure 2-5 VCBO2-B Cable Connections 


2-11 


CONNECTO 
PLATE 


. 


Configurations and Installation 


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Configurations and Insta 


_ ea iain ia AGN mae iii 


M7606-AA MicroVAX Il CPU (KA630-AA)——_ 
M9047 GRANT Cb 

M7607-AA MEMORY 1 MB (MS630-AA) —_ 
M9047 GRANT cb. 
M7504 DENN ETHERNET INTERFACES 
M7169 VCBO2 BASE MODULE _ 

M7168 VCBO2 4-PLANE MODULES __ 
M7168 VCBO2 4-PLANE MODULE _ 

M7513 RODX3 DISK CONTROLLERN_ 
M9058 SIGNAL DISTRIBUTION BOARDX 


a 


VCBO2? 4-PLANE VCBO2 4-PLANE VCBO2 BASE MODULE 


MODULE MODULE (M7169) 
(M7168) (M7168) 


Figure 2—7 VCBO02 Connections in a BA123 Enclosure 


11ation 


BACKPLANE 
AND 
CARD CAGE 


MA Ted GO 


Configurations and Installation 


spon Ui DD Dea gS EA ee 


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Table 2-3 Base Module Switch-Pack N 


keene oso ecm, . . GRO 


Ww 
= 
pa 

B«s 


“Settings 


81 Selects address line 3 0 = On l = Off 
82 Selects address line 2 0 = On 1 = Off 
83 Selects address line J 0 = On 1 = Off 
S4 Unused 


NOTE 


i 


page CSR. 


2 


Sl through S3 selects address lines for the I/¢ 


2.4.1 Internodule Connections 
The VCBO2 base module and the VcBOZ 4- plane module are connected 
togethe 


cher PY cables. The interconnect signals are of two 
categori 


es Sy 


95 a 


1. Interconnect signals common to both 4- plane modules in an 
8-plane sys tem 

2. Interconnect pele unique to each of the 4-plane modules 
in an 8-plane system. 

2.4.1.1 Common Intermodule Connections — The interconnect signal 

subsets are listed in Table 2-4. 

Electrical Connections 

Two versions of a 50-signal ribb 

used: sae to support 4-plane systems 

systems with daisy-chaining capabil 


cable with ground plane are 
; the other to support 8- plane 

ity between the three modules. 

Mechanical Connections 

A 50~pin Berg connecter is mounted on the edge of each quad-height 
module. 


pe 


Memory Signals 


RAS 

CAS 

MEMOE 

LATCH CNTROL 
WSTB 
MWEO:MWE3 
MADO:MAD7 
MAD9 

ADDCLK 


deals 


PHI1 
PHT 2 
ALPHA 
SYNC 
SHIFT30 
CLK30 


Video Processor Control 


128/~-16 
RD/-WR 
LTCLK 
TD0:ID7 
SCROLL 
FORCE 
IDCTL 
WRSCR 
WRUCS 


Table 2-4 


System Clocks 


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Common Intermodule Connections 


Memory row address strobe 

Memory column address strobe 
Memory output enable 

External memory latch controller 
Memory write from timing generator 


OAS SEE BLA SENSIS SSDS OHM SSS NSS SRS SRA AS IS SSG SENS en Stn eis a RIS ce eS 


Configurations and Installation 


REARRANGE Ce NR RRA 


Memory write enables from address processor 


Memory addresses from address process 
Memory address from address processor 
Address pipeline strobe 


19 Total 


Se ebenes eee a wandelte eue needed engerer 


VCBO2 video subsystem clock 
VCB02 video subsystem clock 
Video output clock 

System synchronization 
Video synchronizer 

Centrol synchronizer 


e ve 2 77 p ̃ p BS ASA SSSI PAPA 


Cycle control 

Cycle control 

Video processor latch clock 
Instruction/data bus 

scroll control 

Scroll control 

Chip select control 

Scroll chip select write strobe 
Update chip select write strobe 


16 Total 


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Configurations and Installation 


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2 Unique Intermodule Connections — Table 2-5 lists the 
signals between the VCBO02 base module and the first VCBO2 4-plane 
module. Table 2-6 lists the signals that pass between the base 
module and the second 4-plane module. 


ical Connections 
ferent lengths of a 20-signal ribbon cable with alternating 
and grounds are provided. The shorter cable connects to 
che ow-order 4-plane module, which is configured adjacent to the 
base module, but on the opposite side of the Q22-Bus arbitrator 
(MicroVAX CPU module). The longer cable connects to the high-order 
4-plane module, which is configured in the Q22-Bus backplane 
adjacent to the low-order 4-plane module). This scheme makes the 
two identical 4-plane modules appear electrically unique. 


me 


Elect 
d 
igna 


ri 
‘en 
18 
1 


Mechanical Connections 

The base module has one 15- conductor Berg connector on its upper 
edge, linked to the enclosure's connector plate. The 4-plane 
module has two 20-conductor Berg connectors, each aligned with 
connectors on the base module. 


2 1/0 Connections 
O connection on the base module routes the user 1/0 interface 
to a bulkhead on the enclosure. A cable connects to the 
nodule and terminates at the enclosure bulkhead. Refer to the 
0 al manual for the specific enclosure to determine the 
ength of the I/O cable required. Table 2-7 lists the I/O signals. 
2.4.2.1 Mechanical Connections — The 15-pin Berg connector is 
located at the upper edge of the base module. 


Table 2—5 Intermodule Connections (First 4-Plane Module) 


Video Signals 


PIVIDI 2 
PZVIDI 2 
P3VIDI 2 
P4VIDI 2 


25 


- Option 1 present 
— Defines 4-plane module video processors to be 
low-order 


OPT1 PRES j 
SELECT l 


alder aie die. 


10 Total 


216 


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Configurations and Installation 


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Video ‘Signals 

5VIDO, P5VIDI 2 
Berta, P6VIDI 2 
PYVIDO, PYVIDI 2 
PSVIDO, _P8VID1 2 
Status 


o PRES 4 = e 2 present 
SELECT ~ Defines 4~plane module video processors to be 
high-order 


ae, cl, dh 


10 Total 


5 al 8 F 1 Signals 


saison oasis aan SNM dae baue esas 


Keyboard, Port 1 
Transmit 
Receive 
Power 
ee 


VVV 


Auxiliary 1 POLES. ca 


Transmit 
Receive 
Power 
Ground 
ne V 


Video Signals 


Red video 

Red ground 
Green video 
Green ground 
Blue video 
Blue ground is 


15 Total 


ped — 


CHAPTER 3 
FUNCTIONAL DESCRIPTION 


2.» —t— — —-— eee 


ce SUBSYSTEM OVERVIEW 

This chapter describes the hardware functions of the VCBO2 video 
subsystem. The VCB02 video subsystem is a Q22-Bus-compatible, 
full-page bit-mapped, graphics video subsystem designed to support 
either the VR260 monochrome or VR290 color monitor. A DMA gate 
array chip (DC7035) provides the VCB02 subsystem with a 
specialized DMA engine that interfaces the Q22-Bus with the 
subsystem's video logic. The video logic is based on the address 
processor (DC323) and video processor (DC322) chip set. The 
address processor chip is responsible for all bitmap memory 
address calculations, CRT control, and video data path control. 
The video processor chip is responsible for all data manipulations 
to and from bitmap memory, and data output to the video refresh 
stream. 


a 


DMA gate array. One video processor chip is used for each plane 
bitmap memory in the VCB02 video subsystem. The subsystem is 
designed to support either 4 or 8 planes of bitmap memory. With a 
color monitor, a 4-plane system can display 16 colors (shades of 
gray for a black and white monochrome monitor) from a palette of 
16.7 million colors. An 8-plane VCB02 video subsystem can display 
256 colors (or shades of gray) from a palette of 16.7 million 
colors. Both the 4- and 8-plane versions of the VCBO2 video 
subsystem provide a screen resolution of 1024 (horizontal) X 864 
(vertical) pixels. 


Each VCBO02 video subsystem has one address processor chip and one 
of 


= 


Fach VCBO02 video subsystem has a base module that provides the 
Q22-Bus interface, diagnostic ROM, two asynchronous communication 
ports, the address processor, color maps, and video timing and 
output logic. A 4-plane VCBO2 video subsystem also has one 4-plane 
module that provides four video processor chips, four planes of 
bitmap memory, and chip select registers for the video processor 
chips. In addition to the base module, an 8-plane VCBO2 subsystem 
has two 4-plane modules, for a total of eight planes of bitmap 
memory and eight video processor chips. 

An 8-plane VCBO2 video subsystem is a 
4-plane VCB02 video subsystem is a 2-module 

communicates with the 4-plane module (s) through cables. A 4-plane 
VCB02 video subsystem can be upgraded to an 8-plane system by 
adding a second 4-plane module and changing the module 
communication cables. 


3~module set, while a 
le set. The base module 
K 
t 


Functional Description 


REECE SLO eNO UO ONE TCT FFF 


See VCBO2 MODULES 


C Pare Base Module 
The base module (M71 
calculati 
lists using 


bed 


hardware that: processes address 
to the Q22-Bus, accesses display 
c 


a tee 
. 
eX &, 
1 
See. 
r 
Here 
fe & 
ore 
ee 
2» © 
fag 


t plate trols cursor movement, accepts 
serial aay bus input from attached keyboard/mouse/tablet devices, 
self-tests/diagnoses malfunctioning module components us sing LED 
indicators, emulates consoles, generates subsystem tim ing, and 
provides an 8-plane video output path for its color bitmaps. 


a Chapter 1, the base module is 

1— is a block diagram of the module 
. on configuring the | : 
workstation enclosure, a tabulation of each module's power 
requirements, the ae intermodule connections, and 
instructions on module installation/s servicing. 


Ge ee ee | Instruction/Data Interconnect — The I/D interconnect is 
a byte-wide synchronous interconnect between the a $$ processor 
chip, video processor chip, and Se select registers. The I/D 
interconnect is synchronized to ge > System PHI1 and PHI2 clocks, 
which are further divided into HI 1A A, PHIIB, PHI ZA, and PHI 2B. 

Instructions are transferred on 5 A clocks, data is transferred 
on the B clocks. 


Chip Select Decoding 

The base module generates either a scroll or update chip select 
Strobe when a chip select instruction is decoded, The video 
processor chip selects are decoded from the 

accomplish this, A and B clocks and decode 1 
base module, and either a scroll chip selec 
or an update chip sel ite strobe (WRU 


D interconnect. To 
ic provided on 9 
ite strobe (WRSCR) 
are generated if a 
8 1 
2 


Se 


. 
og 
2 wr 
ect wr: 8 
chip select . is decoded. These 
to the 4-plane module through the module ir 
the data into registers on the I/D interconn 
¢ 


select load commands are shown in Figures 3- 


6 
es 


lqnals are cabled 


a : 

C 4 

tw gna 

1 nnect, and strobe 
rect. The external chip 
1 


ä 3-4, 


8 85 5 N Ae 0 A or 0 
. aie } 00 5 rie 

baal le 5 l * 0 10 a wl 
Penna ee eee ee ' veg. ARRON 1 dle 0 wines ph nl We . N ine 
: N | 
. e et i ei Sas $% ey N ae i ey a 0 e 1 . 
l , 5 9 i i : : . ok mm 
hao J q i kd é 


e 
. 
** 
0 


1 . as i 
i 

/ | ‘ 
Oh — eee 


xe DON'T CARE 


po 


croll Chip Select Load Format ~ Comme 


Figure 3-1 8 


Functional Description 


ith MLMMM MM MMA MMMM MMMM eee, 


ie 


Seg 
e 
en 


<8:1> = VIDEO PROCESSOR PLANE THAT WILL BE CHIP SELECTED BY THIS BIT (1 = ASSERTED). 
X = DON'T CARE 


Figure 3-2 Scroll Chip Select Load Format ~ Data 


08 07 06 
— — 
1 


5 O04 00 


x= DON'T CARE 


Figure 3-3 Update Chip Select Load Format ~ Command 160H 


15 08 07 06 05 34 
— — — (y—-„—ͤ 4 4 . 
| x x x * * * * xX | B | 7 | 6 


<8:1> = VIDEO PROCESSOR PLANE THAT WILL BE CHIP SELECTED BY THIS BIT (1 = ASSERTED}. 
Xx = DON'T CARE 


Figure 3-4 Update Chip Select Load Format ~ Data 


Functional Description 


LS RE CRE dd d og a NC oe i i inden ee chem 


eee 


32 1 2 Subsystem Timing Generation — The oe needed to run 
the VCB02 video subsystem falls into three cat -egories: „ 
clocks, memory strobes, and video clocks. The pixel clock (69.1968 
MHz) is used as che main divide down frequency. The inputs and 
outputs of the timing generator are listed below. 


INPUTS (all sourced by the address processor) 


Syne Reques 
Next i 
Next Rd/-Wr 
Force 


SYSTEM CLOCKS 


MEMORY STROBES 


LATCH CNTRL 
ADDCLK 


VIDEO 


TIES ECL: 5 
TTL/ECL 30 
TTL/ECL 30 
CONV H 
CONV L 


Note that on power-up, memory and system clocking does not begin 


until POK has been received. This is so the System powers-up in a 
consistent manner. 


3-4 


Functional Description 


— e pp p . 


ia 


Cad 


3 video Output Logic — The devices that source data for 
the video output are the video processors (bitmap data) and the 
DMA gate array (cursor data). Video data from all sources is given 
to the video output logic in 4-bit nibbles. The four main 
functions of the video logic are hardware cursor support, mapping 
of the video data through a color look-up table (LUT), converting 
the digital video information into RS-170 voltage levels (not 
timing) for output to the monitor, and looping back the video 
output for diagnostic readback and self-test. 


The following paragraphs describe the operation of the hardware 
cursor, the color map loading, and the video loopback register. 
The digital-to-analog conversion is not accessible to the 
programmer. 


Hardware Cursor 
The 2-plane hardware cursor is used to multiplex the video 
information to the pixel level in the following ways. 


Cursor plane A data is 0 The cursor is transparent and bitmap 
data appears on the screen. Note this 
is the general case any time the cursor 
positioning logic is not outputting 
cursor data. 


Cursor plane A data is l This can occur only when the 
positioning logic is outputting cursor 
data. In this case, cursor plane B data 
controls data to the screen in the 
following way. 


Cursor plane B data is 1 Location [255] of the color map is 
accessed. This location is always 
considered foreground cursor color, but 
may be accessed by bitmap data as well. 


Cursor plane B data is 0 Location [254] of the color map is 
accessed. This location is always 
considered background cursor color, but 
may be accessed by bitmap data as well. 


Synchronization and Blanking 

Video synchronization and blanking are programmable by the address 
processor on any rising PHI3 or PHI4 clock (57 ns interval 
nominal). They must then be synchronized to the video timing and 
shifted so their pipeline is equivalent to that of the video 
output path. Video blanking can also be enabled by setting a bit 
in the memory CSR. 


Video Upgrade Path 


When only one 4-plane module is installed, the upper four bits of 
the video data path are disabled. 


325 
a il 


Functional Description 


aon 


VVV 


a 


COLOR MAP DATA BYTE 


X= NOT LOADED 


MP1 6986 


Figure 3-5 Color Map Data Format 


Color Map Loading 

Color map loading pertains only to the base module. In a 4-plane 
configuration, only the low 16 addresses need to be loaded in each 
map, except for locations [254] and [255] (used by the hardware 
cursor). In an 8-plane configuration, all 256 locations should be 
loaded. The red, green, and blue color maps are accessed 
independently (256 locations for each map). Figure 3-5 shows the 
format for the color map data. 


Color maps should be loaded only during vertical blanking time so 
that no "glitches" are noticed on the screen. If this is not 
possible, a bit provided in the CSR will force the video to a 
blanking state while the maps are being loaded. 


3.2.1.4 I/O Devices — The VCB02 video subsystem has two serial 
EIA RS-232-compatible ports that can be addressed. One port is 
always reserved for the LK201 keyboard. The other port can be used 
for any other serial device, probably a mouse or a tablet. For 
programming information concerning these ports refer to Appendix 
B, C, and D, respectively. 


NOTE 
The serial ports are RS~232 voltage- 
compatible only. 


LK201 Keyboard 

The LK201 keyboard is the keyboard interface to the VCBO2 video 
subsystem. A double- buffered UART in the Q22-Bus 1/0 space 
provides the send/receive port to the 4800 baud serial device. A 
Switch closure on the keyboard causes an interrupt to the Q22-Bus 
to be serviced by reading the value of the UART receive register 
at the CSR address specified in the map. The LK201 keyboard is 
described in Appendix B. 


Mouse 

The 3-button circular mouse is supplied with the Microvax 
workstation. It is RS-232-compatible, using standard serial input 
device protocols. The mouse is described in Appendix C. 


Functional Description 


e TONS NA p RSI 


Tablet 

The optional digitizing tablet responds at the address found in 
the CSR map. It is capable of interrupting the MicroVAX 
workstation for service of position changes and external events. 
The tablet is described in Appendix D. 


Serial Device Protocols 
The protocols for the serial devices are described in the 
Appendices: Appendix B - LK201 keyboard, Appendix C= 3 button 


15 


circular mouse, and Appendix D - optional digitizing tablet. 


Monitors | 
The monitors specified for the VCB02 video subsystem are the VR260 
for monochrome applications and the VR290 for color applications. 


3.2.1.5 System Support -- The system support provided by the 
VCB02 video subsystem includes console emulation, multiple VCBO02 
terminal support, and full diagnostic support. 


VCBO2 Address Map 

Each VCB02 video subsystem has one register in the Q22~Bus I/0 
page. See Figure 3-6. Switches on the base module are used to 
select one of eight possible addresses for this register, as 
listed below. When read, this register provides an identification 
code for VCB02. Data written to this register selects the VCBO2 
memory base address (on a 64-Kbyte boundary). Figure 3~7 shows 
the Q22-Bus memory space. Register mapping is shown in Figure 3-8. 
All registers are accessed on word boundaries. 


VCB02 Address Mapping Scheme: 


QBUS I/O PAGE BASE 
QBUS I/O PAGE BASE 
QBUS I/O PAGE BASE 
BUS I/O PAGE BASE 
QBUS I/O PAGE BASE 
QBUS I/O PAGE BASE 
QBUS I/O PAGE BASE 
BUS I/O PAGE BASE 


1FOOH* 
1FO2H 
1FO4H 
1FO6H 
1FO8H 
1FOAH 
1FOCH 
LFOEH 


+e etter + + + 


Q22-BUS I/O PAGE 


VAX ADDRESS = Q22-BUS 1/O PAGE BASE + 1E8x 


Figure 3-6 Q22-Bus I/O Page 


+L eR 


* Alternate Console: A VCBO2 module assigned this address is the 
system alternate console device. 


3-7 


ctional Description 


CC 


Fun 


ee 


ao 


VAX ADDRESS = 


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88 = 


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4% 


VAX ADDRE 


RAM 


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oes 


UPTO: 


Veo? 


MIR 


0 


GREEN COLOR MAP 


a 


BASE + E000 (HEX 
C 


BASE + CEOO (HEX) 


E COLOR MAP 


BLU 


E + CCOO (HEX) 


den 
% 


BA 


BASE + CAOO (HEX) 


ey, 


= 
oe 
, 
9 
+ 
111 
* 


ATION DEVICE 2 


is 
0. 


COMMUNIC 


CATION DEVICE 


| 


COMMUN 


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2 
a 
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2 
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<< 


GATE ARRAY (DGA) 


BASE + C200 (HEX) 


Register Mapping 


BASE + COOO (HEX) 


Figure 3-8 


Functional p 


eue enen en 


2. 1. 6 Control and Status Registers (CSRs) ~~ The VCB02 video 
ubsystem has two control and status registers. One is located in 
> «6Q22-Bus 1/0 page, the other in 022-Bus memory Space. Both 
egisters are read/write, 

I/O Page CSR 
Figure 3-9 shows the format for the 1/0 page CSR read VCBO2 
identification code. 


ue written into the memory base register selects the 
address (base addr ess) of a 56-Kbyte block of addresse 
be decoded by the VCB02 DMA gate array. The base address 
ayS on a 64-Kbyte boundary in the Q22-Bus memory address 
as selected by bits 00 through 05 of the memory base 
Bits 05 through 00 are compared with signal pins 

: H during the address portion of 0Q22-Bus memory cycles, 

e 3-10 shows the write memory base register format. 


Memory CSR 
Figure 3-11 shows the memory CSR read video readback register 
format. Figure 3-12 shows. the memory CSR write format for the 
control write register. 


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Figure 3-10 Write Memory Base Register Format 


Functional Description 


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x X 3 | 2 | 1 
BIT 3: SYNC DETECT (0 = ASSERTED) 
BIT 2: BLUE > RED (O = ASSERTED) 
BIT 1: GREEN > BLUE (O = ASSERTED) 
BIT 0: RED > GREEN (O = ASSERTED) 
MA 0 J 
Figure 3-11 Memory CSR Read Video Readback Register Format 
15 06 01 00 
x x x x 8 x x x x x 
05 — b masken 
BIT 5: CSR BLANK (O = ASSERTED) 
BIT 4: CSR VIDEO READBACK (1 = ASSERTED) 
BIT 3: CSR SYNC ENABLE (1 = ASSERTED} 
BIT 2 LED FOR HIGH-ORDER MEMORY UPGRADE FAILURE (O = ASSERTED) 
BIT 1: LED FOR LOW-ORDER MEMORY UPGRADE FAILURE (O = ASSERTED) 
BIT 0: LED FOR BASE SUBSYSTEM FAILURE (O = ASSERTED) 


Figure 3-12 Memory CSR Write Format for the Control 
Write Register 


3.2.1.7 Console Emulation — The VCBOZ video subsystem supports 
console emulation through interactions of the MicroVAX CPU, the 


MicroVAX boot ROM, and the VCBO2 ROM, which are mapped in the 
VCBO2 address space. 


The VCBO02 video subsystem is the alternate console device, and 
supports Micro/ODT by providing an ASCII interface to the system 
when in console mode. The VCB02 ROM is word~addressable to allow 
direct MicroVAX CPU reads. For a more detailed explanation of the 
VCB02 diagnostic requirements, refer to Chapter 5. 


Functional Description 


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5 


3.2.1.8 Diagnostic Support — 


3 3 and console 
the VCBO2 ROM, refer to Chapter 


emulation. F. or more informa In on 


Bitmap and Template ne Access 
r memory on the VcB02 4- plane module is divided into three 


ap memory can be accessed through processor-to-bitmap and 
Processor transfers, which are executed through the 
ocessor and vide eo processor chips. Template RAM memory 
IV accessible through Q22-Bus transfers, The LUT, which 
ritten directly is read back indirectly eneough the 
2 as cribed be 


PS 


i 
low. 


a 
. 
iv 
2 
ve 


‘peaabaek path is accessed 5 the memory CSR. Three 
ies „„ to comparisons of the outputs of the 

1 ~analog converters. The e outputs are compared 
through the different at eres levels, so there is 
of confidence in the integrity of the video output 


te 1 


The resolution of this comparison is 20 mv. 


S$ the comparison of the synchronization pulse 
gr gun to a known reference voltage. In 


2 on > een gun 
of a ror, this helps diagnostics determine Le 


| 
he e £ 
che error is ont B02 ule or a monitor/cabli ing problem. The 
reference voltage is set at 0.1 , and the comparison resolution 
3 20 mV. 


Belek Four~Plane Module 
The 4~plane module (M7168) has the hardware that provides the 

lane [l-page memory to the base module. Refer to Chapter 1 
of the 4-plane module's components and Figures 1-1 and 
onfiguration, power requirements, intermodule 


1 


8 
and installation information, refer to chapter 2. 


Memory Structure — For each on- screen“ page of 
plane, the VCBO2 video subsystem provides an equal 
-f£-screen" memory "On-screen" refers to the memory 
used for screen ref ‘resh. The VCBO2 video subsystem 

| programmer a block of memory that is 1024 
X 2048 (vertical) pixels. 


— se 
3-12 


iption 


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303 ADDRESS AND VIDEO PROCESSOR OVERVIEW 
This section presents an overview of the features and operation 
; 


h 
the address processor and video processor chips as 
the VCBO2 video subsystem. 


The address processor chip (DC323) controls all video 
in the VCBO2 video 5 The DMA gate array on the | 
module controls the register interface of the address pre 

sing a 16-bit private ee bus, a 6-bit address bus, and cont 
Signals. Internal to the address processor is a register struct 
through which all commands to, and information to and from, 
video chips must pass. Communication between the address pr 
and video processor chips occurs on a byte-wide ener ener 
(I/D) bus. The address processor chip registers are cla 
into four categories: control, scroll, rasterop n 1 
configuration registers. Once these registers are properly 10 
the address processor chip uses control signals and the I/D bus 
synchronize all internal address calculations, CRT control, and 
exte rnal memory cycles with the video processor chip's dat 
manipulations. 


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The video * chip (DC 322) is the bitmap data path 
VCB02 video subsystem transactions. The ae processor 
controlled by signals from the address processor chip anc 
programm mable registers that can be loaded from the ee 
registers are classified into three categories: ser 
and configuration regi isters. Once properly eee 
processor is capable of: sourcing and receiving data 
bus, logical operations on bitmap data, barrel ehiteis 
sourcing cae to the output video bus. 
The t/D bus is a byte-vide synchronous interconnect between the 
address processor, video processor 115 chip select registers. The 
175 bus is synchronized to the system PHII and PHI2 clocks 
are further divided into PHIIA, PHI1B, PHI2A, and PHI2B. 
Instructions are transferred on the A clocks, and data 
transferred on the B clocks. 


Jacek Hardware Support 
The address processor chip is responsible for funct 
all bitmap planes, such as: all rasterop comput 
address generation, clipping, screen refresh, scro. 
monitor synchronization generation. The video 

(DC322) provides the data path and control data FI 


and scrolling, a barrel shifter for bit N 
with data and mask registers for memory modi 
address logic, and a control store RAM to define 
chip operations seem rasterops. Figure 3-13 is 


of the VCBO2 video subsystem. 


Functional Description 


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BITMAP MEMORY 
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| MEMORY | 


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Figure 3-13 VCB02 Video Subsystem, Block Diagram 


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Functional Description 


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3.3.1.1 Buses — The address processor chip communicates on three 
buses: 


l. 


& & 
a ee 


The private data bus is controlled by six control lines 
and six address lines, and has 16 bidirectional data lines 
that transfer data to/from internal registers in the 
address processor chip. These registers may be addressed 
in two ways: 


a. The six address lines are provided for direct access 
ne MicroVAX CPU through its normal memory or 1/0 
sing modes. 

b. An address counter in the address processor chip 
allows the DMA logic in the DMA gate array to pass 
data and control words to sequential address processor 
chip registers via a single register (address). 


The bitmap address bus provides 11 bits each 
multiplexed row and column address to the bitmap RAM. Tr 
VCBO2 uses 8 row and 9 column addresses to access 
words (2 M bits) of bitmap memory. The bus also provides 
all addresses for screen refresh, scroll writeback, and 
bitmap read and update. 


ntrols the 


The instruction/data (I/D) bus (interconnect) co 
1 data flow 
ic 
F 


video processor chips and provides for al 
between the video processor chips and the M 
(via the address processor chip). Each cycle of the 8-bit 
I/D bus has four states that provide a 16-bit instr ‘action 
from the address processor chip to the video processor 
chips, and 16 bits of data from one I/D bus device to the 
others. These cycles are sed to configure the video 
processor chip registers, regulate data areata fers during 
rasterops, and load the chip select registers on the I/D 
interconnect. The chip select registers external to the 
video processor chips and controlled by the I/D bus are 
used to enable one or more video processor chips to 
perform a transfer. 


Aba CPU 


ie 


The video processor chips use three buses: 


1 


2 


ws 


‘ie 


ee 


The I/D bus (interconnect) described above. 


The 16-bit memory data bus is used in the transfer of all 
data to or from the memories during screen 1 scroll 
writeback, and memory update. 


The video output bus supplies the bit 

plane as successive 4-bit nibbles. nea ex 
externally processed by the color 7 videc 

registers, and D/As to provide the video signa. 

monitor. 


Functional Description 


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3 Bitmap Memory -~- Each plane of bitmap memory 
„ as eight 64 K X 4 dynamic RAMs. A total of 2 M bits 

rovided for each plane, with 864 K bits used for screen refr 
(1024 horizontal X 864 vertical pixels). The remainder is used fo 
fFf-screen storage of fonts and bitmap data. 


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„ Timing — 3 timing refers to a nominal 

> 1 ns actual). All bus m i 
it bi and is based on mu 
fideo bus operates at 60 ns. 


nterface on the address processor chi i 
12 f the aes hardware because its timing 
he DMA gate array. 


cr 


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is 8 


There are two kinds of bitmap memory cycles. A major cyc 
nominal) is used to read or write 8 words 8 1 
the video processor ch for screen refrest ling. Any 
unused major cycle is subdivic So called 
update cycles, 480 ns nominal) er a read 
r of sh 


a4 
Jed into 2 minor oy oles 
4 } 2 t | 
a read-modify- a word may occur to accompli bitmap 
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during any of which ei 
r 


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Fic 

update. Refresh of the eer bitmap memory is accomplished every 
593 us (except du ng vertical retrace, which is less than 677 us) 
by the screen refresh read. (Worst case refresh time = 1.263 ms.) 
Figure 3- Shows an example of a scan divided into 16 major 
oes 3 are used for screen refresh, and seven may be used 
for scroll writeback, if any of their words are contained in a 
scrolling region. The remaining 8 9 plus any unused scroll 
cycles, are divided into minor cycles for updates or NOPs. The 
address bus provides one row and eight column addresses during a 
major cycle, and one row and one column 5 during a minor 
cycle. The data bus to the video pr r chips operates 
concurrently to transfer 8 words (128 bit a uring a major cycle, 
and to read and return a modified word (16 hes) during a minor 
cycle. 


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. 


In the VCBO0O2 subsyste 
8 b 


stem, each scan is programmed to last 10 ma 
ycles (8 are used ef ; 
£ i 2 Ta 


2m, ; 12 
r screen refresh). The positioning and width 
E Or | ng and synchronization are programmable with 
espect to memory cycles; they are set as required by the VR260 
and VR290 monitors. The number of scans per frame - programmed t 
including vertical retrace 1 the number of displayable 
8 64. The position and width of Ver pete 5 blanking and 
ronization are programmable; they are set as required by the 
and VR290 monitors. 


t 
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The I/D bus operates continually at the minor cycle rate (480 ns 
nominal), whether major or minor cycles are in progress. It also 
operates in synchronization with the memory cycles, during which 


two instruction bytes and two data bytes are transferred. 


Functional Description 


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Process 


Functional Description 


An interface to a DMA controller (in the DMA gate array) allows 
decoupling of the MicroVAX CPU from address processor chip 
execution. A request pin may be programmed to assert on any of the 
Same conditions that are available as flags or interrupts to the 
MicroVAX CPU. This pin requests the next data word from the DMA 
gate array. When loading data and command registers, the DMA gate 
array writes to a special address in the address processor chip 
that is associated with an internal address counter. If the MSB of 
the data word is clear, the counter addresses the address 
processor chip register to which data is to be transferred. The 
counter is incremented after each word is transferred. If the MSB 
of the data word is set, the address counter is loaded with the 


‘ite 


low six bits of the data word. 


Only the I/D bus data registers contain 16 significant bits of 
data to allow loading of arbitrary data to these addresses. The 
MSB does not cause the address counter to be loaded if it is 
pointing to either of the I/D data registers. (The addresses of 
these registers are preceded by reserved register addresses so 
that no register load will cause the address counter to be left 
pointing inadvertently to an I/D data register.) The register 
addresses are assigned so that common repetitive functions only 
need to access one group of consecutive registers, in addition to 
the command register. A group of special instructions have also 
been implemented in the DMA gate array to further assist in the 
execution of commands. 


3.3.4 Viewport Support 

To assist the implementation of multiple viewports on the screen, 
the VCB02 chips provide clipping to, and scrolling or dragging of, 
rectangular regions. (The term "region" refers to the 
implementation of viewports in the hardware.) The top and bottom 
of a region may be set to any pixel, the left and right edges must 
lie on a multiple of four pixels from the left side of the screen. 
Figure 3-15 shows examples of possible region configurations. 
There is one clipping (update) region and one scrolling region at 
any instant, but the two are independent of each other. This is so 
writing and scrolling may be active in different regions at the 
same time. Any part of the screen not currently contained in 
either the clipping or scrolling region cannot be modified. It 
will retain any data placed in it previously. The whole update 
region may be either scrolling or not, but a region should not be 
updated if only part of it is scrolling. (For instance, region ll 
should not be updated if region 5 is being scrolled.) 


When a region with writing disabled is updated, clipping still 
allows the image outside the region to be computed. The address 
processor chip provides status to the MicroVAX CPU to indicate 
whether or not any rasterop was completely or partially clipped 
while writing (to aid in selecting algorithm). These clipping 
status bits are accumulated as rasterops progress, and may be read 
or cleared at any time. However, the results are predictable only 
if the bits are read or cleared between rasterops. 


Functional Description 


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Figure 3-15 Region Configuration Example 


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The regions are allowed to be independent as much as possible. The 
Scrolling resource must be allocated to only one region per frame 
time (and an additional frame time is normally required to change 
regions). All regions must share one color map and agree on 
resolution mode settings. Unless large amounts of extra bitmap are 
provided, regions share the off-screen areas used for symbol and 
data storage. Obviously, overlapping regions cannot be independent 
of each other. 


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Functional Description 


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3. 3. 4.1 Scrolling — Scrolling movement can be up, down, left, or 
right (but not diagonally) at a rate of 0 to 15 pixels/frame (or 
faster for vertical scrolls). The part of the region vacated by 
the moving image is simultaneously filled with any solid color. 
Scrolling uses part of the memory time that would otherwise be 
available for writing; but, even when the whole screen is in 
motion, 30 to 40 percent of the nonscrolling update time is still 
available for source/destination operations, depending on screen 
format. (Fifty to eighty percent of nonscrolling time is available 
for destination-only or source-only operations because these 
operations are primarily compute-bound when not scrolling.) 


NOTE 

Actually, the distance of an upward 
scroll is limited only by the number of 
scan times allowed for vertical retrace. 
This time is used to write the fill 
color back into the vacated memory if 
the region extends to the bottom of the 
screen. The distance of a downward 
scroll is subject to the memory 
limitation described below. 


Scrolling is accomplished by moving all the scrolling data from 
its old position in memory to a new position. The normal screen 
refresh process reads and displays the existing memory data, and 
additional memory write cycles are used where necessary to return 
scrolling data to new locations. This is the only technique that 
allows a region of any size, including the whole screen, to be 
scrolled in one frame time; but there are two unpleasant side 
effects. First, only one region can be in motion during a frame 
time, because two regions might need to write portions of the same 
word to more than one memory location. Second, scrolling down 
cannot be accomplished in the obvious way because this would 
require writing data into memory locations not yet read by the 
refresh/scrolling process. An attempt to do this would destroy 
screen data. 


Instead, scrolling down moves all the data outside the scrolling 
region up, and then offsets the memory address at which screen 
refresh starts reading the bitmap. This creates the illusion that 
the scroll region moved down. (Proper synchronization is 
maintained so that the data outside the region does not move.) 
This creates four bad effects: 


1. Some scans of memory must be reserved (and not displayed) 
to prevent data at the bottom of the screen from being 
overwritten by data from the top. The number of scans 
required is equal to the maximum distance, in pixels, to 
be scrolled down in one frame time. 


2. The writing time is consumed as if the whole screen were 
scrolling up. Scroll writing must occur throughout the 
frame so that all data can be moved up in planes where 
scrolling is disabled. 


Functional Description 


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3. Diagonal scrolling is not possible because different data 
must be moved for the downward and sideway motion of a 
region. 


4. Management of the Y offset adds extra work for the 
MicroVAX CPU. 


To synchronize scrolling commands with screen refresh, most of the 
scroll-related registers in both the address processor and video 
processor chips are double- buffered. In the address processor 
chip, the index registers are buffered only to the extent required 
for the continuation of scrolling in one region. (See the NOTE 
below.) The pending half (top level) of any buffered register is 
addressable by the MicroVAX CPU and is loaded at any time during a 
frame. Between frames, the address processor chip transfers the 
data from all pending registers to the active registers, and then 
sets the flag that requests more scroll data. 


A separate I/D command and data path (including chip select 
control for the video processor chips) is provided for scrolling 
to prevent interference between the loading of video processor 
chip registers for scrolling and for updating. This allows a 
scroll service routine to act without regard to the state of 
update service. The scroll and update services must avoid using 
each other's registers. 


NOTE 

To conserve die area in the address 
processor chip, scroll registers are 
buffered only to the extent required to 
sustain scrolling or dragging of a 
single region. Extra buffering of the 
index registers would be needed to 
scroll different regions in successive 
frames. This function is not considered 
important because its only use would be 
in trying to simulate simultaneous 
scrolling of two separate regions. 
However, since a smooth effect cannot be 
achieved with this technique, it should 
not matter that the abruptness of 
jump-scrolling of the two regions is 
increased. If the MicroVAX CPU were able 
to service an interrupt request to load 
4 registers in 200 to 500 s, it would 
be possible to scroll different regions 
in successive frames without the extra 
buffering of the index registers. 
(Normally, the MicroVAX CPU takes an 
entire frame time to load a buffered 
register.) 


3722 


Functional Description 


ß r 


3.3.4.2 Dragging — The scroll function can be used to drag a 
region smoothly to a different place on the screen. For each 
increment of motion, the scroll boundary registers are set for the 
current region location, but with the region size increased in the 
direction of motion by the distance to be moved. This allows the 
whole region to be moved, without the normal truncation, and 
leaves the fill color in the "wake" of the region. Because the 
region boundaries can be defined only on 4-pixel increments in the 
horizontal direction, horizontal dragging must stop on 4-pixel 
boundaries, however; it is possible to move the region at any 
valid scroll speed during the drag. 


If desired, the area to be covered by the moving region may be 
saved prior to each movement, and the area vacated may be restored 
after each movement. A region cannot be updated while it is 
scrolling because there is no way to synchronously change the 
clipping boundaries. The clipping boundaries are not 
double~buffered as the scroll boundaries are. == 


3.3.4.3 Clearing a Region — The address processor chip has a 
provision to allow a region to be cleared to the fill color in one 
frame time, using the bulk scrolling hardware. This action is 
linked to one frame time in the same way that scrolling is. While 
small regions (less than one-sixth of the screen) can be cleared 
more quickly with a rasterop, the erase mechanism does the same 
very cleanly because it is synchronized to occur between two 
display frames. 


3.3.4.4 Drawing in the Scrolling Region — The blank space 
created by scrolling needs to be filled with new data. Drawing as 
scrolling continues is desirable because the smooth effect of the 
scroll is not disturbed. The indexing mechanism of the address 
processor chip allows data to be drawn to the correct screen 
location without regard to how scrolling is moving the screen. 
Typically, the update process draws the display list (or selected 
portions of it) repeatedly to keep filling the scroll region as 
more blank space is created. 


The clipping region stands still during scrolling to prevent data 
from being written outside the region. However, this means the 
clipping region cannot be used as a "drawing function" to control 
the shape or extent of objects being drawn into a moving region. 
This is so because the clipping region does not move with the 
objects as they are drawn. Also, clipping cannot be used to 
prevent multiple writes of data when the same display list 
segments are repeated during scrolling. This would require the 
clipping region to follow a particular set of blank pixels as they 
move on the screen. Multiple writes will create problems for 
display lists that contain segments drawn in complement mode or 
drawn with the painter's algorithm (in which successive elements 
replace previous elements). 


Functional Description 


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To enable synchronizing the update process with scroll commands 
(that is, to fill the blank areas created by scrolling), the pause 
register and the interrupt oer request enable bits can be set to 
interrupt the MicroVAX CPU or request further data from the DMA 
gate array (during DMA) when a specific point on the screen has 
been passed by screen refresh. Normally, the pause is set by the 
scroll service routine to allow the update process to continue 
after the top or bottom of the scroll region is displayed. This 
allows a full frame time to fill the top or bottom edge of a 
region that is scrolling up or down before the blank space would 
become visi) 


Indexing 

To allow updating from the MicroVAX CPU or DMA gate array into a 
region that is scrolling (or has scrolled) without requiring the 
MicroVAX CPU to change the coordinate values in its display list, 
index registers in the address processor chip are added to the 
first source and destination coordinates to match the new position 
of data that has been moved in the memory by scrolling. 


There are six index egi 


ers: old K and 1, new X and , and 
pending X and Y. The 1d v = 


st 
alues are the indexes that apply to data 

that has not yet moved during the current frame; the new values 

are the indexes that apply to data that has already been moved; 

the pending values become the new values at the start of the next 
K 


2 


frame. Between frames, the address processor chip transfers the 
value stored in the new register to the old register, and from the 
pending register to the new register, thus starting the new frame 
with the correct indexes. The index values apply to the region 
that is being updated. Ordinarily, if the update region is also 
being scrolled, the new and old indexes will differ by the scroll 
constant (X or !) for the current frame (loaded in the previous 
frame). If the update region is not being scrolled, the new and 
old values are the same. 


The index values must be changed by the update process between 
updates to different regions. Also, if the update region is being 
scrolled, the scroll process must update the index values between 
frames so that updates will stay locked to the scroll movement 
when they extend beyond the end of one frame time. Because both 
the update and scroll processes modify the index registers, and 
the update process must use the most recent values provided by the 
scroll process, a very tight interlock must be maintained between 
these two processes. 


This interlock is . by the MicroVAX CPU, if the 
DMA-driven update process has not changed the update region to one 
that is scrolling. This so because a frame may end between the 
time the MicroVAX CPU dex values in the data list for the DMA 
me 
2 


18 
in 
controller and the ti these values are loaded into the address 
processor chip. It is best not to send region changes via DMA. 


3-24 


Functional Description 


sR 


sie iii sii aS NE i rR iC NSS li SRR aOR aia GCG 


When the MicroVAX CPU changes the update region, the following 
interlock with the scroll process is recommended. 


1. The MicroVAX CPU always executes the scroll process and 
the part of the update process that changes regions (no 
DMA controller). 


2. The update process must be interruptable by the scroll 
process when the 1 process is changing regions (note 
exception below), unless the latency caused by disabling 
interrupts during index loading is acceptable to the 
system. 


3. During a region change, the update process loads a memory 
location that tells the scroll process which region is now 


xi 


being updated. 


4. The update process copies the correct index values for 
that region from a table maintained by the scroll process 
to the address processor chip registers. The index 
registers must be loaded in the order: pending, new, old. 
If the instruction(s) used to move each index value to the 
address processor chip is (are) interruptable, it is 
necessary to disable interrupts (at least for the priority 
of the scroll service interrupt) while each index value is 
copied. 


5. If a new frame is started, the scroll process is awakened 
by the scroll service interrupt from the address processor 
chip. The scroll process must run to completion before 
returning to the update process. The scroll process 
updates the index table entries for the region being 
scrolled, so that new values are available to the update 
process. 


6. The scroll process should load all six index registers in 
the address processor chip with the new values for the 
region being updated. If the update region is not the same 
as the scroll region, the registers need not be loaded. 
If the scroll process is certain that the index values in 
the address processor chip corresponded to the region 
being scrolled before the end of the frame that caused the 
scroll interrupt (perhaps there is only one region on the 
screen, or only the scroll region has been updated since 
the last scroll), then only the pending index registers 
need to be loaded. 


7. Update processing may now continue. 


SS BU CG EDS eI IR i i AES DAG TS SGU a Roo RUAN 


e Support 

ple video processor chips (data path chips) allows 
mult manipulation of data in many planes of memory. 
deo processor chips are 1 by, and exchange data on, 
D bus The registers fo data transfers and the logic 
> performed may be „ programmed for each 
chip in the system. 


ey, 


„3.5.1 Z-Axis Addressing ~~ Z-axis operations allow the exchanc 

of data between the address processor and video processor chips on 
t. sing 16 bits of a data word to transfer 1 bi 
16 planes. This can be used for both the 
ata between the MicroVAX CPU and th 


I ) e bitmap, and the loading 
ate video processor chip data 1 


40 ko sii 5 
registers. 


it plane 
D bus . 


5 


sits specify th it within an 
ich a ewides processor chip will respond dur 
-he upper 2 bits specify the Z-block (shou 
30 f the VCB02). No two planes may have the same ad: 
must be ensured by the MicroVAX CPU.) 


rogrammed with a 6<b 
85 


1 
ing a Z~axis 

ld be set 80 
dress. (This 


ring processor-to-bitmap (PTB) or bitmap-to~processor (BTP) data 
3 data in a normal rectangle from the bitmap is 
transferred fr 

vi r 


r 
t 
0 om / to PI y the DMA logic 
the DMA gate arr 2— 


ae 


i J memory 1 
array or the MicroVAX CPU itself. If Z-mode transfer 
re requested, each word transferred will be the color of one 
pixel. Since a VCB02 video subsystem can have a maximum of 3 
lanes, the DMA gate array can be used to pack/unpack data as it 
s transferred to/from the MicroVAX CPU memory. Compressing ‘th 
ata reduces the memory required to store an image, and reduces 
ne Sire bandwidth required to transfer the data. 


0 


A Z-ax IS I/D bus cycle ca 
mmand, to load ei 
011 fill data registers 


an be commanded directly, with an I/D 
ther the source, foreground, background or 
n the video processor chips. The 
to the logic units in the video 
round and background registers are 
Das Is by the output of the logic unit. 
1 can program the video processor 
ubsequent elements will be drawn. 
F chips define the color 
areas of scrollec 2910 


Address Calculation and Data Path Hardware 
processor and video processor chips contain bitmap 
é to execute the commands provided by the 


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5 


Functional Description 


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The three rasterop modes are: normal, linear pattern, and fill. 
The contents of the address processor and video processor chip 
rasterop parameter registers are not modified or destroyed by any 
operation of the system. Only those registers whose values are to 
be changed need to be loaded between operations. Of course, the 
contents of data registers may be changed by rasterops. 


3.3.6.1 Address Processor chip Addressing -- Every rasterop has 
a destination and may have zero, one, or two sources. A zero 
source implies a constant source. The destination generator 
selects pixels to be modified and the source generators select 
pixels to be combined with the destination. No curve algorithms 
are implemented because all the useful ones require 
multiplications, and there is no best“ algorithm for all 
applications. Curves may be handled by passing a series of 
straight vectors to the address processor chip. 


The destination is a parallelogram and may be of different size or 
orientation than the first source rectangle, with the data scaled 
or rotated to fit the destination. Rotation and scaling are used 
more for transforming picture elements, such as characters and 
patterns, than for transforming whole pictures. However, scaling 
can be used to "zoom" an image to an area of the screen by a 
scaled copy from another area, possibly off screen. The 
parallelogram (as opposed to simple rectangle) form of the 
destination is largely a fallout of its implementation as two 
independent vectors, but is useful for forming italic characters 
and performing operations on screens with nonsquare pixels. 
Rotation and scaling may not be suitable during complement mode 
drawing operations. 


The sequence of source/destination operations is controlled by the 
address processor chip command register. Three bits select one of 
the eight possible combinations of sources and a destination. (The 
possible sources are: none, first, second, and both. The 
destination is either on or off. Note that not all combinations 
are useful, however.) The source and destination addresses are 
always computed, but these three bits determine whether they are 
used. The effect of the source data is determined by the 
programming of the video processor chips. 


The origins for the first source and the destination areas may be 
offset by the addition of an & anda * index. Index mode may be 
invoked for either the first source or the destination 
independently, but the X and Y index values are the same for both. 
This mode allows the command data to remain unmodified: when a 
region has been scrolled or is being scrolled (only the index 
values need to be updated); and/or the origin of a region may be 
(0,0) to the update process, regardless of its actual location in 
the bitmap. 


e xia 
3 ihe 


Functional Description 


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All address computations in the address processor chip use 14-bit, 
2' complement numbers for each X and Y. Beyond the 14-bit limit, 
calculations wrap from plus to minus in the normal fas shion. The 
usable range of values for any of the DX or DY registers is +/- 12 
bits (+/- 4095 pixels) because these values are multiplied by 2 in 
Some internal calculations. However they are still specified as 
14-bit, 2's complement numbers. Thirteen bits of the X address 
cluding specification of the pixel within a word) and thirteen 
ts of the Y address are available at the output of the chip. 


A 6-deep FIFO is provided to store the computed addresses before 
they are used in memory cycles. This allows better use of 
available memory cycles during scrolling. If only one destination 
Or source is required, six operations can be stored (and two more 
can usually be computed while these are being used, so that at 
least eight operations can be performed during each scan of 


scrolling, if the screen format allows); and, if 
Source/destination operations are required, three (or two for 
double source) ope erations can be stored. Figure 3-16 shows the 
address processor chip data path. 


FF 


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Figure 3-16 Address Processor Chip Data Path 


Functional Description 


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Destination — Rotation 

The destination is a parallelogram defined by two vectors and an 
origin. See Figure 3-17. Each vector is defined by two signed 
integers representing a horizontal delta (DX) and a vertical delta 
(DY), and both vectors start at the same origin. The area is 
scanned by addressing pixels along the path of one vector (the 
Fast vector), Starting from the destination origin (after 
indexing, if selected), until it is exhausted. Then, using the 
next pixel on the path of the other vector (the slow vector) as a 
new origin for another fast vector with the same DX and DY, fast 
vectors are scanned until all the pixels on the slow vector have 
been addressed. Thus, parallelograms of any size or rotation can 
be scanned. Parallelograms can be used to scan rectangles on 
screens having nonsquare pixels. 


Figure 3-17 Example of Destination Rasters 


Functional Description 


enone ez Uae 


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The 

Algori 
vector, 
"major 
According 
along the 
axis. The 
point on 
The last 
one pixel 
the last 


Rel 


Ss on the path 
hm . j 


two 
anerally 
2 F 5 
am 


pi 
Lt components 


path 
origin 
any 
point 
too. 1 
point (it 


and all points 
vector I 

is 
ong) 


s fi point) 


would be restored to its original s 


po yr rt ion 


»les and Duplications 


Using this scanning technique for the 
Slow vector combinations will cause 
pera .lelogram to be addressed more 


ia 
nations 
5 


some pixels 
both effects 


Cause 
Caus 


18 111 
a 
am. 
2ate duplications, 


wi 
ns wi 
ve 


* — 44 


As 


vectors 
ns (0, 
3 vectors 


one hes the vectors points 
irections, duplications will 
ector is in one of the two 
two ectants adjacent 
irection. 


LS 


desti 

some 
than 
to 
or 
The Following combinati 
shown 


1 


Ohe 


cond time. 
tate during complement writing. 


lling down, 


of the vectors are computed by Bresenham's 
(DX and 
longer than the other and is called the 


DY) of a fast or slow 


called the "minor axis“, 


the number of pixels selected 
a eae is 940181 to the length of the major 
put 
igintdelta") 


not including, the last 
are selected. 
vector would be 
Should not select 
Otherwise, a pixel 


corrected for the 
it can address any 


and is 


Some fast and 
within the 
once. Some vector 
missed, and other 
er e within 

of fast and slow 
gure 3-18. 


nation, 
pixels 


88 


be 
eith 
14 N 
Fi 


ne 
in 


of the eight cardinal 


no duplications will occur 


in 


adj 


te 


same 


one of 
occur 


or opposite direction. 
the eight cardinal 
only if the other 
octants, or one of 
opposite cardinal 


acent 
the 


e 


Slow Vectors that 


os. Tf neither vector points in a cardinal direct! 
5 


duplications will occur unless the vectors 
perpendicular“ octants, that 
intervening octant. 


octants separated 


oF 
ieee 
a 

= 


Note that no rectangular area of any « orientation (on a scre 
square pixels) will cause duplications Duplicated pixe 
problems for a complement operation, but one would expe 
overlapping of data when an image is compressed by a! 


1 . . 
above conditions, or is scaled down. These complement problems 


be minimized by doing transformations in off-screen memory without 
1 5 1 e 


1 


complement mode, and then copying the results to the 
screen without a transformation. The video processor chips 
two sets of control registers to support repeated 
operations. 


Figure 3-19 shows combinations of fast and slow vectors 
create holes. 


1. If either of the vectors is parallel to the X- or 
oles can occur. 


2. If neither of the vectors is parallel to the X- or 
1 will be generated only if one vector is 
uadrant adjacent to the quadrant containing the ot 


ed in images, e 
ing can be disab! 


Figure 3-19 Example of Fast and Slow Vectors that Leave Holes 


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ar 


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Functional Description 


r NS SRA 


of the source slow vector is the result of the length of the 
destination slow vector multiplied by the slow scale factor; the 
sign is determined by the sign of the source DY register. 


A fast or slow scale factor is a number less than 1 with 
indication of up or down scaling; it is stored ina aaa 
register. The MSB (bit 13) indicates up- or. down~scaling 
magnitude is specified in the remaining 1 

point preceding bit 12. On each computati 

slow), the address processor chip increments either the source or 
destination vector, adds the scale factor plus 0.0000000000001B to 
an accumulator (initialized to zero) and, if bit 12 of the 
accumulator overflows, increments the other vector. If up-scaling 
is specified, the source is incremented only when the accumulator 
bit 12 overflows and the destination is incremented. The reverse 
is true if down-scaling is speci : 


3 bits, with the binary 
on of a vector (fast or 
t u 
1 


One pixel from the small vector may map to more than one pixel in 
the large vector. This results in nonuniform sampling of the small 
vector during the scaling process. 


The scaling of fast and slow vectors is independent. Down~scaling 


causes pixels in the destination to be written a multiple of 
ee If complement writing is used, 2-step operations using 
off-screen memory may be used to obtain correct results, as 


. above for duplicate destination pixels. 


To ensure expected operation of scaling for rational scale 
factors, it is necessary to round up any scale factor that has a 
remainder beyond the 13th bit from the binary point. This ensures 
the first pixel is not read one time too many. However, the 
address processor chip adds 0.0000000000001B to each scale factor. 
Therefore, a scale factor with a remainder should just be 
truncated, and any scale factor without a remainder (such as 1.00) 
should have 0.0000000000001B subtracted from it. 


Due to the 13 bits of ete sion available, inaccuracies can exist 
in large scale factors. This problem becomes aianiticant when the 


number of significant bits in a large scale factor is reduced to 
near or below the binary order of magnitude of the size of the 
source or destination in a scaled operation. 


The first source rectangle is scanned by starting at the ssh 
(after indexing, if selected) and selecting pixels along the fast 
vector (X direction) until the des tination fast vector is 
exhausted and the fast scale accumulator allows incrementing to 
the next destination pixel. (The latter condition ensures correct 
down-scaling for the 1 destination pixel.) Then, if the slow 
scale accumulator allows, using the next pixel on the slow vector 
(Y direction) as a new tats for another fast vector of the same 
length, additional fast vectors are scanned until the destination 
slow vector and slow scale accumulator are exhausted. Because the 
first source can be indexed and is corrected for the effects of Y 
offset used in down-scrolling, it can address any portion of the 
bitmap memory. 


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Functional Description 


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Figure 3-20 Tiled Areas 


The address processor chip achieves this effect by restricting the 
height and width of a pattern rectangle to integer powers of 2, 
adding only the low-order bits of the destination X and * 
addresses (before indexing) to the xX and Y components of the 
source 2 origin to create the source 2 X and * addresses. When 
tiling is enabled, the effect of the source 2 origin is more like 
that of a pointer to the origin of the tile than that of an 
offset. If the destination is indexed, the phase of the tiles will 
drift across the bitmap with changes in index value. This is a 
desired effect because it allows patterned objects to mesh 
properly, even if they are written at different times to a region 
that is scrolling. 


The height and width of a tile are independent of each other and 
range from 272 to 2°9. The tile width may never be set to less 
than the bus width (16 bits for the VCB02), but 4~ and 8-bit-wide 
tiles are possible in 16-bit mode by repeating the tile elements 
within the tile cell. Tile origins must be on word boundaries in 
the memory. 


As with the second source, no scaling or rotating of tile patterns 
is provided because the address processor chip is not capable of 
the calculations required to determine the starting phase of the 
resulting pattern. If scaling or non-power-of- tvo tile sizes are 
required, the pattern can be written more slowly by calculating 
the phase in the MicroVAX CPU, and using linear patterns to write 
one scan of the patterned area at a time. 


Functional Description 


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Jace One Video Processor Chip - Data Manipulation -- The video 
processor chips perform the actual manipulation of the memory data 
accessed by the address processor chip. This consists of aligning 
the source data bits with the destination location, communicating 
this data to its own logic unit and/or to those of other video 
processor chips, and modifying the destination data with the logic 
unit. Figure 3-21 shows the rasterop data path for video processor 
chip functions 


. 
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Figure 3~21 Video Processor Rasterop, Block Diagram 


Functional Description 


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Barrel Shifter ~ Bit Alignment 

During a bitmap memory read cycle, the barrel shifter accepts a 
32~bit input and provides any contiguous 16-bit segment of this as 
an output. Both words of the input can be the current word being 
read, or one word can be the current word and the other a previous 
word held in one of two delay registers. Fast mode operations 
require the latter ability to avoid excess reads to the source. 
One delay register is always associated with the first source, the 
other always with the second source. The output of the barrel 
shifter can be directed to the source or mask registers on the 
video processor chips, and/or to the I/D bus for broadcast to the 
other video processor chips or the address processor chip. Only 
one video processor chip can drive the I/D interconnect during any 
Source operation. 


The address processor chip provides the shift constants. For the 
first source, the shift constant is the difference between the 
Source and destination pixel addresses (low 4, 3, or 2 bits of the 
X addresses) after indexing. If selected for the second source, 
the shift constant is simply the difference between the low bits 
of the source 2 X origin and the X index, when selected for the 
destination. 


Logic Unit and Source/Mask Registers 

During a bitmap memory read-modify-write cycle, the logic unit 
combines the contents of the source register (loaded with a 
constant during a preceding source read cycle) with the current 
contents of the destination memory location. Any of the 16 
possible bit-wise logical combinations may be requested. The 
output of the logic unit selects, on a pixel~for-pixel basis, a 
foreground or background color to form new destination data. The 
foreground and background registers are usually loaded explicitly 
by the MicroVAX CPU, a Z-axis load, or an ordinary load. They are 
also loaded implicitly during a Z-mode processor<to-bitmap 
transfer. 


When using a full-resolution binary pattern (such Ss a text 
character or vector path) to write into a low-resolution plane, 
adjacent pattern bits must be spread so that all the bits of a 
low-resolution pixel are either on or off. This is accomplished by 
resolution mode logic between the source register and the logic 
unit. This logic ORs the adjacent 2 or 4 bits in 2— and 4-bit 
modes, respectively. If any of the bits in the group is a 1, both 
or all four bits of the group will be ls at the input of the logic 
unit. A programmable complementer between the source register and 
the resolution mode logic spreads the ls or the Os in the source. 
If an operation requires moving data that has already been 
expanded to low-resolution colors, the resolution mode logic can 
be disabled. 


Ba 


Functional Description 


r URED NEU ute , iON 


Two mask registers are provided to control which bits in a 
destination word are to be modified. These registers are loaded in 
the way the source register is loaded. Loading the mask 1 register 
also loads the mask 2 register with the same data, so that only 
one mask is effective. Mask 2 may be loaded independently when two 
masks are required. Either a mask value or its complement may be 
used. 


The address processor chip provides a special mask (called the 
edge mask), via the I/D bus during read-modify-write cycles, to 
define the bit or segment of a word involved in the current 
rasterop cycle. All these mask words are ANDed together, so that 
only bits 5 by all three masks will be modified. Bits in 
the range of a rasterop but not addressed by the address processor 
chip cannot be 1 When no mask is being used, mask 1 should 
be loaded with all ones and both e should be turned 
155 to prevent masking of destination bits. If only mask 1 is 

sed, the complementers for both mask 1 and mask 2 should be set 
50 the same state, or else all bits will be masked. 


Control Store and Function Registers 

Pe provide flexibility in the sequencing and operations of 
Sterops, each video processor chip has two memories that define 

i functions. The control store RAM provides 6 locations, each 

of which define the data transfer functions to be performed on 

each memory cycle of a rasterop: 


1. Where to send the read data from the barrel shifter 
(source, masks, I/D interconnect) 


2. Where to send incoming I/D data (source, masks) 


3. Whether to capture the read data in one of the delay 
registers that precedes the barrel shifter. 


There are two banks of control store RAM, with three locations 
each. The first location of each bank controls data transfers 


during a source 1 read, and specifies the control of the delay 
register for the first source. The second location controls 
transfers during a source 2 read, and specifies the control of the 
other delay register for the second source. The third location 


controls the destination read-modify-write. 


The two banks allow eas * switching between two functions without 
the need of reprogramming the video processor chips (as when a 
Function that must be performed with two rasterop steps is 
executed repeatedly). The address processor chip selects which 
bank to use (as specified by the MicroVAX CPU), and also defines 
the sequence of source and destination accesses. (The sequence is: 
source l, source 2, and destination, if enabled.) 


The control store RAM is required because the video processor 
chips often perform different operations at sia same time. For 
example, during text operations, one video processor chip will be 
reading the font and transmitting it on the L/D bus, while the 
other chips will be receiving the font from the I/D interconnect. 


338 


Functional Description 
CCTV 


The second memory bank of the control store RAM controls the logic 
unit, source resolution logic, and mask registers. This RAM has 
four locations of eight bits. Four bits select a logic function 
for the logic unit; two bits select normal or complement for each 
of the two masks; the last two bits select normal or complement 
for the source register, and enable the source resolution mode 
logic. This RAM is also addressed by the address processor chip 
during rasterops, as specified by the MicroVAX CPU. These 
registers permit convenient transitions between tasks requiring 
different logic selections, such as writing normal and reverse 
text. Four registers allow two orthogonal functions to be 
programmed. 


3.3.6.3 Processor-to-Bitmap and Bitmap-to-Processor Transfers 
Processor-to-bitnap and bitmap-to-processor transfers are similar 
to rasterops, except that either the source or destination is the 
MicroVAX CPU memory. Processor-to-bitnap transfers are called 
PTBS, bitmap-to-~processor transfers are BTPs, and transfers of 
either type are called PBTs. All data for a PBT is transferred 
through the 6-deep I/D data FIFO. The two modes for PBTs are 
X-mode and Z~mode. The second source, scaling, and rotation are 
not available. 


In an X-mode PBT, data from one plane is transferred to/from the 
MicroVAX CPU memory, with 16 adjacent bits in X occupying one 
word, followed by additional Xx words, and then by additional 
scans. 


In a Z-mode PBT, all the bits from one pixel location are 
transferred to/from the MicroVAX CPU memory word, followed by 
additional pixel data along the fast vector, and then by 
additional scans. Since a VCBO2 video subsystem can have a maximum 
of 8 planes, the DMA gate array can be used to pack/unpack data as 
it is transferred to/from the MicroVAX CPU memory. Compressing the 
data reduces the memory required to store an image, and reduces 
the bus bandwidth required to transfer the data. 


A PBT transfers a continuous stream of data words to/from the 
MicroVAX CPU memory, either through the MicroVAX CPU itself or 
through the DMA logic in the DMA gate array. The data words are 
written/read by the hardware along the path of the 
destination/source fast vector, until exhausted, and then along 
additional fast vectors, starting at points along the path of the 
Slow vector. Depending on the sophistication of the transferring 
device, these words can be all sequential in the MicroVAX CPU 
memory, or each fast vector's data can be indexed to different 
points in the MicroVAX CPU memory. The latter action could be used 
to access a rectangle of data within a larger rectangle already 
formatted in MicroVAX CPU memory. However, such indexing is an 
externally supplied function, not a part of the address processor 
chip. 


s=32 


de 


r e ms t , t t RNSNRINiRDNSiNINNNiRiCREonNONHNAORNNAIONI: 


Functional Description 


In general, it is possible to execute PBTs while scrolling. X- mode 
transfers are restricted from use in a region that is horizontally 
scrolling because the number of words transferred depends on the 
alignment of the rectangle being transferred to the memory words, 
which changes during horizontal scrolling. Z-mode transfers have 
no restrictions during scrolling. 


ling region (or in any on-screen location if some 
part of the screen is scrolling down) must operate continuously, 
adhering to à maximum time between words transferred. If a 
transfer becomes delayed, address calculations for scrolling 
become invalid, and data will transfer to/from the wrong screen 
location. There is no such problem for PBTs in off-screen memory. 


PBTS in à scrol 
4 


It is recommended that the MicroVAX CPU compute exactly the number 
of words that will be transferred by the hardware with a PBT 
command. For a Z-mode transfer, this is Simply the width 
multiplied by the height (in pixels 3) of the area bein 25 
transferred. For an X- mo de transfer, the width calculation depen 
on the width (in pixels), the bus width mode (16 bits for 5 
VCBO Z), and the indexed x origin address. If exact calculations 
are not possible, too much data is accommodated by harmless 
additional reads or writes to the FIFO. However, if too little 
data is transferred, the address processor chip will not be 
Satisfied, requiring a agi command (or more data) to continue 
operation. The ability to cancel a BTP operation is useful when 
the MicroVAX CPU scans the bitmap data for a Se gaan set of 
values, stopping when such is found. This is useful for a polygon 
Flood operation. 


i 
5 


Ea 


3.3.6.4 Performance — When no scrolling is in progress, 
destination-only and single-source rasterops are compute-bound in 
the address processor chip; therefore, they operate at 
approximately 500 K cycles/s (compute cycle rate). Rasterops with 
two sources are memory cycle-bound and operate at approximately 
400 K cycles/s (de epending on screen format). Cycles operate on 
either single pixels or words, depending on whether the conditions 
for fast mode exist. The address processor chip requires four 
compute cycles to initialize each rasterop. 


If the whole screen is scrolling up or sideways, or any area is 
down=scro soe all rasterops are memory cycle~ bound. 
Destination-only rasterops operate at 300 K to 400 K cycles /s. 
Single- source rasterops operate at approximately 200 K cycles/s, 
2-source rasterops operate at approximately 150 K cycles/s. 
Partially scrolling screens (except down-scrolling) have update 
speeds between the nonscrolling and full-scrolling speeds. 


— 
i 
S 


Functional Description 


„„ r r . e ROOMBA HAR OH RTO RH AOAIDD: 


One additional performance limitation applies to update 8 to a 
region that is in motion (scrolling), or to any region when 
down-scrolling is in „ Normally, when the screen e 
and scrolling process passes an area on the screen where updates 
are taking place (or source data is being read), the update 
process is temporarily halted while the refresh process passes to 
ensure that only old indexes are used below the refresh pro 

and only new indexes are used above. 


cess, 


This delay is necessary because the address processor cannot 
predict precisely when a computed address will be output to the 
memory. Normally, this causes an unnoticeable decrease in upda 
speed. However, if the update process is proceeding down the 
screen faster than the refresh process (this can happen if few 
than eight memory cycles, depending on screen format, are require 
to write or read all the data at each Y address; e.g. vertical 
ors), the update process will not be able to pass the refres sh 
he refresh process. 


t 
process. This limits progress to that of tt 


To eliminate this effect, it is recommended that a tall, thin 
rasterop be written from bottom to . rather than from top to 
bottom, in a region whose height is a signific cant portion of the 
screen height. This limitation does not apply when the new and old 
indexes are equal (or if they are disabled for both source and 
destination), and the Y offset is unchanged from that of the 


previous frame. 


Ce ee Application to Text 

Normal rasterops are used to write characters. The address 
processor chip contains no additional hardware to assist in the 
display of text. This section describes common text procedures, 


3 Font Storage and Access — Fonts are storec 
undisplayed portion of the bitmap. Ordinarily, a font needs 
stored in only one plane. It is transmitted from that F 
itself and others when a character is written. This results 
writing of monochromatic characters (all of one foreground 
and one background color) in the bitmap, as is normally desired. 
If multicolored or gray-scale (for anti-aliasing) characters are 
desired, the fonts can be stored across many planes. 


Characters may be stored anywhere in the bitmap (though normally 
in off-screen memory). However, a character occupies a 
2~dimensional space in the memory, described by height, width, and 
an X and Y origin. Thus, font storage in the memory must be 
allocated in a 2-dimens ional fashion. Normally, the MicroVAX CPU 
keeps a table where it can look up the origins and widths of the 
characters in each font. While character she ie may be on any 
pixel, faster operation results if characters are left-justified 
in bitmap memory word cells (16-bit words): | 
left-shifting is required, resulting in fewer source reads. 


the 
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3-42 


Functional Description 


c NSAI AATIN MANADO HBO AN 


een 


aS I 


4. This process is repeated until the text is exhausted or an 
attribute change is required. 


The speed of text writing in this mode varies with the character 
size; but, for 9-wide X 15-high ella about 20 K chars/s can be 
written, if fully supported by the MicroVAX CPU. The speed ranges 
from 15 K to 25 K chars/s for other useful character sizes. 
Because a full-page screen contains about 6000 ma a 300 ms 
are required to fill the screen with characters. Adding aan 100 
ms to clear the screen, but considering that an average text page 
really only contains about 3000 characters, about 250 ms will be 
required for a 'nen page“ of average text. Obviously, if the 
MicroVAX CPU is not able to process characters as fast as the 
hardware can take them, the processor will determine the over 
performance. 


3.3.7.3 Variable-Pitch Text -- The MicroVAX CPU uses any selected 
technique ae compute the character spacing. Obviously, fixed 
spacing is useful in many applications. Variable spacing is used 
to justify a line of text by spreading extra pixels throughout the 
line. One computation involves finding the "real" number (integer 


and fraction) of pixels for each character (or space e). Then, each 
character is spaced by the integer number of pixels, plus one more 
pixel, if the fractions have accumulated to more than one. This 


Egor the also allows any non- integer, but otherwise fixed, pitch 
to be simulated. This is 5 for compatibility when dumping the 
bitmap to a dot-matrix . 


A variable-pitch font is displayed with a different spacing 
each character (read by the MicroVAX CPU from its ge . 
This is accomplished by c changing the destination origin t 
DX or the destination origin only. The first way allows Font 
to be stored compactly, with the characters only occupying “their 
width in the memory. However, the speed is somewhat reduced 
because the MicroVAX CPU must wait for the previous rasterop to be 
completed before it reloads the Dx register and starts a new 
rasterop. The second way allows the same speed of operation as for 
fixed-pitch text, but the characters probably need to be stored in 


cells the size of the largest character, so that portions of 
unwanted . are not copied to the screen. Some loss of 
speed result from copying larger areas. If overstrik of 
5 characters is performed, care should be to 


center smaller characters on top of the largest one, and Ee. pas 
to the next character by the largest space. 


If the pitch of any character is larger than the destination fast 
DX setting, care must be taken to clear the area between 
characters that is not covered by the rasterops. This can be done 
by clearing the area of the text line before writi ing the character 
string. 


The performance of F text is similar to that 
described for Lied -pitch text above. 


ay of rotated 5 „ 
ext, except 
ot be paral a: 


and eae Text — Displ 
to the for nornal t 
8 n 

1 


* =) 


a and 8 vecto need not 
respectively, and ae scale factors need not i one. 
rasterop defaults to one pixel at a time. For a 
ar text cell, the fast DX and DY are chos sen to be 
| to the desired angle and Size. (The 
ages along the 45 degree axes may meee: to be 
Figure 3-22 shows examples of scaled and rotated 


made pitch text, 
l parts and Y that 
seline ee Using real position 
ulat ; ientatic r scale of 
the i will be within one pixel 


a  £ixed- -pitch text 
of their intended pos 


scaling cannot be expressed in terms of 
oy ers becaus of the „ number of pixels/ character. 
rhese 555 can 8 written at 500 K pixels/s, taking 1.7 s to 
1 
ah 


11 a 840 K pixel screen. 


This is NORMAL text. 
thio d@ ITALIE text, 


This is 1.3 SCALING. 


15 


Figure 3-22 Text Scaling and Rotatio 


n Examples 


Sates 
i 
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Functional Description 


tei eee aOR Eo etl ea ROU aN al AOI aa OU ge UA oo BOD UG him Go MST ST a nO GR La ESE HE DR URNS NOD ARENA IRON 


. Character Attributes — To set the character attributes, 
appropriate address processor and video processor chip re 
are loaded; all characters retain the current attributes ur 
Settings are changed. However, only the registers fo 
attributes that actually change between strings need to be 
But, if a permanent display list is being maintained, it ma: 
desirable to reset all the attributes periodically (maybe 
beginning of each line). The following list describes the int 
implementation of attributes. 


1. Reverse — Reverse is a specific case of a more general 
class of attributes that modifies the logic function 
being performed on the destination data. Tw ts are 
provided in the address processor chip comm _to 
address one of the four logic unit fu 
complement registers in the video processor chi, 
function st ada could be set to the current defini 
of revers and some other function (such as switching 
from 8 mode to overstrike mode). 


0 
anc 
ne 
‘th 


ex Underscore — An underscore can be drawn as a vector of 
the desired thickness, and linear pattern mode can be 
used if a dashed or other patterned underscore is 
desired. Another technique would be to overstrike e 
character with another character having an underscore. 


3. Overstrike — Overstrike may be accom 
appropriate loading (or not ee ng) of the 
origin register and the us of OR writing 
characters from vari fable-pitch ‘cents are overstr 
must be taken in positioning. 


iba fae 
ae 


4. Invisible — The pen up bit in the address processor chip 
mode register may be used to disable writing, o 
MicroVAX CPU can simply omit any text strings that 

nvisible If erasure of the invisible area is desired 


5 


i 
this must be performed explicitly. 


Ds Intensity, Color and Blink ~~ These are Z-axis paramet 
implemented through the color map. To enable writir 9 i 
appropriate color in the bitmap planes or subplanes, a 
Z-axis I/D bus command accomplishes a Z-axis load of é 
video processor chip foreground and/or backgrc 
registers. This sets all the F/B bits in 98 plane or 
subplane to either 1s or Os. Source patterns are then 
loaded (via the video processor CSRs) either ae a video 
processor chip mask register to ac eee 
writing, or into the source regi 
replace mode writing. 5 bl 
by periodic writing to the bitmap. 


und 


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Functional Description 


ß i NU r r RT UGS CANE EN 


Linear patterns are created by setting the address processor chip 
mode register to linear pattern mode. This unc ouples the source 
and destination initialization from each other. The source Dx 
(fast) and DY (slow) registers define the size and scanning 
direction for the pattern. (The magni tudes of the DX and DY 
registers are significant in this mode.) The size of the source 
pattern can be any integer in either 8 fast or slow directions. 
The path of a patterned vector is defined by the destination slow 
vector, and the width of the vector by the destination fast 
vector. Any fast or slow scale factor may be used in the normal 
manner. Linear patterns never operate in fast mode. 


Linear patterns operate in the following manner. 
8 As the destination scans its fast vector, the source 
provides pixels from its fast vector (as determined by 
the fast scaling). 


2. If the source fast vector expires before the destination 
Fast vector, the source reinitializes its fast vector at 
the origin (slow vector point) last used. Thus, the 
source scans its fast vector as many times as requir red to 
cover the length of the destination fast vector. 


st vector expires, the urce and 


ay When the desti fa 30 
510 eters are incremented (as e 


„ 8 


4. Both the source and destination fast vectors are 
initialized to the resulting new slow points. Fast 


scaling is also initialized. New fast vectors are 
scanned. 


If the source slow vector expires before the destination 
slow vector, the source slow vector resets to the source 
1 origin, and the whole source repeats again. 


é 
. 
= 


6. When the destination slow vector expires, a new 
destination vector can be initialized without disturbing 
the state of the source slow vector or the slow scale 
factor. However, if desired, loading a new source origin 
causes the source and slow scale to be initialized also. 


The result is that a 2-dimensional pattern is scanned by th 
source transferred to the position, direction, and scale of 
destination. If it is desired to scale the pattern so its 
along a diagonal is the same as along an axis, the scale pias 
will need to be loaded along with each new destination fe 
slow vector. Appropriate linear patterns for texturing vecte r 
normally coarse-grained to reduce the effect of sampling errors 


inherent in rotation and scaling. 


3~49 


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Functional Description 


d ß TTA ins eiNNN Ni iii 


SNE 


Scanning is always from one vector (A) to the other vector (B), 
even if the vectors cross. (In such a case, the fast scanning 
direction reverses at the crossing and continues to fill the space 
between.) The last fast scan between the last point on any vector 
and a point on the other vector is not plotted (except under the 
conditions that cause doubling). This is similar to a normal 
rasterop, for which the first, but not the last, point is plotted. 


A polygon to be filled entirely must be divided into two parts 
that can be directly filled by the VcBO Zz video subsystem hardware. 
Each part is i 
i 
x 


irec 

s intersected twice by every line that is parallel to 
the fill ax (excluding edge intersections, or edges parallel to 
the fill axis). If the border of a piece is traversed from the 
topmost ee vertex for an X (Y) fill axis, there is only 
one reversal direction along the Y (X) axis. Figure 3~25 shows 
an example of 5 polygon that meets the preceding conditions for an 
X fill axis. To fill such a polygon: 


51 


ke The address processor chip is set to fill mode, with X 
fill, not baseline mode, source 2 parameters as required 


(if used), and video processor drawing modes as required. 


Be 


. One side of the polygon (from the uppermost point top“ 
to the lowermost point bottom“) is designated side A; 
and the other side is designated side B. It does not 
matter which side is designated A or B 


3. The vector strings that represent each side of the 
polygon are expressed as DX and DY pairs to the next 
point (as with ordinary vectors). (See the AO in Figure 
3-25.) After an initial origin load, all vectors are 
relative. 


4. The vertices from both sides are sorted as a single group 
by increas ing the Y coordinate. If a vertex on each side 
has the same Y value (always the case at the top and 
bottom), the A and B vertices are sorted as a pair. In 
the example: A0O/BO, Al, BI, A2, A3/B2, A4, and A5/B3, 
A3, A4, and B2 all have the same Y coordinate. 


WP 
2 


The DX, D pairs are sorted as single vectors or 
pairs according to the order determined by sort: 
vertices. (Actually, the vertex information is used 
to determine this vector order.) In the 5 
AO (DR: DY)/BO (DX: DY) . AI (DR: DT) . , B32 (DR: Dr) 1 
A4(DX:DY). (No vectors start from A5 or B3, but a n 
A (0: 1/5 (0: 1) vector pair may be added at the point A5/B3 
to complete the last scan of the polygon.) 


3~5] 


Functional Description 


F ͤ e d i OO ii iii nie in i i ition ania ip Gsm aN EGS on CORA 


6. The destination origin registers are loaded with the 
Start point (A0), and the source 1 X origin is loaded 
with the X component of the origin (BO). (Actually, BO 
need not be the same point as A0, assuming they both have 
the same Y coordinate. The source 1 Y origin register is 
ignored for X fill. The roles of the two source 1 origin 
registers are reversed for 1 fill.) 

ce The first vector pair is loaded into the destination slow 
DX and DY registers (A vector) and the source DX and DY 
registers, (B vector, the magnitudes of the source DX, 
and DY are significant in fill mode.) 


8. The address processor chip command register is then 
loaded with a rasterop command, including a source 2, if 
needed. Source 1 should never be enabled in fill mode. 


9. The space between the two vec 
hardware) parallel to the X-ar 
advanced synchronously in Y. 


‘tors is filled (by the 
‘is as the vectors are 


ip is 
1 
1 


lO. When the address processor chip signals that it needs 
more data (rasterop complete flag), the MicroVAX CPU 
loads the next vector or vector pair in the 1 into the 
appropriate vector registers (A to destination slow and B 
to source 1). The MicroVAX CPU then loads the address 
processor chip command register again, continuing with 
the previous step until all required vectors are plotted. 


ll. The process is terminated when the MicroVAX CPU loads new 
dat iT the destination origin registers (which causes 
d) i 


data into t 
the positions to be reinitialized), or switches the 
address processor chip out of £ill mode. 


Fill with Complement Mode 

The procedure above plots all the points that would have been 
plotted by the edge vectors, plus all the points between. However, 
some of the points are plotted more than once, creating potential 
problems for complement mode operations (any operation that XORs 
or uses the complement of the destination). The MicroVAX CPU fixes 
this problem (for most of the important cases) by forcing that all 
pixels to be written an even number of times actually be written 
an odd number of times (ordinarily, writing doubled pixels a third 
time). 


ie 
i 
BS 


dude mme 


Functional Description 


igen RON TSN 


i 


VERTEXAO —~__ top | 


eee 


Wis 


AO DN 


2 „ = sa = see ee 
x FF 
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VERTEX A- 


ne en ee ee ee ee e, ee, ue, a 
e 


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A SIDE — A N „ - VERTEX B1 
at / if ; / 


* 
be pvc sy. gor. A, Ip La wn 
VERTEX A2 —— 


~~ VERTEX B2 


— 


VERTEX 232 


VERTEX AA — Use PARALLE 
ra 5 


U 
TO X INTERSEC) 
AT TWO POINTS 


05 


E 
5 


22 


VERTEX AS ae til j VERTEX 53 


BOTTOM 


e 


Figure 3-25 Example of a Polygon Fill 


Functional Des 


duenne 


cription 


b 


oade 
ahether 


time an A or 
the vector 


occurs each 
vector or 
expired): 


Doubling 
previous 
has also 


B vector 1 
on the other side 


"inbound" (approaching the other 


Has its major axis parallel to the fill axis 


which 


following ic 
ctor whege: 


the minor 
dressed. 


equation, 
axis of a ve 


of the distance, 
Start of 
the 
95 
of th 


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sum of the 
t has expired, 

e vector 
55 of 
vector bei 


bets 
ae 
See 
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pee 
. 


maqnitude of the minor 
vector being tested. 


that 


to the th 
major:m 


slope Ir 
axis 


According 
inbound 
major 
Any othe 
substituti 

a vector “that is 
Slopes greater chan 
for slopes less 
evaluate for slopes 


ons above, any ver 
than or equal 
8 the fill direction a 
“or never 
for is minor 
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acer EO 26h, 


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roe. 


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sie 
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doubling occurs, it 
xt vector with 
ength vector outk 


Ss fix is 


corrected (tripled) 
igth K | 
90 th 


ne: and 


i. a 
sides 


e 


50 


th applied ectors. 
complement mode corrects 


This extra procedure for 
t ‘tances. If the two edges 


E except in two circums 

uncorrectable doubling may occur on one scan. 

normally avoided except in baseline mode.) 

stated 88 s followed by an outbound vector that 

slope tion, the pixels common to the 

itboard of th Flex are doubled. If necessary, 
compu the MicroVAX CPU and 


— 2 


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Functional Description 


api ies NTT eG NG a ei io ga NE OC ii i ia ee a a Cn a aOR F RE ORE oN DR ODER 


A an example of correction of doubling of pixels (see Figure 
3~25), assume that vectors Al (from Al to A2) and A3 (from A3 to 
A4) are the only two inbound vectors with a slope flatter than 

Les ssume also that B2 (from B2 to B3) is the only vector that 
is inbound with a slope between 2:1 and 1:1, but there are no 
expirations of the A side during its length. If the doubling is to 
be * the following comple ete 1 list would be used: 
DK: ies veh DX D* Vy Al(DX:DY), B(-] 7 B (1:0), BI (DX: Dy), 
’ 5 ö A (1:0), A€-1:0), 
1)/B (O: 1). The last vector pair is used to plot the 
the polygon, if desired. 


2 


If two polygons are butted together (that is, one shares some 

edges with another), the common edges will be written twice. But 

because all the pixels on the edge vector have been written 

exactly twice, it is possible to ensure an odd number of writes to 

the edge pixels by writing only the edge vectors again (in the 
io i 


. 
same direction as when filling), including the last point on the 
last vector, 


seline Fill 
simplified fill mode is provided that fills from a single vector 
o @ither a horizontal (for Y fill) or vertical (for X £111) 
1e position of the baseline is programmed by loading 
the source 1 Y origin (for ¥ fill) or the X origin (for X fill). 
In addition, the source 1 DY must be zero for Y fill, and the Dx 
must be zero for X fill. In either case, the other delta must be 
nonzero. Only a single vector path is required, and the path is 
allowed to reverse the direction of its component that is parallel 
to the baseline ine t allowed with 2~line mode). However, the space 
between two lines that converge on a point from the same quadrant 
is difficult to fill in this mode. (Some products have provided a 
11 to a Borne function for this case, but this creates more 
oblems for complement mode.) 


With baseline mode, the same problems and procedures apply when 

92 complement operations, and if the vector path crosses the 

588 ine and then reverses direction (parallel to the baseline, as 

lling a circle. 
d 


€ 


when fi The baseline is written twice, as if two 


). 
polygons had been butted together, and the baseline needs to be 
drawn again as a Single vector to correct for the even number of 


writes. 


3.3.8.4 Polygon Flood -~ A flood operation colors or textures the 
interior of an area whose outline is described in the bitmap. 
This is in contrast to a fill operation. No explicit support for a 
polygon flood function is provided by the address processor chip. 
This function requires the path of writing in the bitmap to be 
conditional on the previous contents of the bitmap. In the 
hardware the path of writing is controlled by the address 
process sor chip, but only the video processor chips see the memory 


da t a il 


Functional Description 


ano 


r e ONS BURN Fie NNN 


Flood can be implemented by using the following commands. 
1. The processor/bitmap transfer facility is used to read a 
scan of the bitmap in Z-mode or one plane of the bitmap 
in X-mode. 


2. Each returned pixel value is checked for a match wit! 
set of boundary colors, and a count is maintained of the 
pixels received. 


3% When à match is f. 
1 nc 


ound, the BTP transfer Pics nated by 
oading a car 9 


is i - 
mmand to the address 0 cessor chip. 
ed pixels on the 
1 way. 


& 


4. A vector is commanded to write the desir 
scan with a color or pattern in the norma 


ui 
= 


The flood algorithm then steps to à point on the next 
scan, or continues at a previous seed point, in the 
normal way. 

The speed eof this operation is determined b 
time, plus the overhead time of the MicroVAX C 
$1 tgnificant if it takes more than 2 us for each comparis son, or if 
the flooded area is narrow). The drawing time is generally not 
significant as compared to scanning and decision-making. Using 
this 5 an empty full-page screen (1024 X 864) has been 
flooded in less than 2 seconds. 


the BTP scanning 
PU (which could be 


3.3.8.5 Objects — Ordinary rasterops can be used to move oe ete 
or Windows on the screen. In a multiplane environment, rectangles 
can be copied by moving the pixels in all planes, in parallel, to 
new ee locations in the same planes. This is referred to as a 
8 an entire rectangle is copied. The source 1 
, from either on or off screen. If a Source 2 
from off screen. 


ove an object (that is, alter only the destination pixels) 
ithin the ee ree of the object, the hardware must be able to 
5 between object and background. This can be done by 
ing the foreground OF the object in one plane. The area of 
Slane within the ra saa 5 is then transmitted to 
e other planes du 1110 the asterop for use as a mask that 
events the alteration of . pixels. This operation is 
158 MONE. Alternatively, the second source 

et from off screen, with “clipping” to 


wi 
di 
de 
th 
th 


5 8 8 8 RES 
in 
2.8 8 


Pr 
referred to as an ob: 
can be used to copy an 
the destination shape. 


AeA ee 


The paragraphs above described the movement of color objects 
(objects defined in more than one plane). It is also possible to 
move an object specified only by a foreground shape, and assign a 
foreground and background color to it at the time it is moved. 

This type of . is described in the section on writing 
text, Paragraph 3.3.7. 


#% 


unctional Description 


VVV 


3.4 ADDRESS PROCESSOR AND VIDE 
COMMANDS 
This 5 defines the interface to the address processor and 


O PROCESSOR CHIP REGISTERS AND 


video processor chips in detail. There are basically two types of 
commands to Bee hardware: direct commands to the address processor 
chip, and I/D bus commands, which are Bases through the address 
* chip to the video processor chips and chip select 


egisters. 


3.4.1 Address Processor Chip Registers and Commands 
All address processor chip commands are the results of address 
processor chip register loads by the MicroVAX CPU or the VCBO2 
video subsystem's DMA logic (in the DMA gate array). Before a 
description of the address processor chip commands and interface, 
the address processor chip registers are defined below. 


3.4.1.1 Address Processor Chip Registers ~- The address processor 
chip contains many loadable registers that hold parameters for 
rasterops, set system timing, and control the operation of the 
chip. Unless otherwise specified, the registers are write-only and 
contain 14 significant bits in 2's complement representation. 
(This includes the sign bit; two MSBs of a word are ignored, 

except for test purposes.) The loading of some registers causes 

the address processor chip to take specific additional actions. 
These actions are described with the corresponding registers. 


Different types of coordinates are implied by the various positio 
registers. "World coordinates" refer to the coordinate system 
image as viewed by the MicroVAX CPU before index values (i 
nabled) are added to translate the image to "device coordinates". 
Device coordinates describe a physical position on the s 
[0,0] is the upper left corner with X increasing to the right | 
* increasing downward. "Memory coordinates" are obtained 
internally to account for down-scrolling by adding the Y offset to 
all — to the on-screen part of the memory (any memory 
location accessed by a major read cycle for screen refresh), 
delineated by ‘the X limit and Y limit registers. 

The DMA logic in the DMA gate array loads registers n the 
register address counter, and thereby, loads several sequential 
registers. The register addresses are assigned to allow all common 
combinations of registers to be adjacent. This allows loading to 
be accomplished with a minimum of address register loads in the 
DMA data list (DMA display list). 


The register addresses (or the address of the first of a group of 
registers) are in hexadecimal and enclosed in brackets []. Where 
specified, bit assignments (or the LSB of a group of bits) are 


enclosed in angle brackets <>. 


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Functional Description 


iS 


Pause Complete -~ Set when the screen refresh process 
reaches the Y address (in device coordinates) that the 
pause register was set to when the current frame began. 
Cleared by writing a word to the status register with a 
0 at this bit position; unaffected by a l at this bit 
position or by values of other bits. This status bit 
will queue two pause events. Thus, if in one frame the 
pause register was set near the bottom of the screen and 
in the next frame the pause register was set near the 
top of the screen, both pause events will be separately 
detected, even if the second event occurs before the 
first event. However, this means that if the pause 
register is set within the active screen and the pause 
Status bit has not been cleared within the previous two 
frames, two clears will be required to make this status 
bit stay low. The pause status bit can be prevented from 
being set by programming the pause register to a value 
greater than that of the end vertical period event in 
the YCT- registers. The INIT pin clears any queued 
pause event, but one explicit clear by writing to the 
Status register is still required to set the pause 
Status bit low. 


Scroll Service (Frame Sync) — Set at the s 
frame, when new scroll parameters may be loaded. 
by writing a word to the status register wit 
this bit position; unaffected by a 1 at 
position or by values of other bits. This bit differs 
from the vertical blanking bit in that the latter is set 
at the beginning of the vertical blanking interval. 


t a e 
se cl i apn 


h 3 O at 
thd 


Rasterop Initialization Complete —— Set when 
initialization of a rasterop, processor-to- bitmap 
transfer (PTB), or bitmap-to- processor (BTP) transfer is 
complete. This indicates it is safe to load the source l 
and destination origin registers, or to load a new (but 
not different) rasterop (but not PTP or BTP) command. 
Cleared when any rasterop, PTB, or BTP command is 
loaded. Set by a cancel command or the INIT pin. 


Rasterop Complete -- Set when rasterop, PTB, or BTP 
address calculations are complete and no further command 
is pending. This indicates it is safe to load any 
rasterop parameters, such as: origins, DX/DY pairs, 
source 2 parameters, scale factors, and the mode 
register, or to load a new (but not different) rasterop 
(but not PTB, or BTP) command. Cleared when any 
rasterop, PTB, or BTP command is loaded. Set by a cancel 
command or the -INIT pin. 


Functional Description 


Hasina 


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Address Output Complete -- Set when all addresses 
calculated by all pending rasterops, PTBs, or BTPs have 


been used. This indicates it is safe to load any update 
parameters, including: clipping boundaries, indexes, I/D 
data, or different commands. In addition, during BTP 
(bitmap-to-processor) commands, this status bit does not 
go high until the IDD FIFO is also empty, indicating 
that all data transferred by the BTP has been picked up 
by the MicroVAX CPU or DMA controller (DMA gate array). 
Cleared when any rasterop, PTB or BTP command is loaded. 
Set by a cancel command or the INIT pin. 


I/D Data Receive Ready -~ Set if the I/D data FIFO has a 
data word available for reading. Cleared if the FIFO 
becomes empty. When a rasterop, PTP, ee or cancel 
command is loaded to the command regis ter or bus, 
initialization occurs, the FIFO is initialized, and this 
bit is cleared. Note that this bit is set any time data 
is in the FIFO (such as during PTB, BTP, or I/D command 
sequences), and should be masked when not used. 


I/D Data Transmit Ready ~~ This bit has four 
interpretations, depending on t. 
i 


h 
he commands being 
executed by the address processor chip 


a. When a rasterop, PTB, or BTP command 
the command register, the FIFO is ini zed and 
this bit is set. During a rasterop or Pi 2 command, 
this bit is set if the I/D data FIFO (6 words long) 
can accept an additional data word. The bit is 
Cleared if the FIFO becomes full. Though this bit 
responds during rasterop commands, T/D data is not 
used, and any data loaded remains in the FIFO during 
the command. 


Ss loaded to 
ali 


b. During an I/D command (after an I/D command has been 
loaded and until some other command is loaded), this 
bit is set if a new data word may be loaded to the 
I/D data register. Cleared when an I/D command is 
loaded to the command register. This bit should also 
be checked before loading another command after an 
I/D command. However, if at least three major cycles 
(one major cycle plus a sync cycle, about 3 us) pass 
before the new command is loaded, this status bit 
need not be checked. 


c. When a cancel command is loaded, this bit is 
momentarily set low When execution of the cancel 
command is e this bit is set high to 

indicate that the IDD FIFO is clear anda new 

command may be loaded. This bit should be checked to 
ec 


indicate completion of a cancel command. This is not 
required if at least Base: major cycles are 
guaranteed to pass befor the next command is 


loaded, 


Functional Descri iption 


siete aia So esi iia asec ai i ODS ei an La eae eon ia Oita Oia TROON NSIT d r 


d. If the I/D data register is loaded 
or BTP is not in progress (see 
or the INIT pin is asserted, 
initialized and this bit is set. 


<7> I/D scroll! Data Ready — Set if a new data word may be 
loaded to the I/D scroll data register. Cleared when an 
command is loaded to the I/D scroll command 


<8> A portion of at least one rasterop clipped at the top 
boundary. 

<9> A portion of at least one rasterop clipped at the bottom 
boundary. 


<A> A portion of at least one rasterop clipped at the left 
boundary. 


<B> A portion of at least one rasterop clipped at the right 
boundary. 


<C> A portion of at least one rasterop was successfully 

drawn (did not clip at any boundary). 

The preceding five clipping bits accumulate clipping 

activity by having clipping results for each destinat ie n 
write cycle ORed with their ae vious contents. These 
bits are asserted high. The last bit may be used to aid 
in selecting an algorithm by 5 that a rasterop 
was at least partly inside the clipping rectangle. 
Clipping information for a rasterop is complete after 
the address complete status bit is asserted. Reading the 
clipping status bits dur ing a yrasterop can yield 
undefined results. 


0 


i 


These five bits are selectively cleared by a write to 
the status register with a 0 in each corres ponding 
clipping bit position to be cleared, and a 1 in 
positions to be unaltered. Zeros or ones in ore bit 
positions have no effect on these status 1 Clearing 
of the clipping status bits during a 5 gives 
unpredictable results. These bits should be cleared only 
after the address complete status bit is asserted. 


A 
— 
* 


Vertical Blanking — Set at the start of the ver 
blanking interval. Cleared by writing a word t 
status register with a 0 at this bit positi 
unaffected by al at this bit position, or by values of 
other bits. This bit differs from the scroll service bit 
in that the latter is set near the end of the vertical 
blanking interval. 


[4] RESERVED — Test function. 


Or 


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(12] PAUSE (PSE) -- The Y device coordinate that specific 
scan that, when displayed, causes the pause status bit 
set or a second pause event to be queued. (See oe 
description of the pause complete status bit above.) Th: 
register is double-buffered so that comparison with the n 
value loaded begins at the start of the following frame an 
continues throughout that frame. Only the low 11 bits of this 
register are significant. 


131 Y OFFSET (PY OF) — Offset added to device coordinates to get 
memory coordinates. Decremented by the MicroVAX CPU during 
e ee ranges between 0 and the height of the 
displayed portion of the bitmap memory (the same value minus 
1 see below). The offset value loaded to this register 
should be the one in effect when the following frame is 
complete, and stored in the Y limit register, due to the 
multiple buffering of this register. 


ee 


[14] » SCROLL CONSTANT (PYSC) — Specifies the vertical distar 

to be scrolled in one frame time. Loading of this regis ny 
causes the region selected by the scroll boundaries to be 
scrolled during the following frame (by the vertical distance 
loaded to this register, or the horizontal distance loaded to 
the scroll constant registers in the video processor chips). 
If no value is loaded during a frame, no scrolling occurs in 
the next frame. 


co 12 Bits. The vertical magnitude (unsigned distance) of 
the scroll. If a nonzero X scroll constant is specified 
in the video processor chips, the Y scroll constant must 
be zero. 


<C> 0 = Up, left or right scrolling. 
1 = Down-scrolling. If down scrolling is specified, the 
scroll direction bits in the video processor chips 
should also be set to down and left. 


<D> O = Normal scrolling. The scroll direction bits in the 
video processor chips should be set according to the 
desired scroll direction. 

1 = Erase mode. The entire scroll region is cleared to 
the fill color regardless of the settings of the scroll 
constants. Up-scrolling must be specified in both the 


ae 


address processor and video processor chips. 


3-65 


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Functional Descripti ion 


igi ie a isa Ss oi e RENN NUNN SE I 


[lE] CLIP W MAX (CYMX) —— Bottom clipping boundary; the first 
pixel outside the bottom of the update region. 


Clipping boundaries are in device coordinates so that they 
are unaffected by the index values. Because clipping is in 
device coordinates, the clipping boundaries stand still on 
the screen during scrolling. Thus, they are not usable as a 
drawing function, but merely to contain the image within the 
borders of the scroll window. They affect whether or not 
destination data is written and the setting of the clipping 
Status bits. All rasterop calculations are still performed. 


[1F] SPARE 

Rasterop Control Registers 

(20] FAST SOURCE 1 DX (FSDX) — Fast extent for the fi 
n t 


irst source 
This can only be in the + or = X direction; there i no Y 
component. 


SOuUrCEe. 


[21] SLOW SOURCE 1 DY (SSDY) —— Slow extent for the first 
se in the + or - Y direction; there is no X 


This can only b 
component. 


Only the sign bit (MSB, bit 13) of the source 1 delta 
registers is significant in normal mode. (Even the signs are 
ignored if the source 1 is not enabled.) The whole value is 
significant in linear pattern and fill modes. In fill mode, 
only values in the range 2 “12-1 to 2 12 are allowed in the 
source 1 delta registers because thes e N are multiplied 
by 2 in some calculations internal to the address processor 
chip. 


[22] SOURCE 1 X ORIGIN (SXO) -~ X coordinate of the first source 
origin. 


[23] SOURCE 1 Y ORIGIN (SYO) — X coordinate of the first source 
origin. 


The first source origin components can be in either world c 
device coordinates, depending on the setting of ex moc 
for as first source. The loading of either - these 
registers in linear pattern mode resets the source pattern 
scan and the slow scale calculations. 


pers 

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oe 
a 
Co 
= 
m 


STINATION X ORIGIN (DXO) — X coordinate of the destination 


Functional 


don mov 


[25] 


[2A] 


Description 


ngs in Ung iy GROEN LRN 


DESTINATION Y ORIGI 
origin. 


The destination o 
device 


the destinati 


Fill 
ized. 
of the 


the first s 
any 


t 6 
sterop ini 


DESTINATION 
vector. 


DESTINATION 
Vector. 


DESTINATION 


Slow vector. 


DESTINATION 
4 510 ow vector. 
delta 
chip. 
(FSC) 
> 


rst source 


ante, deu 


SCALE 
first 


each F . 
caling (if a 
eek ed in th 
preceding bit i 
0153 t 
gnores the 
bic 


coordinates, 


mode 


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tie 


O each 


i eee enn een ele 


N (DYO) — 


rigin components 
sects ng 
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i 
On. i 
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vector 
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DX (FDX) -- 


DY (FDY) -- ¥ 


X 


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re Se ee 


calculations 


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On inf 


lati 
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Scale ees 
ne ne 


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factors 
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e remaining 1 
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scale 
factors 


scale , the 


scale 


enabled, 


Y coordinate 


can 
on the 
either of thes 32 


extents 
destination 

1 
loaded wi 


status 


X component of 
component 


component 


“~~ X component 


because these 
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a1 ing (if 
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factor. 
unle GS & 


of the destination 


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are re 


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to the address 


vectors of 
near pattern 


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low vectors of 
linear pattern 


* 

— 

or, 
a 


with the 
processor 

The address 
both the 


inary pater 
“Ente adds 
processor 
source 1 and 


[2D] 


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eee 


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[30] 


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7 


Functional Description 


SOURCE 2 X ORIGIN (S2K0) — X coordinate of the second source 
origin. 


SOURCE 2 Y ORIGIN (S2Y0O) — Y coordinate of the second source 
origin. 


The source 2 origins are added to the unindexed destination 
addresses (or low bits of them, if tiling is enabled). The 
second source origin components are always memory 
coordinates. The source 2 cannot be indexed and it is 
not adjusted for the effects of Y offset; therefore, it must 
be off screen. If tiling is enabled, the source 2 origin must 
be on a word boundary in the memory. 


SOURCE 2 HEIGHT AND WIDTH (S2HW) —— The contents of this 

register determine the size of the source 2 tile. 

40 3 Bits. Tile width (W) from 0 to 7; the width of the 
tile is 2 (M2) (from 4 to 512). 


<3> Reserved (normally 0). 


445 3 Bits. Tile height (H) from 0 to 7; the height of the 
tile is 2 (Hz) (from 4 to 512). 


<7> O = Tile height and width enabled; high bits of 
destination component truncated before adding to source 
2 origin. 
1 = Tile height and width disabled; all destination 
address bits added to source 2 origi 


ERROR 1 (ERRI) -- Error adjustment added to the error 
register during rasterop initialization for the slow 
destination (A side in f111 mode). 


ERROR 2 (ERR2) -~ Error adjustment added to the error 
register during rasterop initialization for the fast 
destination in normal and linear pattern mode, and for the 
source 1 (B side in f111 mode). 


Screen Format Control Registers 


Y SCAN COUNT O (YCTO) 


Y SCAN COUNT 1 (CTI) 


Y SCAN COUNT 2 (YCT2) 


Functional Description 


icici cia cain nemo SCG igi igi . . iii aii iG i iii iain 


[34] Y SCAN COUNT 3 (YCT3) 


These four Y parameter registers program all vertical timing 
for the VCBO2 video subsystem. Each register determines the 
time of one vertical event, such as the assertion of vertical 
blanking. The event is specified by the two MSBs (bits 12 and 
13). The low 11 bits determine the time of the event (scans 
for vertical synchronization events, and scans minus 1 for 
other events), starting from vertical unblank ing. The events 
are stored in the regis Sters in order of increasing time (low 
11 bits), starting in YCTO. The highest time value is 
programmed for the vertical period event. If the horizontal 
period is set for an odd number of major cycles (N odd, where 
"N" is defined for the horizontal period event, below), there 
must be an even number of scans in a frame. This is so there 
will still be an even number of major cycles in a frame. (The 

period event must be set to an odd number.) Vertical 
blanking is deasserted (set low) when the vertical period is 
reached. The bits of the Y scan count registers are assigned 
as follows. 


402 11 ae 
blanki 
scans mi 
Svenk is se 
ins 


ime of event from deassertion of vertical 
ans for vertical synchronization events, and 
for other events). The end vertical period 
to the number of scans in the frame, minus 


1. 
2 ct 


sit 


00 = End vertical period. Set vertical blanking low in 
ing scan 
ical blankir 
‘Cical sync lo 
ical sync hi 2210 


ng high. 


The VCBO2 video subsystem provides a composite 


synchronization signal. The vertical synchronization 
signal chooses between two events in the X scan counter 
that provide the variable-width horizontal 
synchronization pulse needed in a composite 
synchronization system. When using composite 
a Nae ei the vertical synchronization interval 


. 
3 be delineate 
hronization 8 
nehroni zatio 
i 


d by the high state of the vertical 
gnal, allowing the longer horizontal 
me to be determined by the "100" or 
X scan counter (see below). 


A sample assignment of events for a composite sync 
5 CTO sets vertical blank high, CTI sets 
vertical syne set 
low, and YCT3 set 
the vertical eounese 


, YCT2 sets vertical synchronization 
s vertical blanking low and restarts 


a 


Functional Descripti 0 


niece NR 


VVV 


A system synchronization request is generated by the 
address processor chip in the scan prior to the 
deassertion of vertical blanking (scan prior to the 
N displayed scan). The exact timing of the 
nroni za ation request within that scan is determined 
e X scan count registers described below. 
[35] X SCAN CONFIGURATION (XCON) 

<0> Bits. Number of major read cycles used for each scan. 
1is is normally set to the smallest integer greater 
han or equal to the number of pixels to be displayed on 
zach scan divided by 128. In the VcBOZ video subsystem, 
this must be set to 8 (1024/128 = 8). Memory refresh is 
accomplished approximately every 0.5 ms, plus any gap 
occurring during vertical retrace. See the discussion of 
the — ane XL registers for required relationships to 


— 
on 

i. 
2 
e & 


Bus width mode must be programmed here and in 
sssor chips before any bitmap memory 
is attempted. Once bus width is initialized, most 
operations are independent of the bus width. Exceptions 
are X-mode processor/bitmap transfers, source 2 tile 
origins, and video processor scroll boundaries. The 
assignment of x and Y address bits to the address 
processor chip output ns depends on bus width and the 
memory configuration t below. The VCB0O2 is a 16-bit 
bus-width system and requires both these bits set 


pi 
bi 


se 


<8> Memory configuration controls the number of row 

addresses refreshed on each scan. In "greater than or 

equal to 1024" mode, 8 are v In "greater than 

or equal to 512" mode, 4 row addresses are refreshed. 

The number of pixels read in each scan is the number of 

refresh reads programmed in XCON * 16 * 8. The VCBO2 

19 subsystem requires this bit to be reset, which 
selects 1024 mode (XCON * 16 * 8 = 1024). 


0 = 1024 Number of pi: read from memory/scan < 2048 
1 = 512 < Number of pixels read from memory/scan < 1024 


[36] X LIMIT (XL) — Width of that portion of the memory 
the screen refresh process (could be more than disp 
his register tells the address calculation hardwar 
shades of the memory, in X, the Y offset (used 
olling) should be applied to. The number loaded to 
a4 st be the number of read cycles set in 
iration register, times 128. (For the VCBO2: 8 X 


read 
Tayed 
e 


Functional Description 


e . e iii a ß pies ia iia eH e IA NGA RARER aNANR NNSA: 


— 


[37] X LIMIT (YL) ~~ 1 of the portion of memory read by the 
screen refresh Pr cess (864 for the VCB02), plus the number 
of extra scans quired when down-scrolling (between 16 a 
32 is suggested). is register tells the address calculat 
hardware what exte nt of the memory, in Y, the Y offset ee 
for down-scrolling) should be applied to. 


of the re 


oe e ben . 
i@rss 


8 


The I offset is appli 

memory defined 7 she ‘ote 

i The memory : 
i 


ed to al 

rc : 
u 2 Y 

ght of gs ke screen 


ctangular area in the 
0] and [XL-1,Y¥L<-1] 
1 


1. 
angle Pram nddveds 0 
or 


e | 2 

he n aes 571 (but not includine 
t] is not usable for any purpose. 
X limit 


r 
1 

di ree 

the address [X limit, Y limit] - usak 

The memory be tween the right edge of the screen an : 

(if any) can be used, but only for = addresses from 2 to the 

height of the displayed screen. The addresses refer to 1 

this paragraph are in device 1 


Pe 
re 
@ 
Oe 


[38] X SCAN COUNT (XCTO) 


pond 


[39] X SCAN COUNT (XCT1) 


[3A] X SCAN COUNT 2 (XCT2) 


Lad 
— 
f 
e 
* 
e 


SCAN COUNT 3 (XCT3) 


[3C] X SCAN COUNT 4 (XCT4) 


. 
2 
5 
= 
SS 
mo 
Ll 
eee 


(XC T5) 
N COUNT 6 (XCT6) 


rs are similar in function to the Y 
scan count registers. These seven & parameter registe 


he X scan count registe 
= e, Woe a 4 L. a 
55 me eee boner izontal timing for the VCBO02 video subsystem. 
E i Ff ; 


— 

2 
etermines 9 ae fF one horizontal event 
zontal blanking. The event is 

1 


er tion o 51 1 
he low 11 bits determine the 
. 


88 £ 
igh-order ph 

ent (in 16ths of a major cycle, nominally ot 
some cents are not allowed to be programmed to thi 
on). This starts from a reference time preceding Ee 
ng of the memory cycle that reads the first data to be 
1ed on a scan (or the corres ponding time duri ing 
e retrace). The events are stored in the registers in 
order of increasing time, . ng in XCTO. The highest time 
value = programmed as the horizontal period event. Bit <E> 
must be programmed in all seven et even if the ee 
horizontal period“ event is in an earlier register. The bits 
of the X scan count registers are assigned as follows. 


ee, , 
we e. 


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<0> 


<B> 


<E> 


E> 


Functional Description 


io eR aR SEARO NTO GARONA 


11 Bits. Time of event from a reference time 3 1/4 major 
cycles before the start of the first memory cycle on a 
scan, in 16ths of a major cycle. The start of a eee 
cycle is defined as the rising edge of PHI 2 during t 
RAS precharge that begins the 8 e. No 2 events may 
occur in the same 1/4 of a major cycle; _that is, no 2 
events may have times that are equ 71 in bi I 

2 bits. 


888 
2 


3 Bits. Event. 

000 = Set horizontal blank low. 

001 = Set horizontal blank high. 

eee = Set horizontal sync low except during vertical 
ne event. 

11 = Set horizontal sync high except during vertical 
mec event. 

0 = Set horizontal sync low. 

1 = Set horizontal sync high. 

10 = End horizontal period. 

ll = Set sync request event. 


A 1 must be programmed for this bit in the XCT- 
following the register that contains the "syne 
event. All other registers must contain a 0 in 


Test functi 


. 


on in XCT6 (normally 0). 


The period must be set to NX 16-4. The integer multiple 
N must be equal to twice 8 number of read cycles in 
XCON plus at least 2 (a integer number of major 
cycles). A larger N „ the horizontal retrace 
interval by units of 1 major cycle. N must be at least 
LO 

Horizontal blanking is normally set low shortly after 
the start of the first memory cycle of the scan to allow 
for the pipeline delay of data in the address processor 
and video processor chips and in the video output 
circuitry. The address processor chip produces the 3 1/4 
major cycle delay mentioned above, and the video 
processor chip produces an additional 10 alpha clock 
delay (5/8 major cycle). Horizontal blanking is set high 
after the desired number of pixels are displayed on a 
scan. 


The polarity of horizontal syne is programmable. 
Horizontal synchronization starts when set high by the 
101 event (or low by the 100 event). Horizontal 
synchronization ends when set low by the 010 event (or 
high by the 011); except when vertical synchronization 
from the Y scan counter is high, when horizontal 
synchronization is set low by the 100 event (or high by 
the 101 event). The 100 or 101 events always change 
horizontal synchronization; one of these events should 
be set to occur after the 010 or 011 event when 
composite sync is generated. 


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Processor Chip Commands — All command 


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f 


a 


hroniz 


ve 
2 


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Sync 


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Funct 


Functional Description 


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F E 0 0 B A 9 8 
ADDRESS PROCESSOR CHIP COMMAND 


0 3 2 1 


/ 0 
| /D INTERCONNECT COMMAND 


wn 


SIE OP CODE ADDRESS 


snl JJ Ses ES oi 


DTE 
Figure 3-26 Command Register Format 


Not all combinations of the command bits are meaningful; onl 
specific commands described in this section are allowed. II 
commands yield undefined results; they are not NOPs. 


y the 
legal 


All commands (except cancel) involve the video processor chips. 
Only those video processor chips selected by the chip select 
register respond to commands on their I/D bus (interconnect) 
inputs and/or allow writes to their associated memory planes. 
Participation in scrolling is determined by the setting of the 
scroll enable bit in each video processor chip. When multiple 
video processor chips are involved in an operation (such as a 
color rasterop or a register load common to many chips), all the 
corresponding chip selects are set. If only one video processor 
chip is to be active (as for a unique register load), only the one 
chip select is enabled. A separate chip select register is used 
for loading video processor chips when using the scroll I/D 
command register. 


The chip select registers have an unencoded enable bit for each 
video processor chip in the system. The chip select registers are 
connected to the I/D bus (interconnect) and are loaded with an 
external I/D bus (interconnect) load. 


If a rasterop command has been loaded and the initialization phase 
is complete (indicated by the initialization complete status bit), 
another identical command may be loaded, effectively requesting a 
repeat of the previous command. The command register is not 
actually double- buffered (only the reloading is remembered), so 
the previous command will not complete properly if a different 
command is loaded before the previous command finishes. (The 
address output must be complete before a new command is loaded.) 
The ability to queue a repeated command is used to reduce register 
loading overhead between rasterops of 3 series, such as when 
displaying a text string. PTB or BTP commands cannot be queued in 
this way because loading a new PTB or BTP command clears the IDD 
FIFO. 


Functional Description 


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e 
e 
ee 
my 

me t 
Cs 
Ou 
re 
35 
age 

S 
— 


processor chip registers does not requi 
) y command. The registers are lc pews se eithe 
by use of the address pins, i 5 tr 
address counter, he interrupt and red i 
with the status register, are used to 


artes 


oe pins, in < onjunct ion 
ermine the sate time to 


sters and chip select registers are 
cessor chip I/D command. Though any 
be transmitted with thi 


preg 
e 
e 
e 
i. 
pee A 
geo? 
2 
ae 
8 
baa 
i, 
Seite: 
i, 
td 
eee 
Lee 
F 
ee 
See 
ame 
Pe 
“st 
ba OS 
fin #% 
agg 
gat i 


ls command, 
are permitted. No reading or active 
cont y the address processor chip as part 
rops are al Figure 3-27 shows the I/D bus video 
register load command format 


a 


or 

rf ti 
_— 
ame 
8 
— 

5 


‘ie 


The address“ in Figure 3 specifies the desired video processor 
chip regis Only those video processor chips whose e ed 
registers be . should be chip selected. Figure 3-28 
Shows the I/D bus Z-axis video processor register load command 


Format. 


The "reg" in Figure 3-28 specifies the register to be loaded: 


lock" should be set to zero for the VCB02 video subsystem. 2 
specify one of the four possible groups of planes or 
aoe whose values are specified by the 16-bit I/D bus data. 
orecessor chips pertinent to the Z-axis load should be 
p 5 Figure 3-29 shows the I/D bus external = ats ster 
load command format (used for loading the chip select registers). 


This instruction is i 
regardless of the se ett cir 
except OOH may be encode d 
the external devices 
chip wi 

transfer 

reserved for the a 
I/D bus cycles. 


gnored by all video processor chips, 
ng of the chip select registers. Any data 
in the seven low bits of the command for 
to decode. However, the address processor 
ll always source data during the I/D interconnect data 
cycles. The I/D bus (interconnect) instruction OOH is 
ddress processor chip to transmit during idle 


The instructions above can be used through either the update (IDD 
nd CMD) or scroll. id ICS) ports. The corresponding data 
95 ö ded before one of the command registers is 
ata register is loaded (except during PTB or 
ord can be trans mitted on a following 
the previous state of the IDD FIFO. Of 
regis ster is the same because it is 
After the command is loaded to the 
Peers aan status flag should be 

| 911) before a new data word 


poe is 


“ 


’ 
TP comman 
I/D Somme an 
cours phe 
only a 81 

appropriate , 
detected (by “interrupt 
or another mand is 10 


the 


= 
os 
8 
3 
te e 
ee 
if 
* 
8 
Se 
ie 


i 7 one 
e eee, e 
3 0 0 


Functional Dese 


F 


I/D Bus Video Processor Register Load 
Command Format 


Figure 3-28 I/D Bus Z-Axis Video Processor Register Load 
Command Format 


EXTERNAL OUTPUT INSTRUCTION | 
. ls ae 0 — 


aa i AS. 


Prgure 3-29 I/D Bus External Register Load Command Format 


order to avoid interference with update operations, only the 
u 


r C 
ll process sho ld load the following registers in the address 
co 4 4 1 


D SCROLL DATA (IDS) 

SCROLL COMMAND (ICS) 
SCROLL X MIN (PXMN) 

OLL X MAX (PXMX) 

ROLL Y MIN (PYMN) 
‘OLL TY MAX (PYMX) 
Y OFFSET (PYOF) 
¥ SCROLL CONSTANT (PYSC) 
PAUSE (PSE), if used for scroll synchronization 


s W #8 
pm Re 


= 


i 
8 


= 
nnn 
eee 
ad 


. 


= 


Oo OO «~] Gy G1 & Ui ho ee 
= 


. 


The following address processor chip registers may be loaded by 
the scroll process with the necessary synchronization between the 
scroll and update processes. 


= 


PENDING X INDEX 1 50 
PENDING Y INDEX (PYT) 
NEW X INDEX (NXI) 
NEW T INDEX (NYT) 
OLD X INDEX (OXI) 
OLD X INDEX (OYT) 


= 


= 


= 


Gy U7) wd Us A Pr 
= 


2 


The scroll process should load only the following registers in the 
video processor chip. 


SCROLL CONSTANT 

FILL 

LEFT SCROLL BOUNDARY 
RIGHT SCROLL BOUNDARY 


2 = 


2 


= 


iy oie aig 
3277 


Functional Description 


ehen eon 


e e RTF ERCoMUMNNISaRarRREAREoNDASAinIONNONDG 


Rasterop Command 
Prior to iss 
registers sho 
During a rast 
before any reg 
command shown 


n 
uing a command to start a rasterop, all pertinent 
uld have been loaded, including the mode register. 
erop, the appropriate status bits Should be detected 
iste are changed. All functions are invoked by the 
i 


9 
rs 
igure 3-30. 


n F 


Figure 3-30 Rasterop Command Format 


O bits enable the first or second 
should never be enabled in fill mode.) 

ways set high to enable the destination. (If it 
oled, no 5 would taken by the hardware, except 
| ) I/D byte specifies the active 


2 
— 
Pr 
rr 
a 
8 
= 
2 
* 
5 
Oo rr 
a 
oy 
bee 
rr 
22 
= 
Bee Leal 
= 
a 
© 


n 
cycle or the 5 FNC SEL is a 2-bit code that selects one 
of the four logic unit function registers in each video processor 
ch E 


ip. "CSR" specifies the bank of CSRs to be referenced during the 
1 


urce and destination cycles. 


SS proce p fills in the last two CSR address bits 
to the ever. in progress. The video processor chips 

i ee. are erected . the chip select 
qui form of a rasterop 


D 
5 
= 
— 
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8 

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rs 
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e 
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bits are used to monitor the progress of a rasterop 
ote] nitialization complete indicates that the source 1 and 
fest ae Gon origins may be loaded and the previo ous rasterop 
mand may be requeued (by loading the CMD regi ter again). This 
ise to reduce wasted time between text characters. Rasterop 
dicates that 5 . may be loaded. Address 
mplete indicates thé any registers may be loaded. 
only one of these bahia bits is enabled at a time. 


* 


8 
ra 


Processor~to-Bitmap or Bitmap-to-Processor Transfers 
Processor-to-bitmap transfers tee or bitmap-to~processor 
transfers (BTPs) are similar to rasterops, except that either the 
source or the oe is “the Ba ea VAX CPU) memory. These 
ransfers use the ne a tus bits for control of the 
mor S, wit ata buffer bits. 


good 


Functional Des ion 


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All data for a PTB or BTP is transferred through the I/D data FIFO 
(IDD). This 6-deep FIFO is cleared when any PTB or BTP (or 
rasterop, or cancel) command is written to the command reg 

Data may then be written to the IDD address "in 
processor-to-bitmap (PTB) transfer, if the transmit status bi 
set. Data may be read from this address duri 
bitmap-to-processor (BTP) transfer, if the receive status bit 
set. A PTB or BTP command is complete when the address output 
complete status bit is set. All data will have been 
transmitted/read from the FIFO and any register can be loaded. 


es 


Scaling cannot be applied to a PTB or BTP because th 
processor chip ignores the scale registers unless both t 
8 


8 5 
t ) 
1 and destination are enabled. A PTB or BTP never enable 


1 
he source 
both. 


2 


When PTB or BTP are used during scrolling, data must be 
transferred continuously to prevent computed addresses in tt 
address processor chip from becoming invalid. The MicroVAX CPU 0 
DMA controller 8 the DMA gate array) must transfer two words 
every horizontal scan time. 


X~Mode PTB and BTP 

In an X-mode PTB, data is transferred from the processor ee. 
CPU) memory to 1 plane with 16 bits adjacent in x ing 
word, followed by additional X words, and then litional 
scans. In an X-mode BTP, data from one plane is trans ferred to the 
processor memory with 16 bits adjacent in X occupying one word, 
followed by additional X words, and then by additional scans. The 
LSB of a word is the leftmost pixel in the displayed word; the MSB 
is the rightmost pixel. The area of the bitmap that is involved in 
a transfer of data to or from the processor memory is determined 
by setting the rasterop destination and source to span an 
unrotated rectangle. Figure 3-31 shows the processor-to~bitmap 
X-mode command format. 


3 
51 


R CCC 
1 a 5 


n Figure 3-31, the FNC SEL and CSR bi 
or rasterops, except that any CSR 
1e register to which the processo! 
elect register controls the plane (. ro 
i. (are) being transmitted. The dest registe 
programmed for the origin and s gras rectangle 
transferred. The fast DY and slow DX must both be zero. 


ts have the same 
sation can be 385 
ata will be loaded. 
Lo oun the proces 
t 


N 
= 


tion sterop 


5 
J 
| 
: 
5 
i 
i 
3 
3 
5 
: 
5 
= 
| 
| 
5 
5 


dasauge e 


ng of the 


ddle 


i 


essor word 


the m 


Ln 


4 


com 
ie 


vo Bi 


rst pro 


fo 


Start 


05 
‘a 


on 


at 


e 
e, 


0 


1 


. 


ch 


ea 


normal rasterop 


any x 


8 


to 


0 


oe 
hg 


1 * 


i 


ed alignment of 


¢ 


ect 


core 


the 


C 


ommand, 


command 


the bitmap-to-processor X-mode 


rasterops, 


more 


for 


. 


Interconnect. 


. 
oh 


Source 


fe reg 


the 


ng 


data 


C 


command, 


5 


PTI 


orrespond 


words, 


BTP 


from 


data may be read 


BTP 


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Functional Description 


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Z-Mode PTB and BTP 

In a Z-mode PTB or BTP, all the bits from one pixel location (one 
bit from each plane) are transferred from or to a processor memory 
word, followed by additional pixel data along the fast vector, and 
then by additional scans. The bitmap area is again determined by 
an unrotated rectangle addressed by the rasterop destination and 
source. Because the Z transfer occurs one pixel at a time, there 
are no restrictions on shifting or use during scrolling, other 
than the requirement of continuous data transfer. Figure 3-33 
shows the processor-to-bitmap Z-mode command format. 


In Figure 3-33, F/B is set to 0 to select the foreground register, 
and to 1 to select the background register. The source register 
cannot be used for PTBZ operations. The use of logic unit function 
register 10 is assumed in the PTBZ command, and is normally set to 
force 1 to select the foreground register, or 0 to select the 
background register. The planes being transmitted to are 
controlled by the plane address, the "Z block" address, and/or the 
chip select register. The destination rasterop registers are 
programmed for the origin and size of the rectangle to be 
transferred. The fast DY and slow DX should both be zero. The 
destination may start on any pixel. Figure 3-34 shows’ the 
bitmap-to-processor Z~mode command format. 


The plane address, the "Z block" address, and/or the chip select 
register are used to select the video processor chips that form 
the 2 word. The destination rasterop registers are programmed for 
the size of the rectangle to be transferred. The fast DY and slow 
DX should both be zero. The source registers are programmed for 
the origin of the data. The sign bits of the source DX and DY 
determine the direction of scanning. 


Figure 3-33 Processor-to-Bitmap 


Figure 3-34 Bitmap~to-Processor Z-Mode Command Format 


During execution of the cancel c 


command is com 
This bit shoul 
unless the so 


used in the vcB0 Vi 
access the video pr 


Functional Description 


a Nn SC i a ge a TA GE UN ONL NI i gS IOI I OCT GI RG URNA 


Cancel Command 

The cancel command stops all operations, regardless of the command 
in progress, dero for commands entered through the scroll I/D 
port. The rasterop status bits are set to their "completed" 
States, and ene address processor output FIFO is cleared. The IDD 
FIFO is also cleared, and the ID status bits set accordingly. me 
pause, scroll service, I/D scroll data, clipping, and verti 
blankin ng Status bits are not affected. Figure 3-35 shows the 
cancel command format. 


jeje 
8 
Lend 


Me 


mand, the I/D data transmit 
s bit dogs, anand the cancel 
may be loaded. 
ommand is loaded, 
delay. 


1 
ready status bit is held low. Wher 


4.20 Video Processor Chip (I/D Bus) Commands 
i ruction/data interconnect is wees to control all the video 
eb 81 and chip select egqisters, The I/D bus 
1 ovide for the exchange of data between 
the video processor chips and the 
ip select registers for the video 
chips' participation 
select registers are 
t sroll process to 
ssor chips, the other for the update 


a 


roecessor bon! 5 
chips: control 
a 


process. 


are in hexadec 
b i t el SS & si & 
angle brac 


[o] RESOLUT 


* 
CC 


„4.2.1 Video Processor Chip Registers — The basic width of a 

vid 0 Processor chip regis ster is 16 bits. All the video process 
egister are it ab- = none Jable. The re 

he addre ss of the first of a group of 

mal and ens close orackets IJ. 

(or the LSB of a group of bits) are 


hi 
add 


© 
1p 
r 


2 . 


asses (or t 
i 


—. 


gn mene 


x5 aa 
rc 

Wi 
At 

Ww 

= 


1 
bits (t. 


ee 7 
. 


the edge mas 


01 it 
he combinat of mas sk ), 
ste constant, and 


1, mask 2, ar 
the source regis the ra sterop barrel sh 
Z- Axis commands to make a videc 

Or 
11 


6 

t ideo processor chip perform as l, 
2 or 4 planes. The VCBO2 color maps cannot take advantage of 
resolution mode, so this feature is not supported. For normal 
VCBO02 operation, l-plane resolution must be selected. 


a 


ee eee lee 


Functional Description 


ieee aia AA i i GRRE 


00 = 1 Plane. Each mask/source bit controls its 
respective mask mux/logic unit bit independently of the 
others. All barrel shifter constant bits are 
significant. The video processor chip acts as a single 
plane for Z-axis operations, receiving or transmitting 
the one bit corresponding to its plane address. The 
plane address may be programmed to any value. 


01 = 2 Planes. Even and odd mask/source bits are ORed 
(after the complementers controlled by the LUF 
registers), and the result is used to control both the 
corresponding bits of the mask mux/logic unit. The LSB 
of the rasterop barrel shift constant is truncated so 
that data in this plane moves only by a multiple of two 
bits. The video processor chip acts as two planes for 
Z~axis operations receiving or transmitting the two 
bits corres ponding to its plane address and the next 
most Significant bit. The plane address must be 
programmed to an even value. 


10 = Undefined results. 


11 = 4 Planes. The four mask/source bits from each 
nibble are ORed (after the complementers controlled by 
the LUF registers), and the result is used to control 
all four corresponding bits of the mask mux/logic unit. 
The two LSBs of the rasterop barrel shift constant are 
truncated so that data in this plane moves only by a 
multiple of four bits. The video processor chip acts as 
Four planes for Z-axis operations, receiving or 
transmitting the four bits corresponding to its plane 
address and the next three most significant bits. The 
plane address must be programmed to a multiple of four. 


NOTE 
The rasterop barrel shift constant must 
be truncated in low-resolution video 
processor chips to keep the bits in 
their proper subplanes. The address 
processor chip cannot supply each video 
processor chip with a different shift 
constant. (Each video processor chip may 
be programmed for a different 
resolution.) On the other hand, this 
effect cannot be provided for scrolling. 
The error caused by truncation must not 
be accumulated and the scrolling region 
may not be the region for which the 
resolution mode has been set. Horizontal 
scrolling should be only in increments 
of the lowest-resolution plane involved. 


Functional Desc cri eien 


gunman unden 


[1] BUS 


CCC 


WIDTH -~ 2 Bits (starting with <2>). Allows either 4, 8, 


or 16 bits of memory to be used, depending on the number of 


pixel 


S required by the display. The VCBOZ video subsystem is 


a l6-bit system and requires the bus width to be set to 


l6~bit 


mode. All video processor chips and the address 


processor must be set to the same bus width. The vides bus 
speed for the 16-bit bus width is 4 bits every 60 ns. 


— 
See 


SCROLL CONSTANT —— This register is double-buf 
loaded becomes active at the beginning of th 


~bit bus width. 
4 bus width. 
defined results. 
6—-bit bus width. 


fered; data 
1e following 


frame, 


<O> 


e 
* 


<6> 


3-84 


4 Bits. X scroll constant. For left scroll, this nibble 
is the magnitude of the scroll, 0 to 15 pixels per frame 
time. For right scroll, this nibble is the magnitude of 
the scroll minus 1. The values 0 to 15 result in scrolls 
of 1 to 16 pixels per frame time, respectively. If the 
scroll disable bit is set in this register, or if a 
nonzero Y scroll constant is programmed in the address 
processor chip, this nibble must be 0. If the region 
being scrolled contains some video processor chips set 
for low-resolution, the low-order one or two bits of 
this nibble should be 0 for left scrolls, or all Is for 
right scrolls. 


Horizontal scroll direction. 


0 = Left. Also use 0 for up, down, and disabled 
scrolling. If a nonzero Y scroll constant is programmed 
in the address processor chip, this bit must be 0. 

1 Right. 


O = Disables scrolling (horizontal or vertical) of all 
data accessed by this video processor chip (disables 
writing for memory plane). Also, the other bits in this 
register must be set to down, left, and zero X scroll 
constant. 

1 = Enable scrolling. 


Vertical scroll direction. This bit accounts for some 
asymmetries between up- and down-scrolling. 


0 = Down scroll. Also used with disable scroll. 
1 = Up, left, or right scroll. 


VVV 


Functional Description 


A ANC neee ee RN TN NID: 


PLANE ADDRESS -~ 6 Bits. Plane address for Z-axis operations. 


r 
No two video processor chips should be given the same (or 
) 


overlapping) plane address(es). If the fill register is 
loaded in Z-mode by the scroll process, the plane addresses 
must be established permanently. However, if the scroll 
process loads the fill registers individually, different 
update regions could have different plane address 
arrangements, 


400 4 Bits. Bit address within Z-axis block {0 to 15). 
Addresses the bit (or low-order bit in a low-resolution 
video processor chip) on which the video processor chip 
will exchange data on the I/D bus during 2-mode 
transfers. This must be a multiple of two or four in a 
low-resolution video processor chip. 


<4> 2 Bits. Z-axis block address (0 to 3). These are 
essentially the high-order bits of a 66-bit plane address 
(intended for use in systems with more than 16 planes), 
but separate blocks must be addresses with separate 2 
commands. For the VCB02, these bits should be 00. 


LOGIC UNIT FUNCTION -~ 4 registers of 8 bits. Any one of the 
four registers can be selected for use during a rasterop or 
PTB command. During Z-mode processor-to- bitmap commands, 
function register 10 is used for modification of the bitmap. 


<O> 4 Bits. Logic unit function. The video processor chip 
logic unit combines the word read from the destination 
(D) during a destination cycle (read-modify-write cycle) 
with the contents of the source register (S) (normally 
loaded during a previous Source memory cycle). This 
occurs after the latter has passed through a 
complementer and resolution logic. The logic unit then 
uses the result (F) to select the foreground or 
background color. 


0000 = 
0001 = 
0010 = 
0011 = 
0100 = 
0101 = 
0110 = 
0111 = 
1000 = 
1001 = 
1010 = 
1011 = 
1100 = 
1101 = 
1110 = 
1111 = 


= ZEROS 

= NOT(D OR 

= NOT(D) AND 

= NOT (D) 

= D AND NOT ( 
, ( 


ao 


eget Gree 


= D XOR 
AND 
= D AND 
= NOT(D XOR 


e. 


ANNNNNNN 


= NOT(D) OR 


D 
= D OR NOT(S) 
D OR 8 


Pay hey ay Pe] Aaj ey a] ey ey rey Me) ey Pe] ey ay yy 
ll i 
— 
© 
a 
= 


= ONES 


3-85 


Functional Description 


3~86 


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mask 1. 
= Use the complement o 


as 
. 
SZ 
he & 
85 
. 
2 
928 
eS 


mask 1. 


<5> 0 = Use mask 2. 
l = Use the complement of mask 2. 


<6> 0 = Use the complement of source. 
l = Use source, 


<7> 0 = Enable resolution mode logic for the source 
register. 

1 = Disable resolution mode logic for the source 

register (pass bits 5 to the logic unit without 

combining adjacent bits, regardless of resolution mode 


register setting). 


The following four registers have 16 bits. The LSB is the 


leftmost Sod eee in a word, the MSB is the rightmost pixel. All 
four registers can be loaded by I/D bus register load 
commands. The mask and source registers can also be loaded by 
data transfers during rasterop cycles. The source and fill 


registers can be loaded with constant data (solid color) by a 
Z-axis register load. 


MASK 1 — Programmable mask register 1. Used to control which 
bits are modified by a read-modify-write cycle. Loading mask 
1 loads mask 2 with the same data, so that only one mask is 
effective. 


MASK 2 -- Programmable mask register 2. Used to control which 


bits are modified by a read-modi fy—w write cycle. 


The outputs of the two mask registers are followed by 
independent complementers (controlled by the logic unit 
function registers). The outputs of the complementers are 
ANDed with each other and with the edge mask (which defines 
those bits involved ina rasterop). The only bits modified 
are those selected by all three masks. (A 1 from the AND 
enables modification of a bit.) Resolution mode logic follows 
_ AND function. If only mask 1 is used, both complementers 

st be enabled or disabled together to prevent the masking 
of all bits. 


SOURCE -- Source word (normally loaded by a source memory 
cycle) for the logic unit to combine with the destination to 
select the foreground or background colors for each pixel. 
The source data is processed by a complementer and resolution 
mode logic before entering the logic unit. The Z-axis address 
for this register is 00. 


WWEiTUuTIUR IMME IOI EMT CTO RIOR NTO MAC MMMM ETN MOMMA NIMC NINN 


Functional Des 


eee e une mun 


cription 


FILL -- Data to be inserted into memory words to fill the 
blank space created by scrolling. Normally, a solid color 
fill is desired, and is provided with a Z-axis load, if 
loaded directly. This register is double-buffered and data 
loaded becomes active on the following frame. The Z-axis 
address for this register is 10. 


Because the scroll region boundaries can be set within a 
word, the video processor chips must be notified which bits 
of the leftmost word and the rightmost word are actually in 
the scroll region. The video processor chip can be programmed 
to place the region boundaries on any bit position (for 
possible future extension), but the address processor chip 
cannot specify the boundary closer than a multiple of four. 
Therefore, only those boundaries that select groups of four 
bits should be selected. These registers are double-buffered 
and data loaded becomes active on the following frame. 


LEFT SCROLL BOUNDARY — 16 Bits. All bits are clear, 
corresponding to the pixels that are to be scrolled in the 
word that contains the left edge of the region. (All other 
bits are set.) Normally, this requires clearing all bits from 
the pixel on the edge through the MSB of the word; but if 
both edges are contained in one word, only bits from the left 
edge through the right edge are cleared. 


RIGHT SCROLL BOUNDARY ~- 16 Bits. All bits are clear from the 
LSB (left edge) through the bit corresponding to the 
rightmost pixel that is to be scrolled in the word that 
contains the right edge of the region. (All other bits are 
set.) All bits are set unless the right boundary between 
words (LSB not scrolled) or both edges are contained in the 
same word. 


BACKGROUND COLOR — Selected by a 0 at the output of the 
logic unit. The Z-axis address for this register is ll. 


FOREGROUND COLOR -- Selected by à 1 at the output of the 
logic unit. The Z-axis address for this register is Ol. 


The foreground and background registers have 16 bits. The LSB 
is the leftmost pixel in a word, the MSB is the rightmost 
pixel. Both registers can be loaded by I/D bus register load 
commands and by a Z-axis register load. The outputs of the 
logic unit select these registers on a bit-by-bit basis as 
the inputs to one side of the mask mux. (The mask mux then 
selects between this new data and the old destination data.) 
Either of these two registers is used to pass data during 
Z-mode PTB operations. 


CONTROL STORE RAM -~ 6 registers. The video processor chip 
control store RAM controls the transfer of data within the 
video processor chip, and to/from other I/D bus devices, 
during rasterops. Addressing of its contents during rasterops 
is controlled by the address processor chip and occurs once 
for each update memory cycle. 


3-87 


Functional Description 


eee 


een ai ubilneemeonmdeeh 


5a a Ag RH aE Ng LS nL lu GST AU EE Og a Rc se QR Ft URN NG. 


[10] CSR O — Controls the first source read if bank a is selected 
and source 1 is enabled in the address processo , 
register. 


[ll] CSR 12 — Controls the second source read if bank 1 is 
elected and source 2 is enabled in the address processor 
aa command register 
[12] CSR 2 -- Controls the destination read-modify-write if bank 1 
is selected and the destination is enabled in the address 
processor chip command register. 


[13] Reserved. 


St source read iff bank 2 is selected 
n the address processor chip command 


[14] CSR 4 =~ Controls the Fi 
and source 1 is enabled 
register. 


r 
i 


[15] CSR 5 — entre ls the second source read if bank 2 is 
selec pi and 1 2 is enabled in the address processor 


ation read-modify-write if bank 2 
ination is enabled in the address 
ster. 


[16] CSR 6 — Controls the destin 
is ted and the dest 


t 
a 8 
sor chip command regis 


NOTE 
These assignments of CSR functions are 
defined by the address processor chip. 
The video processor chip assumes no 
assignment of CSRs, except that CSR 0 
and 4 are linked to the first delay 
register, and R 1 and 5 are linked to 
the second delay register. 


Each of the CSR words has the following bit assignments. 


<O> 2 Bits. External load. Selects the register into which 
incoming data from the I/D bus (if any) will be loaded 


a 


Following a memory read. 


00 = None 

01 = Source 

10 = Mask 1 and mask 2 
ll = Mask 2 


3-66 


Functional Description 


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<2> 2 Bits. Internal load. Selects the register into which 
incoming data from the local memory plane (from the 
barrel shifter) will be loaded following a memory read. 


0 = None 

1 = Source 

OQ = Mask 1 and mask 2 
1 = Mask 2 


<4> I/D bus (interconnect) output control. Only one plane 
should be enabled to output its shifted data on the I/D 
bus, for all other planes, during any one memory read 
cycle (that is, for any one CSR address). 


= Disable output. 
= Enable output. 


<5> Barrel shifter delay control. When executing a fast mode 
asterop, one output word is usually formed from a part 
of each of two source words. To avoid excessive reads to 


the source raster, the previous word can be held in a 

delay papi déer so its remainder can be used with the 

next word. This bit controls one delay register when the 
5 
he 


active CSR is 0 or 4 (for source 1), and controls tl 
other delay register when the active CSR is 1 or 5 (for 
source 2). 


u 


Do not load delay register. 
Do load delay register. 


a 


NOTE 
With two separate delay registers 
selected by the CSR address, the delay 
enable bit is no longer necessary. It 
should be programmed to a l. 


There may be no reason to ever program 
either destination CSR to other than 
000000. These two registers may be 
unnecessary. 


3.4.2.2 Instruction/Data Bus Instructions -- I/D bus inst 
are specified by a l-byte code. Rasterop, PTB, and BTP cc 
are Further specified by 3 subinstruction byte. Most 
interconnect instructions are also accompanied by a 16-bit data 
transfer. 


Functional Description 


iA 


ASNT i pinned ii ct ln dn p ß UG Occipital niin 


I/D Instructions Issued by the MicroVAX CPU 

The addressed video processor chip register of 16-bit data 
transmitted on the I/D interconnect is contained in the word 
loaded to the IDD (or IDS) register of the address processor chip 
(previous to loading an I/D bus command). This instruction is 
always initiated by the MicroVAX CPU. The address processor chip 
never transmits the instruction without an explicit command to do 
so, as shown in Figure 3-36, 


Figure 3-37 shows the instruction format that loads all bits of 
the addressed register (in the video processor) with the contents 
of 1 of the 16 I/D bus data bits. The low four bits of the plane 
address programmed into each video processor chip selects the I/D 
data bit used during the load. Only those video processor chips in 
the addressed Z-block that are chip selected are updated. The 
Z~block should be 0 for the VCBO2. If a video processor chip is 
set for a low-resolution mode, a pair of bits or a nibble is 
duplicated into each of the 8 pairs or 4 nibbles of the selected 
register. Z-axis register addresses are defined as follows. 


00 = Source 

01 = Foreground 
10 = Fill 

ll = Background 


The VCBO2 video subsystem uses instructions designed to control 
external I/D devices, which load the update and scroll chip select 
registers. The format of the external register load instructions 
is shown in Figure 3-38. I/D instructions are distinguished by bit 
7 = 0 in the instruction byte. Instruction 00H is reserved for 
NOP, 


Address Processor Chip I/D Instructions 

The only direct I/D bus (interconnect) instructions a programmer 
will use are the video processor chip and chip select register 
loads. The remaining I/D interconnect instructions are used by the 
address processor chip to control rasterops. 


The instruction shown in Figure 3-39 is transmitted by the address 
processor chip when the I/D bus is idling. 


Functional Description 


ee a ce ae eee een nail 


SUBINST: | UNDEFINED 


MAT BAS 


Figure 3-36 Video Processor Chip Register Load 
Instruction Format 


INST: 2 BLOCK 


SUBINST: | UNDEFINED 


BART O46. 


Figure 3-37 Video Processor Chip Z-Axis Register Load 
Instruction Format 


| FF 
INST: 10 EXTERNAL OUTPUT INSTRUCTION 


j 
i 


SUBINST: 


MA 6487 


Figure 3-38 External Register Load Instruction Format 


INST: 


— ü — | 


UNDEFINED 


WRT Ga 


SUBINST: 


a8 


Figure 3-39 No Operation Instruction Format 


Functional Description 


nN 


r a ee 


it 


The instruction shown in Figure 3-40 is essentially identical to 
the video processor chip Z-axis register load, except that the 
instruction is generated with an accompanying read-modify-write 
cycle (as part of a processor-to-bitmap transfer). Bit F/B is set 
to 0 to select the foreground register, and to 1 to select the 
background register. The source register cannot be used for PTBZ 
operations because the propagation delays in the video processor 
chip are too long for the path through the source register. The 
use of logic unit function register 10 is assumed in the PTBZ 
command. An edge mask is provided to select the one bit in the 
memory being written. However, the Z data being written by the 
Current memory cycle is that which was transmitted during the 
previous I/D bus cycle (not the concurrent cycle). These are 
really ordinary Z~axis register loads interleaved with 
destination-only rasterop cycles. The right and left mask 
specifiers are equal for this instruction and are the address of 
the selected bit. 


The address processor chip uses the instruction shown in Figure 
341 during a bitmap-to-processor transfer, along with an 
accompanying memory read cycle. The bit address specifies the bit 
in the memory word for which the color is being read. The video 
processor chip generates a barrel shift constant from the bit 
address and the low four bits of the plane address. Each of the 
video processor chips addressed by the Z-block transmits its bit 
(or bits, if a low-resolution chip) on the appropriate I/D bus 
Pin. 


The instruction shown in Figure 3-42 is generated by the address 
processor chip with an accompanying memory read cycle to control 
the handling of the read data. The CSR address selects the 
controlling CSR location, which is either O0, 1, 4 or 5. Th 
subinstruction controls the use of the barrel shifter to align the 
Source data with the destination location. The barrel shifter has 
a 32-bit input and selects a 16-bit segment as an output. If the 
shift constant is 0, the leftmost 16 bits are selected. If the 
shift constant is 15, the rightmost bit of the left word and the 
left 15 bits of the right word are selected. The inputs to the 
left or right word of the barrel shifter can come either from the 
data read on the current cycle, or from the data previously stored 
in the delay register that corresponds to the addressed CSR. If 
the LD bit = 0, the current word is used for the left input. If 
the LD bit = 1, the delay register is used for the left input. The 
right input is selected similarly. 


The instruction shown in Figure 3-43 is generated by the addres 
processor chip with an accompanying read-modify-write cycle t 
control the logic unit register and the edge masks. The CS 
address selects the controlling CSR location and is either 2 or 6. 
One of the four logic unit function and mask control registers is 
selected. The subinstruction sends the edge mask to select the 
bits to be written into the word. The left mask is the bit address 
of the leftmost pixel to be modified. The right mask is the bit 
address of the rightmost pixel to be modified. Therefore, if one 
pixel is to be modified, both mask values are the same. The LSB, 


u 
or leftmost pixel, is 0. The MSB, or rightmost pixel, is 15. 


3-92 


Functional Description 


1 | Z BLOCK 


INST: 


i ‘ 
5 q i 


RIGHT MASK 


MB c 


Figure 3-40 Z-Axis Write (Two Interleaved Instructions) Format 


— — 
N 1 | NOP | zeLock | 


SUBINST: | RIT ADDRES 


Figure 3-41 Z~Axis Read Instruction Format 


CSR ADDRESS 


INST: 


SUBINST: | acm | SHIFT CONSTANT 


Figure 3-42 


INST: 1 | FNCSEL | NOP | CSR ADDRESS 


i 


SUBINST: | LEFT MASK 


Figure 3-43 Active Cycle for Read-Modify-Write 
Instruction Format 


Functional Description 


his 
func 


nen d d ee 


ee Configuration 
tion scribes system-wide interconnection, timing, and 


tional 1 8 specific to the VCBO2 video subsystem. 


Address Processor Chip Pins — The see te processor chip 


“contained in an 84-pin, leaded, square, surface-mount package. 
numbers are indicated in brackets II. eroupe of pins are 
isted in order, starting with the high-order pin. 


Processor Interface 


DAT<15:0> ~— 0 


5 5 


73, , 75; 


DAT<15:00> are connected to PB<¢15:00> on the DMA gate 
array and are een for the read/write data transferred 
From/to any register in the address processor and video 
processors. DAT<15:00> are tri-stated to receive register 
data unless RD is high, and -AS and —DS are low. 


AD<5:0> (Input) 177, 78, 79, 80, 81, 821 


AD<5:0> are connected to the AA<6:1> pins of the DMA gate 
array and select an address processor chip register. 
AD<5:0> are latched on the falling edge of As. 


~AS (Input) [84] 


The falling edge of ~AS latches the address on AD<5:0> and 
provides the address processor chip select function. In 
the VCB0O2 video subsys tem, ~AS and -DS are both connected 
to the ADDAS L pin on the DMA gate array. ADDAS L is 
asserted by the DMA gate array only for address processor 
chip bus cycles. When data is transferred to the address 
processor's ADCT register, -AS increments the register 
point E. 


~DS (Input) [83] 


The falling edge of -DS latches processor data. During a 
read, the low level enables DAT<15:0>, and the rising edge 
as isables DAT<15:0> output buffers. -DS and -AS are both 
nnected to the ADDAS L pin on the DMA gate array. ADDAS 
L. is asserted by the DMA gate array only for address 
processor chip bus cycles. 


RD (Input) [1] 
RD is connected to the DMA gate array pin ADDWR L. When RD 
is asserted (high) a read cycle is selected. When RD is 


deasserted (low) a write cycle is selected. RD is latched 
by DS. 


Functional Description 


“REQ (Output) [11] 


-~REQ is connected to the DMA gate array pin ADDRQ L. REG 
is asserted by the address processor chip when a bit in 
the request enable register matches the corresponding bit 
in the status register. ADDRQ L synchronizes the transfer 
of data by the DMA logic (in the DMA gate array) with the 
execution of instructions by the address processor. 


-INT (Output) [10] 


INT is connected to the IROI L pin on the DMA gate array. 
~INT is asserted by the address processor chip when a bit 
in the interrupt enable register matches the corresponding 
bit in the status register. IRQ] L is used by the DMA gate 
array to request interrupt service from the MicroVAX CPU 
for the address processor. 


INIT (Input) [2] 


INIT is connected to the QBUS INIT signal. INIT resets 
the address processor chip command processor, halts 
commands, and clears the address counter, IDD, and address 
output FIFOs. It also disables the I/D bus drivers on the 
address processor chip until the first occurrence of SYNC 
following deassertion of INIT. 


Memory Address and Video Processor Chip Interface 


oe 


MEMAD<10:0> (Output) [52, 51, 50, 49, 48, 47, 46, 45, 44, 
43, 40] 


Bitmap memory address bits; multiplexed row and column 
addresses for the bitmap. Addresses are clocked out by 
ADDCLK: one row and eight column addresses for a major 
cycle, or one row and one column address for a minor 
cycle. 


ADDCLK (Input) [25] 


Bitmap memory address clock. Nine c 
8 


cles per major memory 
cycle; two cycles per minor memory c 


yel 
ycle. 
128/-16 (Output) [37] 


Bitmap memory cycle select. High selects a major cycle for 
a 128-bit read or write (in 16-bit mode). Low selects a 
pair of minor cycles for a 16-bit read or write (also 
16-bit mode). 

R/-W (Output) [36] 

Bitmap memory read/-write. Selects read or write for major 
or minor cycles. If write is indicated for a minor cycle, 
external timing implements the required RMW sequence. 


ta FA om 


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Functional Description 


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Monitor Timing 
® BLANK (Output) [7] 
Video composite blanking signal. High indicates blanking. 
. CMPSYN (Output) [6] 


Video composite/horizontal synchronization. Composite 
synchronization; programmable pola rity. 


* VRTSYN (Output) [5] 


Video vertical synchronization. Not used in the VCBO2 
video subsystem; programmable polarity. 


Clocks 
* PHI1, PHI2 (Input) [53, 55] 


Phase 1, 2 clock inputs. Non-overlapping clocks; period is 
1/4 major cycle. 


Phase 3, 4 clock inputs. Non-overlapping clocks; period is 
1/8 major cycle. 


3 synchronization request. Low indicates that a 

stem synchronization should be initiated by ed external 
ing generator (in the following major cycle; reset to 
h state by the assertion of SYNC). 


6 SYNC (Input) [9] 


5 


System synchronization. Issued by the external timi 
generator during the first part of a synchronization 
interval to reset the phase of address processor chip 
timing logic. Also, a number of double- buffered registers 
are updated. Note that this is not a chip reset pin. All 
clock signals are held frozen during the entire 
synchronization interval (two major cycles). 


8 
8 
n 
e 
i 


e VDDL1, VDDL2, VDDL3, VDDI, VDDM, VDDC, VDDD [3, 23, 62, 
17, 41, 54, 67] 


Power. +5 V power supply for logic, I/D bus, memory 
address bus, clocks, and data bus. 


Functional Description 


eee mln 


® 


3.4.3.2 
contained in a 68-pin, leaded, square, surface-mount package. Pi 
numbers 

order, 


Na GN Ga Nga e NDeNTRSGR IUGR SARIN AOSD ae A EIU EINER OHO 


GNDL1, GNDL: 


2, GNDL3, GNDI, GNDM, GNDC, GNDD [4, 24, 61, 
13, 42, 56, 68] 


Power return. Ground for logic, I/D bus, memory address 
bus, clocks, and data bus. 


VBB bypass. 
Spare [29, 30] 
Video Processor Chip Pins -- The video processor chip is 


i 
are indicated in brackets I]. Groups of pins are listed in 


starting with the high-order pin. 


Bitmap Memory 


ah 


3-98 


Bitmap data input/output bus. The DIO<15:0> output drivers 
are tri-stated when R/-W is high. 


SCROLL (Input) [10] 
Scroll enable. 


are contained 
rightmost word i 


High indicates all DIO<15:0> bus words that 
in a scrolling region, except for the 
n the region. 


a, 


PE (Output) 125] 


Plane enable. When high, this tri-state signal „ the 
bitmap memory to be written during a rasterop or scroll 
write cycle. This output driver is tri-stated when R/ -W is 
high. 

128/-16 (Input) [65] 

Major or minor cycle. When high, this signal „ 
internal logic that is associated with majo cycles 
(128—-bit process). When low, this signal mel cates 
internal Ogre that is associated with minor cycles 
(16-bit process). 


Bitmap memory 5 memory write. When high, all 
DIO<15:0> and PE output drivers are tri-stated and the 
video processor chip may receive bitmap memory data. When 
low, all DIO<15:0> and PE output drivers are enabled. 


When 128/-16 is low, the falling edge of RM is used to 
latch into the bitmap memory data on the DIO<15:( 


sii 


I/D Bus 


o 


Functional Description 


LTCLK (Input) [66] 


The latch clock is generated by the timing logic on the 
base module. When R/-W and 128/-16 are high, the falling 
edge of LTCLK is used to latch into the bitmap memory data 
on the DIO<15:0> lines. 


When R/-W is low and 128/-16 is high, the rising edge of 
LTCLK causes valid scrolled data to be shifted out on the 
DIO<15:0> lines. There are eight cycles of LTCLK per major 
cycle. 


(Interconnect) 

ID<7:0> (Input/Output) [31, 32, 33, 35, 36, 38, 39, 46] 
Instruction/data input/output interconnect. Normally 
tri-stated to receive instructions or data, the ID<7:0> 
output drivers can be enabled during execution of Z-axis 
or active I/D instructions. 

cS (Input) [40] 

chip select. While receiving an instruction, if ID<7> and 


cS are high, the arriving instruction is latched and 
executed. Otherwise, the arriving instruction is ignored. 


Video Output 


@ 


Clocks 


” 


VID<3:0> (Outputs) 156, 57, 58, 39] 


Video output. Screen refresh data is shifted out on these 
output lines on the rising edge of ALPHA. 


ALPHA (Input) [55] 


Data on the VID<3:0> lines is shifted out on the rising 
edge of ALPHA; period is 1/16 of a major cycle. 


PHI1, PHI2 (Inputs) 150, 49] 


Non-overlapping clocks that determine overall timing and 
control of the video processor chip; period is 1/4 of a 
major cycle. 


SYNC (Input) [63] 


System synchronization. When asserted, synchronizes the 
phase of internal video processor chip states to the 
remainder of the VCB02 video subsystem. Also, a number of 
double-buffered registers are updated. Note that this is 
not a chip reset pin. 


3-99 


Functional Descriptio 


F . RC OURO 


+5 V power supply. 


8 VSS 48:00 Drivers: 1, 68, 67, 27, 28, 44, 45; Logic: 29, 


Power return. Driver ground; logic ground. 


VBB, CAVITY [61, 60] 


Substrate bias. VBB must be connected to CAVITY. 


. 


High-Speed Timing 


Clock Generation 
The address processor and video processor chips require the 
following clocks. 


05 PHT1, PHI2 —— Basic system clocks for both the address 
processor and video processor chips; determine I/D bus 
7 


‘i 


# ee PHI4 — Serial arithmetic clocks for the address 
cessor chip. 


m 


LPHA — Video output clock for the video processor chip. 


@ ADDCLK —— Address output clock for the address processor 


® LTCLK —— Data clock for 128-bit cycles (major cycles) for 
the video processor chip. 


Clock timince 3 in increments of 30 ns (nomi 
actual perio HI anc is 115 


nal); however, the 
¢ th 
120 ns. All o 


J 

be $s 115.6 ns, rather than the nominal 
th e accordingly. 

The skew between any two of the above clocks 1 8 not exceed +/- 5 

ns. This is achieved by deskewing all these clocks through latches 

clocked at 30 ns. 


ADDCLK has nine cycles per major cycle or two per minor cycle. 
LTCLK has eight cycles for every major cycle or pair of minor 
cycles. Though LTCLK does not clock data at the pins during minor 
cycles, it is still used internally. 


Functional Description 


[Thhhh[h[hhhhhh[[!!!!!!!!!!!!!.!.. i 


System Synchronization 

All system timers are synchronized to each other once every frame 
(vertical scan of the screen). Synchronization occurs at a time 
when no screen refresh or other user-perceivable activity is in 
progress. 


ha 


Synchronization is accomplished by freezing all clocks and memory 
timing signals for two major cycles (one compute cycle in the 
address processor chip). This is called the ‘synchronization 
interval. During the first part of the synchronization interval 
(the first major cycle) the SYNC pins on the address processor and 
all video processor chips are asserted. The clocks must be stopped 
at the start of any major cycle (rising edge of every other PHI2) 
that is permitted by the programming of the X SCAN COUNT 
registers. During the synchronization interval, the clocks must 
remain in the following states. 


PHI] ~ Low 

PHI2 - High 

PHI3 - High 

PHI4 ~ Low 

ALPHA — High 

ADDCLK - High 

LTCLK — High 

Other memory timing signals as required 


@€¢¢¢¢ 8 6 © 


After the synchronization interval, all clocks must proceed 
exactly as if the two major cycles of the synchronization interval 
had never occurred. Basically, the only clocks that do not freeze 
are the ones that are needed to time the synchronization interval. 
The synchronization interval is initiated when the address 
processor chip issues the SYN/REQ signal. The exact timing of this 
signal is programmed in the X scan count registers. The clock 
generating logic responds to SYN/REQ by starting a synchronization 
interval at the next major cycle boundary. 


Processor bus activity can proceed as normal during the 
synchronization interval. 


I/D Bus (Interconnect) 

The instruction/data interconnect is tied to the address processor 
and video processor chips and to the chip select registers. 

The I/D bus transmits two bytes of a command from the address 
processor chip, and transfers two bytes of data from the address 
processor or video processor chips every minor cycle. 


Functional Description 


BAA 


een 


F e r 


Transmissions are synchronized to memory cycles, as required. A 
byte is transmitted during each of the four PHI1 and PHI2 pulses 
in a minor cycle. Each of the two PHI1 and two PHI2 pulses are 
labeled A and B. The rising edge of PHI2B starts a minor cycle, 
and the sequence is PHI2B, PHIIB, PHI2A, PHIIA. The command/data 
sequence is as follows. 


I 


1 Instruction 1 

2. PHII1A — Sub instruction 1 
3. PHIZB - Low byte data 0 

4. PHI1B — High byte data 0 


1. PHI2A 


5. PHI2A — Instruction 2 

6. PHIIA - Subinstruction 2 
7. PHI2B - Low byte data 1 
8. PHI1B ~ High byte data 1 


9. PHI2A — Instruction 3 
10. PHIIA - Subinstruction 3 
ll. PHI2B — Low byte data 2 
| 1B — High byte data 2 


13. Ete, 


Notice that the data for instruction 1 follows instruction 2. This 
provides for certain pipelining requirements of source rasterop 
memory cycles. 


External I/D Bus (Interconnect) Devices 

In addition to the address processor and video processor chips, 
the chip select registers are attached to the I/D bus. These 
devices are write-only because the address processor chip always 
transmits data during an I/D interconnect command. External I/D 
commands are distinguished from video processor chip commands by a 
zero in bit 7 of the instruction byte. The subinstruction is 
undefined during external I/D instructions, and so, is not of use 
to an external device. The external register numbers for the chip 
select registers are 


® Update Chip Select = 60L 
4. Scroll Chip Select = 40L. 


The logic that controls the loading of the chip select registers 
decodes the instruction byte that is present only during PHI2A 
eycles. The logic synchronizes to the PHI1/PHI2 A/B cycles by 
uSing SYNC, which always occurs during a PHI2B cycle. 


Chip Selects 

Each video processor chip has a chip select pin that controls 
whether or not it responds to I/D bus instructions, and through 
the PE pin and write enable logic, whether it allows writing in 
its associated memory during rasterops. An unencoded pin from a 
chip select register is provided for every video processor chip in 
a VCBO2 video subsystem. This allows any combination of video 
processor chips to be enabled. Chip selects are sensed by video 
processor chips only during the instruction cycle (PHI2A). 


3-102 


Functional Description 


. c AaiieR Cain iOS INAN AITO Onin 


Because the scroll process needs to access the video processor 
chips without disturbing the update process, it requires a 
separate set of chip selects. The scroll chip selects are provided 
by a register connected to the I/D bus. 


Memory Address Bus 
The bitmap address bus is common to all bitmap planes. Two groups 
of pins on the address processor chip control the address bus to 
the bitmap memory: 


1. The MEMAD, WE, and SCROLL pins are clocked by the ADDCLK 
pin. The MEMAD pins provide one row address and one column 
address for each 16-bit (minor) cycle, and one row and 
eight column addresses for each 128-bit (major) cycle. A 
valid set of write enables and a scroll are provided for 
each column address. The -WE pins are meaningful only 
during write cycles. The SCROLL pin is meaningful only for 
128-bit read cycles. ADDCLK has a high interval that 
includes the first 30 ns of the PHI2B that starts a major 
cycle (or pair of minor cycles). The rising edge of the 
pulse that includes this interval brings the first column 
address (or only column address for a minor cycle) from 
the address processor chip. The previous pulse fetches the 
row address, and the following pulses (for a major cycle) 
fetch additional column addresses. There are nine cycles 
of ADDCLK in a major cycle and two cycles of ADDCLK in a 
minor cycle. ADDCLK is the same for reads as for writes. 


The series of column addresses in a major cycle form a 
sequential up-count. The MEMADs are latched externally to 
the address processor chip (on the 4-plane module) to 
deskew the propagation delay of the address processor 
chip, in order to obtain tight memory timing. This latch 
is also clocked by ADDCLK, so that the last column address 
of the previous cycle is going to the memory while the row 
address of the next cycle is coming from the address 
processor chip. Similarly, the row address is applied to 
the memory while the first column address is fetched from 
the chip. 


The scroll pin indicates memory words that are contained 
in the scroll region. It comes out of the address 
processor chip with the address of the associated word and 
is latched along with the MEMADs. However, it is accepted 
by the video processor chip as if it were data coming from 
the memory; therefore, it is delayed further so that it 
matches the data timing. 


NOTE 
The scroll pin from the address 
processor chip does not connect directly 
to the scroll pin of the video processor 
chip. 


3-103 


ee 
a 


‘unctional Description 


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128/~16, R/-W, and FORCE ett are provided by the 
288 processor chip on the an that precedes the 
PHI 25 that starts each major ave: (or pair of minor 
cycles). These pins warn the clock e rator of the type 
fF cycle that should be generated next. A 16-bit write 
cycle means that a 16-bit read-modify-write cycle 
(Containing both read and write portions) is next. 
NOTE 
128/-16, R/-W pins from the address 

or chip do not connect directly 
pen A "16, R/ A pins of the video 


The 
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Memory Address Bit Assignments 
The sequence of address outputs at the MEMAD<10:0> pins of the 
address processor chip is a function of the bus width and memory 
configuration bits in the X scan configuration register of the 
address processor chip. The X and Y address bits are multiplexed 
out at row and column times for the memory in such a way that 
3885 refresh is guaranteed by keeping the fastest moving X and Y 
oes in the low eight row addresses. Table 3-1 lists the 
ddress bits, numbered according to their s 
ca den lations. The lowest four X address bits 
1) es: pm, ye pl 15 
od 
4d 


ua 


i 


att 


ie he ance in address 
S not Shown in Table 
he 16-bit bus width 


access pixels within a mem n 
, the weno? does not use 


| i Ory 
je used by the VCBO02 video subs 
dress bit 10. 


re 
— 
re 
e 
i 
cr 
21 


These addresses are mapped with an external multiplexer to 
generate the row and column addresses for the memories as shown i 
Table 3-2. Note that 11 bits of X are used for a total of 2048 
scan lines of me mor y- The low 4 bits of Xx (X0 through X3) are not 

| since data is accessed 16 bits at a time. X4 is not used in 
d Supplied to the memories, but is used to 
n two banks of memory. Five bits of X are Suppli 
S as an address. This results in 1024 pixels or 
2 X 32 = 1024). The VCBO2 memory is organized as 
X 2048 (vertical) pixels. 


e 


scan li 
1024 (he 


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rizgont 


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sa au FI 

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8 — 


Memory Refresh 

Memory refresh is accomp rocess. For 

enerated. To 

2 Scans must 

le of 32, so 
sses at the 
266-adevess 


lished by the screen refresh p 
each horizontal scan, = unique row addresses are g 
generate a complete sequence of 256 row addresses, 3 3 
occur. The VCB0O2 atepiay: 864 scans, which is a multip 3 
there are no incomplete sequences of 256 row addre 
bottom of the sc display. In the VCB02, a complete 
sequence is ; 2 
the 4 ms rec 
accomplished du 
time to complete a refresh (1. 263 ps) is the 5 zh period (593 
us) plus the vertical retrace time (36 scan lines = 667 us). 


in less than 0.6 ms. This is far less than 
‘ed by the dynamic memory. However, no refresh is 
rtical retrace. Therefore, the worst-case 


Functional Des scription 


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N ia Multiplexed MEMAD<10:0> Bits 


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1 3 10 9 7 6 5 4 3 2 1 


Row Tine X12 111 
9 Tine * es 


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Note: Greater I 1024 1 16— Be ‘pas: 1 


Table 3-2 


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emory Address Bits 


Address Bit 7 6 5 4 3 2 1 0 


Row Address * 9 
Column Address 8 * 


“ayant ORO ASG ieee odeube dhe, ee banane e e SSS AST LASSE 


Memory e 

The VCBO2 aut subsystem was designed to work with 64 K X 4 K 
dynamic RAMS ( th page mode access). The data rate during major 
cycles requires approximately 90 ns cycles. Two banks of RAM are 


ie 


multiplexed to e eve this data rate. 


Since the VCBO02 has two screens of memory per plane, 64 K X 4 RAMs 

are arranged in even and odd banks (of 4 chips each), with 
successive major cycle words accessing alternate banks (sele ected 
by address bit X 4). 


Memory Data Bus 

The memory data lines for each plane are connected to the video 
processor chip data lines through a transceiver with integral 
transparent latch. The latch is held open to pass data directly to 
or from the memory during minor (16-bit) cycles, with the 
direction controlled by R/-W. The latch is used during major 
(128-bit) cycles to extend the hold time of memory data. The latch 
is clocked by LTCLK. 


The type of memory cycle in the video processor chip is controlled 
by the 128/-16 and R/-W pins. These pins are changed at the time 
of the PHI2B clock that starts each major or minor cycle. If the 
minor cycle is a read-modify-write (signaled from the address 
processor chip as a 16-bit write), the R/-W pin initial 
indicates a read, and, at the appropriate time in the cycle, 
changes to a write to latch data and reverse the bus. 


NOTE 
The 128/-16, R/-W pins from the address 
processor chip do not connect directly 
to the 128/-16, R/-W pins of the video 
processor chip. 


Functional Description 


ONT SANA III HENTAI SINS SIDERED SONU EHO RS RON I GBR SETH GE HERE OS A a i SI d SE GU SH RS iE ATi al iii p NOOR GOON NR ARON KO 


The memory data bus is controlled differently for major and minor 


1. Major cycles —— LTCLK contre 
During 128-bit reads, data 
processor chip on the . 
128-—bit writes, d 
chip or i “LTC 
differe 0 eads and writes. During 16-bit 
‘cles, CLK continues to run, using the 128-bit read 
] 


ols the clocking of data. 
is latched in the video 
ing edge of LTCLK. During 
es from the video processor 
CLK, The timing of LTCLK is 


2. Minor cycles — During a 16-bit read, data is latched in 
the video processor chip | falling edge of ae PHI2A 
middle of the ‘ing a read-modi fy j 
latched Lir 


ng or PHI2A 


. 


1S earlie: 
rocessor ae 2 


baus eS the 


Write Enable Circuits 
The clipping and „ logic use write enables of the bitmap 
memories to se rite memory words and parts of words. In 
é CBO2 video subsystem, the write enables are arranged in groups 
, Separately for each plane. This allows 
nag to boundaries at each multiple of four bits 
] allows each plane to be independently 
scrolling. These groups of write enable 

gical combination of signals from four 


Le 
re 


] 
enabled for ra ste 
pins are co keels 
sources. 


1. The 


pins from a address processor chip provide 
ables for ach nibble of each 16-bit word 
ated with each ae ae address. The -WE signals are 
I 5 AD 


DCLK, similar to the MEMAD 
are further delayed to match 
nese signals provide the 4-bit 
and scrolling boundaries, and 


a 


legic for each plane. 


rT} pin from each video processor chip is used for the 
write enable logic of only the associated plane to enable 
or disable rasterops or scrolling for that plane. For 
ster the PE pin responds o the state of chip select 
uring h I/D inst ction of the rasterop. It 
| scroll) chip 

e PE pin is controlled 
the video processor chip 


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Functional Description 


eee 


3. The force pin from the address processor chip is delayed 
until the rising edge of PHI2B starts a major (or minor) 
cycle, and is then combined in the write enable logic of 
all planes. This pin is asserted during major cycles if 
down-scrolling is active anywhere in the frame. This 
signal is used to force writing in planes where scrolling 
is disabled (because all data, rather than no data, must 
actually move in these planes during down-scrolling). 
Thus, writing is disabled in any plane where PE is not 
asserted, unless both FORCE is asserted and PE is not 
asserted. 


4. The write enable logic also uses high-speed clocks to 
generate the high-resolution edges in the final write 
enable waveforms. 


Video Bus and Video Output Circuits 

The video bus from the video processor chip is clocked by ALPHA 
and provides data on every clock. The data is deskewed by a short 
set-up time shift register on the next 60 ns edge. Ultimately, the 
4-bit video data is shifted in a serial stream through a color map 
and digital-to-analog converter, and sent to the video monitor. 


The BLANK and CMPSYN signals from the address processor chip are 
precision outputs that provide the address processor composite 
video blanking and composite synchronization of the monitor. These 
signals are generated with 60 ns resolution and are normally 
deskewed with the video data. Because the blanking output is only 
programmable in 60 ns increments, external pipelining is used to 
ensure the blanking signal matches the higher-resolution video 
signal, so that the correct pixels are blanked and unblanked. 
3.4.3.3 Initialization -~- The INIT pin resets the operational 
aspects of the chip: stops rasterops, clears FIFOs, resets status 
bits, and clears the interrupt enable registers. This is different 
from the system SYNC pin, which resets timers and counters. 


Jao DMA GATE ARRAY 

The DMA gate array provides a complete DMA Q22-Bus interface, 
address processor display list processing (using the template 
RAM), hardware cursor support, and I/O decode (including interrupt 
handling). 


The DMA gate array (DC7035) is a semi-custom-integrated circuit 
constructed using double-level metal HCMOS gate array technology, 
and packaged in a ceramic 120 PGA (pin grid array). The DMA gate 
array was designed to provide a specialized DMA engine that 
interfaces the 0Q22-Bus to the address processor chip, and assists 
in the execution of video display lists and the transfer of bitmap 
data. 


3-107 


Functional Description 


r 


is merely a sequence of commands and data that 
ed video operation when executed by the address 
y uSing the DMA engine provided by the DMA gate 
oh VAX CPU need only create the display list and 
ate the DMA process. This frees the MicroVAX CPU from the 
den of transferring the data to the address 5 chip ee 
ng the execution of the display list. isplay lis 
ed uted by the DMA gate array are Pepe! to as 


— 
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oO 
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5 


exec 8 
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5 


control Signals for 
sferred from/to the 


: provides dedicated address and 

Adress Processor chip. The data is tran 

through the gate array to/from a second 16-bit data bus 

lled the "private bus." The private bus is shared by the DMA 

2 fay, the address processor chip, and an external RAM called 
1 


The template RAM is partitioned inte 
rds are reserved as 3 FIFO f 
rds are used to sto cursor bi 

e RAM is used to store disp. 


at 
N nose routines common to many appli 


three segments. The first 64 
the DMA process. The last 32 
ap data. The remainder of the 
y list routines, particularly 
t 


® 


to 
or 
tm 
la 
cations. 

isplay lists stored in the template RAM are referred to as 
"template 1 lists." Special commands have been 5 ai 
allow template display lists to be called from DMA display lis 
Commands have also been provided that allow template display li 

to fetch commands and data from the DMA display list data 3 
(from the FI IFO). As a result, routines stored in the template RAM 
can es as command “templates" that fetch variable data from the 
FIFO. ng template display list routines minimizes the number of 
ee that must be transferred in a DMA display list. Fever bus 
n are required to transfer the reduced DMA display list; 
ra rr 
1 


2 


31 
* 
therefore, overall systen performance is improved. The DMA gate 
array provides dedicated address and control signals for the 
template RAM. 


ition to the DMA engine, the DMA gate array includes an 
pt controller, address decoding logic, and video cursor 

. ‘The interrupt controller provides masks, generates a 

ble interrupt vector (the vector base is programmable), and 
esolves interrupt priorities for three interrupt sources. One 

I es from the internal DMA logic. The interrupt outputs 
: ; SS processor chip and the communications controller 
on the VCB02 base module are connected to two interrupt input 
provided by the DMA gate array. 


* on | 
2 5 


ey 
on, 

2 

. 


oy 


8 9 


Functional Description 


r OR NNINRS RTO eGR NTR a aN eOR Oso NAMNSARONN 


een neee muede 


The address decoding logic provides . chip enables for a 
56~Kbyte memory address block. Enable signals are provided for 
external ROM, the template RAM, the 2988 5 processor chip, and an 
external address decoder. The base of the 56- Kbyte address block 
is programmable to any 64- Kbyte boundary in the Q22-Bus memory 
address space 


The cursor logic generates a 2-plane, 16 Xx 16 pixel, bitmap 
eursor. Cursor data is read from the 5 RAM during the 
horizontal sync interval. The start addres of the cursor is 
programmable to any pixel location and may be es e off the 


active screen refresh area. The gate array outputs the cursor data 
at the appropriate time, every fourth VCBO2 video pixel clock 
cycle. The data is output as two 4-bit words. 


The following sections explain the operation of the DMA gate 
array. 


Sade. Address Decoding 

A power reset disables the address decoder in the DMA gate array. 
To enable the address decoder, a value must be written to the I/0 
page control and status register (CSR) and decoded external to the 
gate array by logic on the base module. When this address is 
detected, the external decoder asserts the CONSEL L signal pin on 
the gate array. If the cycle is a write cycle, 3 5 gate 1 
writes the bus data into its memory base register, asserts the 

signal pin RPLYO H, and enables its address 90 ‘logic. If the 

cycle is a read cycle, the gate array asserts RPLYO H, and the 
contents of the external I/O page CSR are output. (The gate array 
does not drive the data lines.) 


The value written into the memory base register sele 
starting address, or base address, of a 56-Kbyte block 
addresses to be decoded by the DMA gate array. The base address is 
always on a 64-Kbyte boundary in the Q22-Bus memory adereds space. 
All locations in this 56— Kbyte block are word-addressable only. 


ets the 


The DMA gate array segments the 56-Kbyte block of addresses and 
generates enable signals, as shown in Figure 3-44. The gate array 
asserts RPLYO H during any cycle that accesses any location in the 
56~-Kbyte address block. All addresses can be expressed as the sum 
of the Q22-Bus memory base, VCBO02 memory base, and offset (t the 
offset within the selected 56-Kbyte block). The Q22-Bus memory 
base is the system address of the first location in the 4-Mbyte 
Q22-Bus memory address space. The VCBO2 memory base is the offset 
of the first location of the VCBO02 memory address space (within 
the Q22-Bus memory address space). The VCBO02 memory base is 
selected by the value written to the memory base register. 


Functional Description 


HSH 


e US ee RNS nN iaiaDeAiSNA NAT AARUIONSKRINONANERionEOUNIN NGOS NaS 


ADDRESS SIZE OF BLOCK 


Q22-BUS MEMORY BASE + 
VCBO2 MEMORY BASE + E000 HEX 


Q22-BUS MEMORY BASE + 
VCBO2 MEMORY BASE + C400 HEX 


Q22-BUS MEMORY BASE + 
VCBO2 MEMORY BASE + ( 6200 HEX 


Q22-BUS MEMORY BASE + 

VCBO2 M EMORY BASE + COOO HEX 
TEMPLATE RAM 
Q22-BUS MEMORY BASE + 


7 BO2 MEMORY BASE + 8000 HEX 


US MEMORY BASE + 
J 02 MEMORY BASE + 0000 HEX 


64 KB BOUNDARY 


MPL BOF 


Figure 3-44 DMA Address Map 


3.5.1.1 ROMENB Decode — When any location in the first 32 Kbytes 
(offset 0000 hex to 7FFF hex) of the 56-Kbyte address block is 
accessed, the DMA gate array asserts the signal pin ROMENB L. 
ROMENB L is used as an enable for the external console 
emulation/diagnostic ROM on the base module. The DMA gate array 
does not drive the bus data lines when ROMENB L is decoded. 


3.5.1.2 RAMOE Decode ~~ The DMA gate array asserts the signal pin 
RAMOE L when a Q22-Bus cycle accesses any location in the next 16 
Kbytes (offset 8000 hex to BFFF hex) of the 56-Kbyte address 
block. RAMOE L enables the template RAM for access. The gate array 
completes the Q22-Bus cycle by performing the desired operation on 
the template RAM. Q22-Bus slave accesses of the template RAM are 
allowed at any time, and temporarily halt any display list 
execution that may be in progress. Execution of the display list 
resumes when the slave cycle is completed. 


Functional Description 


ß cA SET RSS IN NOON 


„ Address Processor Chip Addresses — The next 256 word 
locations (512 bytes, offset C000 hex to CIFF hex) are reserved 
for address processor chip registers. If one of the address 
processor chip locations is being accessed, the gate array 
completes the Q22-Bus cycle by performing the desired operation on 
the address processor chip. The DMA gate array temporarily halts 
the execution of display lists to allow Q22-Bus Slave accesses at 
any time. Execution of the display list resumes when the slave 
cycle is completed. 


3.5.1.4 Gate Array Addresses -- The next 256 word locations (512 
bytes, offset C200 hex to C3FF hex) are reserved for registers 
internal to the DMA gate array. Q22-Bus address bits ADO9 H 
through ADO1 H are decoded to select registers, as shown in Table 
3-3. Currently, only nine register addresses are utilized. 


_Table a 3 Sate Array Add 

922 ~Bus Address 1 

09 08 07 06 05 04 03 02 01 3 5 

Sen aaa Status reg 

DMA address counter 

DMA address counter 
(15 
(21 


ess Decoding 


EN BNR EOIN daa eee null ene. 


. 
ee, 


: DMA byte counter 
: DMA byte counter 


eet ee Se se & 
i Le Fe 


— 


FIFO register 
Cursor X position „ 
Cursor Y position regi 
W 5 


ani Se SSE DA aS IE DOO ESE CE BNIB ebenda 


i 5 


ter 
ster 


X 
X 
X 
X 
X 
X 
x 


OFF OOFR OO 
SrFOrFOrROFS 


X = Don't care 


3.5.1.5 IOENB Decode -~ If a location in the next 7 Kbytes 
oo. ‘t C400 hex to DFFF hex) of the 56-Kbyte address block is 
accessed, the DMA gate array asserts the signal pin IOENB L. IOENB 
L is used as an enable for an external decoder on the base module 
that segments the 7-Kbyte address block to provide register space 
for the communications controller, the memory page control and 
status register, and the color maps (red, green and blue). The DMA 
gate array does not drive the data bus lines when IOENB L is 
decoded. 


3.5.2 DMA Engine 
The DMA logic provided by the DMA gate array can perform three 
basic types of DMA transfers: 


l. Processor-to- bitmap trar isfers (PTB) 
2% Bitmap-to-processor transfe ( 
Sis Display list transfers. 


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eee eee 


1 


mode 


and DMA 


f 


) 


an 
2 
eee, 


w 


performed 


e 


b 


to 


of 


number 


the 


cy 


t DMA byte counte 


22-bi 


er 


~ount 


0 


rd 


low wo 


he 


1. 
un 


the 


— has 


larly, 


on 
wo 
D 


load the DMA byte counte 
b 


. 
st 


to 
DMA proc 


from 


tance 


8 


aie 


ass l 


any 


error bit 


) 


uO 


bit 


error 


ph 
is 
1e 
to 


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f 


( 


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le) 

4 

a 0 


Par 


to 


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4 
ss 


15 
St 
S 


ue: 
bus 

n 

9 


ers 
ro 


f 
€ 


During the 
5 
r 
nti 


Dp 
DMA r 
= 
word transf 


2-Bus 
dealt ene we Leet Kaze 


th 
2 


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Q 

op 

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performed. 


are 


sfers 


e. 
Bos 
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ood 
= 


FIFO. 


64—word 


a 


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5 


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a e 


0 


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addre 


ate RAM cycle. 


Functional Description 


. p PhWWrrſWWWWWWWWWW77WWE—＋kõö; — 


13 of register 2 indicate the number of words in the FIFO (0 = 
empty, 63 = full). The MicroVAX CPU can access the FIFO locations 
directly by addressing the first 64 words in the template RAM. 
Accessing the FIFO by addressing the template RAM does not affect 
the FIFO pointers. The MicroVAX CPU should not access the FIFO 
register or modify any of the FIFO locations by addressing the 
template RAM unless there is no active DMA process. 


The MicroVAX CPU can be used to load/unload the FIFO instead of 
the DMA engine provided by the DMA gate array. Once the DMA mode 
is selected, the DMA gate array transfers the data between the 
address processor chip and the FIFO identically, independent of 
the loading or unloading method (MicroVAX CPU or DMA). 


If the address processor chip is the DMA destination, the DMA gate 
array transfers a word out of the FIFO whenever one or more 
locations are filled, provided the address processor chip's DMA 
request signal (signal pin ADDRQ L) is asserted. If the address 
processor chip is the DMA source and has data ready (signal pin 
ADDRQ L is asserted), the gate array transfers the data to the 
FIFO whenever at least two locations are free. 


If bitmap-to-processor byte mode is selected, DMA data can be 
"byte packed" as it passes through the DMA gate array. Byte 
packing takes the low bytes of two consecutive words in the FIFO 
and "packs" them into one word for transfer to the Q22-Bus 
destination. The low byte of the first word read from the FIFO 
becomes the low byte of the packed word. The low byte of the 
second word read from the FIFO becomes the high byte of the packed 
word. The packed word is then transferred to the Q22-Bus 
destination. If the MicroVAX CPU is used to unload the FIFO 
instead of the DMA engine, it must perform the byte packing task. 
Paragraph 3.5.2.2 describes the intended use of byte packing. 


If processor-to-bitmap byte mode is selected, DMA data can be byte 
unpacked as it passes through the DMA gate array. Byte unpacking 
takes the low byte of a word read from the Q22-Bus and "unpacks" 
it into two words for transfer to the FIFO. The low byte of the 
Q22-Bus word is written to the low byte of the first FIFO 
location. The high byte of the Q22-Bus word is written to the low 
byte of the next FIFO location. If the MicroVAX CPU is used to 
load the FIFO instead of the DMA engine, it must perform the byte 
unpacking task. Paragraph 3.5.2.1 describes the intended use of 
byte unpacking. 


When the Q22-Bus is the DMA source and byte unpacking is disabled, 
the DMA gate array initiates a DMA transfer only when there are at 
least 17 free locations in the FIFO. When the Q22-Bus is the DMA 
destination and byte packing is disabled, the DMA gate array 
initiates a DMA transfer whenever there are at least 16 FIFO 
locations containing data (except at the end of the DMA process, 
when the DMA byte counter is less than 32). Twice as many FIFO 
locations are used for each Q22-Bus word transferred when byte 
unpacking is enabled. 


Functional Description 


NNO ANNUM e 


VET 


When the Q22-Bus is the DMA source and byte unpacking is enabled, 

the DMA gate array initiates a DMA transfer only when there are at 
least 33 free locations in the FIFO. When the 022-Bus is the DMA 
destination and byte packing is enabled, the DMA gate array 
initiates a DMA transfer whenever there are at least 32 FIFO 
locations containing data (except at the end of the DMA process, 
when the DMA byte counter is less than 64 

locations are used for ea 

packing is enabled. 


* Twice as many FIFO 
ach O22 - Bus word transferred when byte 


3.5.2.1 * 


rocessor~to-Bitmap Transfers — Processor 
mode is sele 


ce te 
sted by setting the DMA mode 1 bit (10) a 
O bit (09) of the control and status reg 


2a 
the DMA fede 18 SR). 
The Q22- . S the DMA source and the address processor chip is 
the DMA de ation during processor-to- pear transfers. All 


words trans 
chip IDD¹ re egi 
types of proces 
transfers. 


ins 
ee are data words written to the address processor 
ste (address processor chip 3 7). The two 
sor- 9 bitmap transfers are single-plane and Z-axis 


A Single-plane processor-to-bitmap transfer moves data 
Q22-Bus memory to one bitmap plane (the video memory associ 
with one video processor chip). Each woré a 16 bits that 
(Th ) 
a 


Fror 

ate 

i t. 

are adjacent horizontally. e@ end c ori zontal line 5 
(b 

( 


m 
2d 
© 

adjacent to the start of the next horizontal line.) The LSB 

0) of the word is the leftmost pixel in the displa he MSB (bi 
15) is the rightmost pixel. 
A Z-axis processor-to-bitmap transfer moves data from the Q22-Bus 
memory to a Single pixel location. (Each plane receives one bit of 
the data.) Since the VCB02 supports a maximum of eight planes, two 
words can be byte packed into one word to reduce the amount of 
Q22-BuS memory required to store a copy of a multiplane bitmap 
image. The gate array can unpack the bytes as the data is read 
from the Q22-Bus. Each byte of the word is stored in separate word 
locations in the FIFO, The low byte is written to the FIFO first 
The high byte is written to the low by f the next word loc cation 
in the FIFO. Subsequently, the DM ate . transfers the 
unpacked data from the FIFO to the address processor chip. By 
us ing byte unpacking, the number of Q22-Bus 5 can be 
reduced, resulting in higher system performance. Byte unpacking is 
enabled by setting the byte enable bit (08) in the control and 
status register. 


t 
1 


„ Bitmap- to- Processor Transfers — Bitmap- to- processor DMA 
mode is selected by resetting the DMA mode 1 bit (10) and setting 
the DMA mode 0 bit (09) of the control and status register (CSR). 
The Q22-Bus is the DMA destination and the address processor chip 
is the DMA source during bitmap-to-processor transfers. All words 
transferred are data words read from the address processor chip 
IDD register (address processor chip register 7). The two types of 
bitmap-to-processor transfers are Single-plane and Z-axis 
transfers. All data read from the address processor chip is loaded 
into the FIFO directly. The DMA gate array transfers the data from 
the FIFO to the selected Q22~-Bus location. 


Functional Description 


nimi i lect 


A single-plane bitmap-to-processor transfer moves data from one 
bitmap plane (the video memory associated with one video processor 
chip) to Q22-Bus memory. Each word contains 16 bits that are 
adjacent horizontally. (The end of a horizontal line is adjacent 
to the start of the next horizontal line.) The LSB (bit 0) of the 
word is the leftmost pixel in the display, the MSB (bit 15) is the 
rightmost pixel. 


A Z-axis bitmap-to-processor transfer moves data from a Single 
pixel location. (Each plane contributes one bit of the data.) 
Since the VCBO2 supports a maximum of eight planes, two words can 
be byte packed into one word to reduce the amount of Q22-Bus 
memory required to store a copy of a multiplane bitmap image. The 
byte packing is performed as the data is read from the FIFO for 
transfer to the Q22-Bus. Byte packing takes the low byte of the 
first word read from the FIFO and saves it in the low byte of a 
holding register. The low byte of the second word read from the 
FIFO is written to the high byte of the holding register. The byte 
packed data in the holding register is then transferred to the 
Q022-Bus. By using byte packing, the number of transfers on the 
022-Bus can be reduced, resulting in higher system performance. 
Byte unpacking is enabled by setting the byte enable bit (08) in 
the control and status register. 


3204289 Display List Transfers — Display list DMA mode is 
selected by resetting the DMA mode 1 bit (10) and setting the DMA 
mode 0 bit (09) in the control and status register (CSR). The 
O22- Bus is the DMA source and the address processor chip is the 
DMA destination during display list transfers. Both commands and 
data may be contained in the words read from the Q22-Bus. The 
022~Bus DMA logic in the DMA gate array transfers words from the 
022-Bus to the FIFO (the first 64 words of the template RAM). 


The transfer of data and commands from the FIFO to the address 
processor chip is controlled by the display list processor logic 
in the gate array. As the words are read from the FIFO, the 
display list processor conditionally decodes each word. If the 
word is decoded as a display list assist command, the display list 
processor executes the command as specified in Paragraph 3.5.5. 
Some display list assist commands are transferred to the address 
processor chip, others are not. All words read from the FIFO that 
are not recognized as display list assist commands are transferred 
to the address processor chip. Command and data encoding are 
detailed in Paragraph 3.5.5. 


3-115 


Functional Description 


c ¶ 


bebe 


3 Interrupt Controller 

The DMA gate array provides a 3-bit interrupt controller. One 
interrupt is connected internally to the DMA logic, the other two 
are connected to the input pins IRQ] L and IRQ2 L. On the VCBO2 
base module, IRQ] L is connected to the address processor chip's 
interrupt output, and IRQ2 L is connected to the communications 
controller interrupt output. When set, the external interrupt 
enable bit (02) of the control and status register (CSR) masks the 
external interrupts. When set, the DMA interrupt enable bit (01) 
in the CSR masks the internal DMA interrupt. When the mask is set 
the interrupt(s) is(are) ignored. If any of the interrupts are 
asserted but not being masked, the gate array asserts IRQ L 
(interrupt output). An external interrupt is asserted by 
generating a high-to-low transition on the input pin and 
maintaining the low level until the interrupt is acknowledged. The 
DMA interrupt is asserted if the slave device reports a memory 
parity error (CSR bit 06), or a bus timeout condition occurs (CSE 
bit 05). The DMA interrupt is also asserted when the DMA done bit 
(CSR bit 15) is set. 


During a Q22~Bus interrupt acknowledge cycle, the gate array 
latches the three interrupts when DIN H is asserted. If none of 
the interrupts is asserted, the gate array asserts IAKO H when 
TAKI H is asserted. If a nonmasked interrupt is asserted when IAKI 
H is received, the gate array outputs a priority encoded interrupt 
vector, asserts RPLYO H, and clears the highest priority 
interrupt. Bits 00, 01, and 09 through 15 of the interrupt vector 
are always 0 during an interrupt acknowledge cycle. Bits 04 
through 08 of the vector are Programmable by writing to the 
interrupt register. Bits 02 and 03 of the vector are encoded 
according to the highest priority interrupt asserted, and unmasked 
as shown in Table 3-4, 


The interrupt register i 
being read, 1e 
e 


readable. While the vector register is 
through 15 of the 


8 8 
nterrupts are latched and are read on bits 12 
c : 


1 
vector register. (Refer to Paragraph 3.5.6.9.) 


Table 3~4 Interrupt Register Vector Bits 02 and 03 


auen O Rina ORION Rat sn SEC ee 0 1 sao oor soma vi pepo Oca nete. 


Priority Interrupt Vector Bit 03 Vector Bit 02 
Highest DMA Interrupt 

Second IRQ] L. 
Lowest IRQ2 L. 


ee 


IE OSCARS PPR SOR ono RDNA RENAO LEHRER 


Functional Description 


igi ase ele lll laben api REO AR A oi 


3.5.4 Cursor Logic 

The cursor logic generates a 2-plane (A and B), 16 X 16 pixel, 
bitmap cursor for use by external video output logic. The cursor 
data can be enabled for output at any pixel location, and may be 
positioned on- or off-screen (that is, on = active video, off = 
video blanking). When set, the cursor enable bit (00) in the 
control and status register (CSR) enables the output of cursor 
data. The position is selected by the values written to the cursor 
Xx position register and cursor Y position register. The X position 
register and Y position register should only be modified during 
the vertical syne period, or when the cursor enable bit (00) in 
the CSR is reset (cursor is disabled). 


The Y position register is loaded into an up counter (requires 
2's complement data) on the second horizontal sync pulse during 
the vertical retrace period. (BLANK H remains asserted for at 
least two horizontal sync periods.) The Y counter is incremented 
by the trailing edge of BLANK H (the start of each active video 
line). The contents of the Y counter are checked on the leading 
edge of CSYNC H (during the horizontal retrace period preceding 
the next scan line). If the cursor enable bit (00) in the CSR is 
set, and all except the four least significant bits of the Y 
counter are set, the cursor is enabled for output on the new 
display line, and two cursor data words (16 bits) are read from 
the template RAM. 


The last 32 locations of the template RAM are reserved for cursor 
bitmap data. The first 16 of these words are cursor "A" data, the 
last 16 words are cursor "B" data. The least significant 4 bits of 
the Y register select which cursor "A" and cursor "B" word to 
read. As the Y counter is incremented by succeeding scan lines, 
the address of the cursor A and cursor B data words increments. 
(As the monitor is scanned from top to bottom, the cursor data is 
output from lowest address to highest address.) The reading of 
cursor data has the highest cycle priority. (Display list 
execution, Q22-Bus DMA, Q22-Bus slave cycles, and display list 
execution are all lower in priority.) 


When the cursor data is enabled for output on a display line, the 
X counter determines the position on the line that the data is 
output. Bits 02 through 10 of the X position register are loaded 
into an up counter (requires 2's complement data) by horizontal 
sync pulses (present on CSYNC L). The X counter is incremented 
(effectively by 4 since the Xx counter begins with bit 02) by 
CURCLK H (cursor clock). CURCLK H is one-fourth the VCBOZ video 
pixel clock frequency. 


The cursor data is output when all bits of the X counter are set. 
(Bits 02 through 10 are all 1s.) The least significant two bits of 
the cursor X position register shift the cursor data so that it is 
pixel-aligned. (Refer to Paragraph 3.5.6.7 for details). The 
cursor data must be shifted up to speed by shift registers 
external to the gate array. The shift registers should be loaded 
synchronously on the leading edge of CURCLK H. 


Functional Description 


F . lA EMMA EATER AMRIT RyANEARNIRIURATNIRNRNAKiGKiiNTiRiNNMiKIiNKeRiNSoMARiNINNKMUNeNIE 


3.5.5 Display List Data and Commands 

The commands described in the following section provide 
flexibility in the use of the template RAM as a local store RAM 
for routines that can be called from DMA display lists (display 
lists transferred from the Q22-Bus by the DMA gate array). In 
addition to commands that start and stop execution of template 
display lists (routines stored in the template RAM), commands are 
included that allow data and commands stored in the FIFO to be 
used by template display lists. One of the commands allows 
processor-to-bitmap transfers to be imbedded in a DMA display 
list. Each command is described in detail in the following 
sections. 


3.5.5.1 Display List Data — All words in a display list that 
have bit 14 and 15 reset, as shown in Figure 3-45, are considered 
to be display list data by the gate array and are transferred to 
the address processor chip's ADCT register (register 0). Bits 0 
through 13 are data bits and may have any value. The address 
processor chip writes the word to the register being selected by 
its ADCT register. Display list data can be used in template 
display lists and DMA display lists. 


Se Dee JMPT e ADDRESS Command — The JMPT e ADDRESS command has 
bits 15 and 13 reset, and bit 14 set, as shown in Figure 3-46. 
When executed by the display list processor, the JMPT @ ADDRESS 
command loads the word address (A011 through 13) contained in bits 
0 through 12 into an address counter in the gate array called the 
template address counter. If the address bits A07 through Al3 are 
reset, the display list processor resumes execution of the display 
list contained in the FIFO. If any of the address bits A07 through 
Al3 are set, the display list processor executes the template 
display list at the specified address. This command provides the 
ability to "call" a template display list from a DMA Display list, 
to "jump" within template display lists, and to end the execution 
of the template display list and return to execution of the DMA 
display list in the FIFO. The JMPT @ ADDRESS command is not 
transferred to the address processor chip. 


l PTB NWORDS Command —— The PTB NWORDS command has bit 15 
reset, and bits 14 and 13 set, as shown in Figure 3-47. Bits 00 
through 12 (NOOO through N12) are a 2's complement count value. 
When executed by the display list processor, the PTB NWORDS 
command loads the count into a counter in the gate array. The 
command is not transferred to the address processor chip. The gate 
array transfers the next N words (N is the count value) from the 
FIFO directly to the address processor chip's IDD register 
(register 7). Display list execution resumes from the FIFO (even 
if the PTB NWORDS command was executed from a template display 
list). The PTB NWORDS command allows processor-to-bitnap transfers 
of up to 8 K words to be imbedded in a DMA display list. However, 
the data must not be byte packed. 


3-118 


Functional Description 


eee dg 


ig 


O5 4 03 02 01 00 


j i 005 | 004 | DOS | DO2 01 | DOC 
| L 


Figure 3-45 Display List Data 


| A13 | A12 | Att 


— 


Figure 3-47 PTB NWORDS (Processor-to-Bitmap Transfer 
Number of Words) 


3.5.5.4 Other Display List Commands — All other display list 
commands recognized by the DMA gate array are encoded in bits 12 
through 15 of the word, as shown in Figure 3-48. Bits 00 through 
11 of the word may be used as data for loading the address 
processor chip's ADCT register. (The address processor chip only 
uses bits 00 through 05. Bits 06 through 11 are reserved.) All 
commands must have bit 15 set. All commands that have bit 14 
cleared are transferred to the address processor chip, causing the 
ADCT register to be loaded (bit 15 set). When bit 13 of the 
command word is set, the display list processor logic fetches the 
next word from the FIFO. (The word may be data or a command.) Bit 
12 disables the command decoding of the next word fetched by the 
display list processor logic (allows 16-bit data to use bits ll 
through 15). Though many combinations of bits 12 through 15 are 
anticipated to be useful in the execution of display lists, some 
combinations of these bits may not be. 


Pea PT Oe uu 


DATA BIT 09 


DATA BIT 08 


185 
— 
= 
Boies 


ini 


a 


DATA BIT O. 


DATA BIT 03 


IT O1 


eee 


Commands 


i 


ny 
i 


y Lo 


6 


MAP BS 


DATA BIT 00 


Other Displa 


3-48 


Figure 


Functional Description 


32086 Register Descriptions 

The following paragraphs describe the usage of each bit of all 
registers in the DMA gate array accessible from the Q22-Bus. All 
registers are word-accessible only. 


3453651 Control and Status Register (Register 0) — The control 
and status register (CSR) provides various control and status bits 
for the various functions the DMA gate array provides. Each bit is 
described in Figure 3-49. 


DMA DONE 
READ/WRITE DONE SELECT 
READ-ONLY RESERVED 
READ-ONLY RESERVED 
READ-ONLY RESERVED 
READ/WRITE DMA MODE BIT 1 
READ/WRITE DMA MODE BIT O 
READ/WRITE BYTE ENABLE 
DMA ERROR 

READ-ONLY SLAVE PARITY ERROR 
READ-ONLY BUS TIME-OUT ERROR 
READ/WRITE CURSOR TEST ENABLE 
READ/WRITE DMA TEST ENABLE 
READ/WRITE EXTERNAL INTERRUPT ENABLE 
READ/WRITE DMA INTERRUPT ENABLE 


READ/WRITE CURSOR ENABLE 


KAR TES Te 


Figure 3-49 CSR Register Bitmap 


3-121 


Functional Description 


neun 


DMA done 
the 


1 ie ni 
L& 


Lese 


Done 


The done 
DMA done 
(14) enables 
counter 


th 
2 
Si 


13: Reserved 
— 13 1 8 
When the 


12: Reserved 


2 A 
When th 


CSR bit 
effect. 


8 
Bit ll: Reserved 


. 14 18 
hen the 


DMA Mode 


5 


2 


cre 


0 oie bho 


ot 


FIFO 


Rolo nee isi TR 


( Read- On! y ) 


b 
5 
OMA 


Select 


bit (15) 


Dit: (18) 
FIFO is empty; it 
t and the DMA byte counter 


is 


i 


is also 


n INIT 
15) has 


Di 
( 


(Read/Write) 


bit 
to 
do 


(14) 
be set. 
ne bit (1 


reset whenever 
it is also reset whenever the done select bit (14) 
TE not empty. 


is set whenever the DMA byte 
set whe 


selects the 


conditions 
Writing a 0 to the done 
5) to be set whenever 


ii iii iain sei oii igi ele ene 


the DMA byte counter is 
is set 


counter is 0 
enever the done select bit 


is 0. 


that enable the 
select bit 
the DMA byte 


1e DMA byte counter must be 0 and the FIFO must be 


e DMA 
See 
gnal pin QINIT H 


ee 


done bit (15 


the 


(Read-Only) 


erved for 


read, 


(Read-Only) 


reserved 


CSR 


3— 
ser * 


ood 


70 


ead-Onl 


and 


ing the 
Should no 
is 


2) 


La 


for 


is read, bit 1 


8 


y) 


for 
bit 1 


rved 
read, 


1 (Read/Write) 


10 contro 
1ows the b 
the da oa pi 

not be modi 
empty. 


n 
fi 
(Read/Write) 


10 
shows 


control 
the 


t be 
empty. 


fu 


Zz 
Lt 


) 


bit 


if 2 1 
F 
ets 


i. 


future 
bit 13 1: 


550 


eakumeenmlilunn 


is written to the done 
for CSR bit 15 above. 


the DMA select bit (14). 


use. Writing bit 13 has 


always 0. 


use. Writing bit 12 has 


always 0. 


use. Writing bit 
always 0. 


10 


the operation mode of the DMA 


ed 


settings 
QINiIT 
unless 


for the various DMA 
H resets bit 10. The DMA 
the DMA byte counter 


the operation mode of the DMA 


settings 
Signal pin QINIT H resets bit 
modified unless 


various DMA 
9. The DMA 
the DMA byte counter 


for the 


sss ection einige ie NRO pn SD SET e Ue a RGB A Ua OO AON 


_ Functional Description 


Table 3-5 CSR Bits 8, 9, and 10 
CSR 10 CSR 09 CSR 08 DMA Function 


X Halt 

X Display List 

0 BI tmap- to- Processor (word) 

L Bitmap-to-Processor (byte packed) 

0 Processor~-to-Bitmap (word) 

1 Processor-to-Bitmap (byte unpacked) 


X = Don't care. 


Bit 08: Byte Enable (Read/Write) 


CSR bits 8, 9, and 10 control the operation of the DMA engine. 
(Refer to Table 3-5.) The byte transfer enable bit (08) is 
effective during processor-to-bitmap (PTB) and bitmap-to-processor 
(BTP) transfers only. Setting the byte enable bit (08) enables 
byte packing/unpacking during PTB/BTP transfers. (Refer to 
Paragraphs 3.5.2.1 and 3.5.2.2.) The byte enable bit (08) should 
not be modified unless the DMA byte counter is 0 and the FIFO is 
empty. 


CSR bit 10: DMA Mode 1 


CSR bit 09: DMA Mode 0 
CSR bit 08: Byte Enable 
Bit 07: DMA Error (Read/Write) 


Writing a 0 to CSR bit 07 has no effect. Writing a 1 to CSR bit 07 
resets the DMA error bit (07), the slave parity error bit (06), 
and the bus timeout error bit (05). 


The DMA error bit (07) is reset when the slave parity error bit 
(06) and the bus timeout error bit (05) are both reset. Asserting 


eee 


Bit 06: Slave Parity Error (Read-Only) 


If a slave parity error occurs while the DMA gate array is the bus 
master, the slave parity error bit (06) and the DMA error bit (07) 
are set. Writing a 1 to CSR bit 07 or asserting the signal pin 
QINIT H clears the slave parity error bit (06). Writing CSR bit 06 
has no effect. 


Bit 05: Bus Timeout Error (Read-Only) 


If a bus timeout error occurs while the DMA gate array is the bus 
master, the bus timeout error bit (05) and the DMA error bit (07) 
are set. Writing a 1 to the CSR bit 07 or asserting the signal pin 
INIT H clears the bus timeout error bit (05). 


3-123 


Functional Description 


‘iiss ints BES SUE RU RA GR ee initia Gig ß ORG ICR NSIS 


Bit 04: Cursor Test Enable (Read/Write) 


Writing a 1 to the cursor test enable bit (04) enables a special 
test mode for the cursor logic in the DMA gate array. This test 
mode is intended for use in device testing only. For normal 
operation, the cursor test enable bit (04) must be reset. 


Bit 03: DMA Test Enable (Read/Write) 


Writing a 1 to the DMA test enable bit (03) enables a special test 
mode for the DMA logic in the DMA gate array. This test mode is 
intended for use in device testing only. For normal operation, the 
DMA test enable bit (03) must be reset. 


Bit 02: External Interrupt Enable (Read/Write) 


Writing à 1 to the external interrupt enable bit (02) enables the 
Signal pins IRQ] L and IRQ2 L to generate an interrupt. Writing a 
0 to the external interrupt enable bit (02) disables all external 
interrupts. Asserting the signal pin QINIT H resets this bit. 


Bit 01: DMA Interrupt Enable (Read/Write) 


Writing a 1 to the DMA interrupt enable bit (01) enables the DMA 
done bit (15), or the slave parity error bit (06), or the bus 
timeout error bit (05), to generate an interrupt. Writing a 0 to 
the -DMA interrupt enable bit (01) disables all DMA interrupts. 
Asserting the signal pin QINIT H resets this bit. 


Bit 00: Cursor Enable (Read/Write) 


Writing a 1 to the cursor enable bit (00) enables the cursor logic 
to output cursor data. Writing a 0 to the cursor enable bit 
disables the output of cursor data. This bit should be modified 
only during the vertical retrace period. Asserting the signal pin 
OINIT H resets this bit. 


3.5.6.2 DMA Address Counter (15:00) (Register 1) — The DMA 
address counter (15:00) is the low word of the 22-bit DMA address 
counter provided by the DMA gate array. The low 16 bits of the 
Q22-Bus DMA source/destination address are loaded into this 
register. If an odd value is written to the DMA address counter, 
the first DMA transfer is a byte transfer and the counter is 
incremented by 1. If an even value is written to the DMA address 
counter, the first transfer is a word and the counter is 
incremented by 2. With the exception of the last transfer, all 
subsequent DMA transfers are word transfers and the counter is 
incremented by 2. 


Functional Description 


If the DMA byte counter is even for the last transfer (byte count 
= 2), the transfer is a word transfer and the DMA address counter 
is incremented by 2. If the DMA byte counter is odd for the last 
transfer (byte count = 1), the transfer is a byte and the DMA 
address counter is incremented by 1. The DMA address counter 
(15:00) overflows into the DMA address counter (21:16) when it is 
at maximum count and is incremented. Whenever the DMA address 
counter (15:00) is written, the DMA address counter (21:16) must 
Subsequently be written to maintain valid data. The counter should 
not be written unless the DMA byte counter is 0 (the Q22-Bus DMA 
process is complete). The DMA address counter (15:00) is readable. 
Figure 3-50 shows the DMA address counter register 1 bitmap. 


3.5.6.3 DMA Address Counter (21:16) (Register 2) — The DMA 
address counter (21:16) is the high 6 bits of the 22-bit DMA 
address counter provided by the DMA gate array. The high 6 bits of 
the Q22-Bus DMA source/destination address are loaded into this 
register. The counter is incremented when the DMA address counter 
(15:00) is at maximum count and is incremented. Whenever the DMA 
address counter (15:00) is written, the DMA address counter 
(21:16) must subsequently be written to maintain valid data. The 
counter should not be written unless the DMA byte counter is 0 
(the Q22-Bus DMA process is complete). The DMA address counter 
(21:16) is not readable. Bits 07 through 15 of this register have 
no effect when written. Figure 3-51 shows the DMA address counter 
register 2 bitmap. 


DMA ADDRESS COUNTER (15:00) READ/WRITE 


. 


Figure 3-50 DMA Address Counter Register 1 Bitmap 


DMA ADDRESS COUNTER (21:16) WRITE-ONLY 


A ee a ee ee are eee. ew 


MA 0 


Pigure 3-51 DMA Address Counter Register 2 Bitmap 


Functional Description 


Fe es ae ee 


3.5.6.4 DMA Byte Counter (15:00) (Register 3) — The DMA byte 
counter (15:00) is the low word of the 22-bit DMA byte counter 
provided by the DMA gate array. The low 16 bits of the Q22-Bus DMA 
byte count are loaded into this register. If an odd value is 
written to the DMA address counter, the first DMA transfer is a 
byte transfer and the byte counter is incremented by 1. If an even 
value is written to the DMA address counter, the first transfer is 
a word and the byte counter is incremented by 2. With the 
exception of the last transfer, all subsequent DMA transfers are 
word transfers and the counter is incremented by 2. 


If the DMA byte counter is even for the last transfer (byte count 
= 2), the transfer is a word transfer and the counter is 
incremented by 2. If the DMA byte counter is odd for the last 
transfer (byte count = 1), the transfer is a byte transfer and the 
counter is incremented by 1. The DMA byte counter (15:00) 3-111 
overflows into the DMA byte counter (21:16) when it is at maximum 
count and is incremented. Whenever the DMA byte counter (15:00) is 
written, the DMA byte counter (21:16) must subsequently be written 
to maintain valid data. The counter should not be written unless 
the DMA byte counter is 0 (the Q22-Bus DMA process is complete). 
The DMA byte counter (15:00) is readable. Figure 3-52 shows the 
DMA byte counter register 3 bitmap. 


3.5.6.5 DMA Byte Counter (21:16) (Register 4) — The DMA byte 
counter (21:16) is the high 6 bits of the 22-bit DMA byte counter 
provided by the DMA gate array. The high 6 bits of the Q22-Bus DMA 
byte count are loaded into this register. The counter is 
incremented when the DMA byte counter (15:00) is at maximum count 
and is incremented. Whenever the DMA byte counter (15:00) is 
written, the DMA byte counter (21:16) must subsequently be written 
to maintain valid data. The counter should not be written unless 
the DMA byte counter is 0 (the Q22-Bus DMA process is complete). 
The DMA byte counter (15:00) is readable. Figure 3-53 shows the 
DMA byte counter register 4 bitmap. 


When read, bits 08 through 13 contain the FIFO count (number of 
words in the FIFO). If the FIFO count is 0, the FIFO is empty. If 
the FIFO count is 63, the FIFO is full. Reading the DMA byte 
counter (21:16) temporarily halts the execution of display lists. 
Display list execution resumes when the Q22-Bus read cycle is 
completed. Bits 07 through 15 of this register have no effect when 
written. 


DMA BYTE COUNTER (15:00) READ/WRITE 


Figure 3-52 DMA Byte Counter Register 3 Bitmap 


f 
FIFO COUNT 5 
dN 
* 
FIFO COUNT 2 
2 
0 
V 


RESERVED 
F 
RESERVED 


C21 
1 
i 
1 
1 


DMA Byte Counter Register 4 Bitmap 


DMA BYTE COUNTER (21:16) 


READ-ONLY 
READ/WRITE 
READ/WRITE 


READ/WRITE 
READ/WRITE 


READ-ONLY 
READ-ONLY 
READ-ONLY 
READ-ONLY 
READ-ONLY 
READ-ONLY 
READ-ONLY 
READ-ONLY 


F 
f 


Figure 


a 
al 


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3.5.6.6 FIFO Register (Register 5) — The FIFO implemented by the 
DMA gate array uses the first 64 word locations of the template 
RAM. The gate array maintains two pointers into the RAM that 
control the loading and unloading process. The MicroVAX CPU can 
access the FIFO by addressing register 5 (FIFO register). When the 
MicroVAX CPU accesses the FIFO register, the appropriate pointer 
(read or write) is incremented and used as the address for the 
template RAM cycle. 


FIFO data always passes through the DMA gate array. The MicroVAX 
CPU can determine how many words are in the FIFO by reading 
register 2 (DMA address counter <21:16>). Bits 08 through 13 of 
register 2 indicate the number of words in the FIFO (0 = empty, 63 
= full). The MicroVAX CPU can access the FIFO locations directly 
by addressing the first 64 words in the template RAM, Accessing 
the FIFO by addressing the template RAM does not affect the FIFO 
pointers. The MicroVAX CPU should not access the FIFO register or 
modify any of the FIFO 3-112 locations by addressing the template 
RAM if a DMA process is active. Figure 3-54 shows the FIFO 
register bitmap. 


3.5.6.7 Cursor X Position Register (Register 6) -- 


NOTE 
The format of the data loaded into the 
cursor & position register is complex. 


a 


Bits 02 through 10 of the X position register are loaded into an 
up-counter by the first cursor clock pulse (signal pin CURCLK H) 
after the assertion of the signal pin CSYNC H (that is, during 
the horizontal sync interval). The second CURCLK H pulse completes 
the synchronous load of the 2's complement value into the X 
counter. Beginning with the third CURCLK H pulse, the X counter is 
incremented (effectively by 4 since the X counter begins with bit 
02) by CURCLK H (cursor clock). CURCLK H is one-fourth the pixel 
frequency. The cursor data is output when all bits of the X 
counter are set (bits 02 through 10 are all 1). Because the X 
counter begins counting during the horizontal retrace period, an 
offset must be included in the data loaded into the cursor X 
position register in order to position the cursor at the left edge 
of the active video line. Refer to the algorithm in Figure 3-55. 


The data loaded into the X counter (bits 02 through 10 of the 
cursor X position register) must be 2's complement data. The two 
least significant bits of the cursor X position register cannot be 
2's complement data. 


Functional Description 


FIFO REGISTER READ/WRITE 


MP TWD 


Figure 3-54 FIFO Register Bitmap 


CURSOR X POSITION REGISTER WRITE-ONLY 


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| 


2 oO Dc 


00 [OO 
SOG [GO moo 
= OO 


| 
| 


@ OO 


200 GO 


Noo 


OO = BIT OO OF THE CURSOR X POSITION REGISTER 
iT T 


XO1 = BIT OO OF THE CURSOR X POSITION REGISTER 


CURO = THE CURAO H OR CURBO H OUTPUTS OF THE GATE ARRAY 
CUR1 = THE CURA1 H OR CURB1 H OUTPUTS OF THE GATE ARRAY 
CUR2 = THE CURA2 H OR CURB2 H OUTPUTS OF THE GATE ARRAY 
CUR3 = THE CURA3 H OR CURB3 H OUTPUTS OF THE GATE ARRAY 


po, ..., 015 = BIT O,..., 15 OF THE CURSOR A OR B DATA READ FROM THE TEMPLATE 


MA 6984 


Figure 3-55 Cursor X Position Register Bitmap and Algorithm 


3-129 


Functional Description 


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The two least significant bits of the cursor X position register 
shift the cursor data so that it is pixel-aligned. (Refer to 
Figure 3-55.) The cursor X position register should be modified 
only during the vertical sync interval, or when the control and 
Status register cursor enable bit (02) is reset. After modifying 
the cursor & position register, at least one CSYNC H pulse must 
occur prior to the start of the first active display line. 
(Equalization pulses are required unless a least one blank line 


occurs after the release of the vertical sync pulse.) The cursor X 


position register cannot be read. Writing bits 12 through 15 has 
no effect. 


3.56.8 Cursor Y Position Register (Register 7) — The cursor * 
position register is loaded into an up-counter on the second 
horizontal sync pulse during the vertical retrace period. (BLANK H 
remains asserted for at least two horizontal syne periods.) The Y 
counter is incremented by the trailing edge of BLANK H (the start 
of an active video line ) The contents of the Y counter are 
checked on the leading edge of CSYNC H (during the horizontal 
retrace preceding the next scan line). If control and status 
register bit 02 is set, and all except the four least significant 
bits of the X counter are set, the cursor is enabled for output on 
the current display line, and two cursor data words (16 bits) are 
read from the template RAM. The cursor Y position register should 
be modified only during the vertical sync period, or when the 
cursor enable bit (02) in the CSR is reset (cursor is disabled). 
After modifying the cursor Y position register, at least two CSYNC 
H pulses must occur prior to the 9 of BLANK H (the end 
of the vertical syne blanking interval). The cursor Y position 
register cannot be read. Writing bits a to 15 has no effect. 
Figure 3-56 shows the cursor Y po ositi ion register bitmap. 


ge 


‘it 


3.5.6.9 Interrupt Register (Register 8) -- The interrupt register 
provides interrupt status to the MicroVAX CPU. When read, the 
status bits are latched by the assertion of oe Signal pin DIN H 
and remain latched until DIN H is removed. By writing the 
interrupt register, the base for the interrupt vector output by 
the DMA gate array during interrupt acknowledge cycles can be 
selected. (Refer to Paragraph 3.5.3.) Each bit is described in 
Figure 3-57. 


Bit 15: Latched IRQ (Read-Only) 


The latched IRQ b (15) is set whenever the latched DMA IRO bit 
latched IRO bit (13), or latched IRQ2 bit (14) is set. 
bit 15 h 10 effect. Asserting the signal pin QINIT H 

g 8 


51 t 
1 
5 as on 
resets the latched IRQ bit (15). 
Bit 14: Latched IRQ2 (Read-Only) 


The latched IRQ2 bit (14) is set whenever the control and status 
register external interrupt enable bit (02) is set and the signal 
pin IRQ2 L becomes asserted (the adder chip is requesting 
| ervice). Writing bit 14 has no effect. Asserting the 
INIT H resets the latched IROQ2 Bit (14). 


fa 


i 8 
Signal pin Q 


nia iis coi 


CURSOR Y POSITION REGISTER 


15 12 1 


Figure 3-56 Cursor Y 


READ-ONLY 
READ-ONLY 
READ-ONLY 


READ-ONLY 


READ-ONLY 
READ-ONLY 


READ-ONLY 


Figure 3-57 


Functional Description 


ion 


ME 


Position Register Bitmap 


LATCHED DMA IRQ 


RESERVED 


RESERVED 


VECTOR BASE 08 


VECTOR BASE 07 


VECTOR BASE 06 


VECTOR BASE 05 


VECTOR BASE 04 


INTERRUPT VECTOR O03 


INTERRUPT VECTOR O2 


RESERVED 


RESERVED 


MT OG 


Interrupt Register Bitmap 


3~131 


Functional Description 


Bit 13: Latched IROI (Read-Only) 

The latched IROI bit (13) is set whenever the control and status 

register external interrupt enable bit (02) is set and the signal 

pin IRQl L becomes asserted (the communications controller is 

requesting interrupt service). Writing bit 13 has no effect. 

Asserting the signal pin INIT H resets the latched IRQ] bit (13). 

Bit 12: Latched DMA IRQ (Read-Only) 

The latched DMA IRQ bit (12) is set whenever the control and 

Status register DMA interrupt enable bit (01) is set and a DMA 

interrupt occurs. The DMA interrupt status can be read from the 

control and status register (register 0). Writing bit 12 has no 

effect. Asserting the signal pin QINIT H resets the latched DMA 

TRO bit, 213)5 

Bit ll: Reserved (Read-Only) 

When read, bit 11 is always reset. Writing bit 11 has no effect. 

Bit 10: Reserved (Read-Only) 

When read, bit 10 is always reset. Writing bit 10 has no effect. 

Bit 09: Reserved (Read-Only) 

When read, bit 09 is always reset. Writing bit 09 has no effect. 

Bit 08: Vector Base 8 (Read/Write) 

Bit 08 of the interrupt vector output by the DMA gate array is 

selected by writing this bit. The vector base 8 bit (08) is reset 

when the signal pin QINIT H is asserted. 

Bit 07: Vector Base 7 (Read/Write) 

Bit 07 of the interrupt vector output by the DMA g 
( 


selected by writing this bit. The vector base 7 bit 
when the signal pin QINIT H is asserted. 


te array is 
7) is reset 
Bit 06: Vector Base 6 (Read/Write) 

Bit 06 of the interrupt vector output by the DMA gate array is 


Selected by writing this bit. The vector base 6 bit (06) is reset 
when the signal pin QINIT H is asserted. 


3-132 


Functional Description 


Bit 05: Vector Base 5 (Read/Write) 

Bit 05 of the interrupt vector output by the DMA gate array is 
selected by writing this bit. The vector base 5 bit (05) is reset 
when the signal pin QINIT H is asserted. 

Bit 04: Vector Base 4 (Read/Write) 

Bit 04 of the interrupt vector output by the DMA gate array is 
selected by writing this bit. The vector base 4 bit (04) is reset 
when the signal pin QINIT H is asserted. 

Bit 03: Interrupt Vector 3 (Read-Only) 

The interrupt vector 3 bit (03) is priority encoded and is 
determined by the status of the latched DMA IRQ bit (12), latched 
IRQ] bit (13), and the latched IRQ2 bit (14), as shown in Table 
3-6. Writing bit 03 has no effect. 

Bit 02: Interrupt Vector 2 (Read-Only) 

The interrupt vector 2 bit (02) is priority encoded and is 
determined by the status of the latched DMA IRQ bit (12), latched 
IRQ] bit (12), and the latched IRQ2 bit (14), as shown in Table 
3-6. Writing bit 02 has no effect. 

Bit Ol: Reserved (Read-Only) 

When read, bit 01 is always reset. Writing bit 01 has no effect. 
Bit 00: Reserved (Read-Only) 


When read, bit 00 is always reset. Writing bit 00 has no effect. 


Table 3-6 Interrupt Vector 3 Determination 


Latched Latched Latched Interrupt Interrupt 
IRQ2 IRQ] DMA IRQ Vector 3 Vector 2 
X X 0 0 0 

* 0 1 0 1 

0 1 1 1 0 

1 1 1 1 1 

1 1, 1 1 1 


3133 


Functional Description 


3.5.6.10 Memory Base Address Register -- A power reset disables 
the address decoder in the DMA gate array. To enable the address 
decoder, a value must be written to the I/O page control and 
Status register (CSR) and decoded external to the gate array by 
logic on the base module. When this address is detected, the 
external decoder asserts the CONSEL L. signal pin on the gate 
array. If the cycle is a write cycle, the DMA gate array writes 
the bus data into its memory base register, asserts the signal pin 
RPLYO H, and enables its address decoding logic. If the cycle is a 
read cycle, the gate array asserts RPLYO H, and the contents of 
the external I/O page CSR are output. (The gate array does not 
drive the data lines.) 


The value written into the memory base register selects the 
Starting address, or base address, of a 56-Kbyte block of 
addresses that are decoded by the DMA gate array. The base address 
is always on a 64-Kbyte boundary in the Q22-Bus memory address 
Space, as selected by bits 00 through 05 of the memory base 
register. Bits 05 through 00 are compared with the signal pins 
A(21:16) H during the address portion of Q22-Bus memory cycles. 
Figure 3-58 shows the memory base register bitmap. 


i A21 | A20 | A19 | A LA 
4! ͤ A Soenent Seana, Sona Leesa 


VET Qe 


Figure 3-58 Memory Base Register Bitmap 


se Signal Description 


3.5.7.1 Q22-Bus Interface -- The signals described in thi 
section are provided by the DMA gate array for interfacing to th 
Q22-Bus. 


lo 
e 


AD 


(15:00) H -- Address/Data (Input/Output, Tri-state) 

These multiplexed address and data lines are used for both master 
and slave cycles on the Q22-Bus. During the address portion of a 
DMA transfer (master) cycle, the DMA gate array outputs the lower 
16 bits of the DMA destination address on AD(15:00) H. When the 
gate array is a Q22-Bus slave device, it latches the address 
information received on AD(15:00) when SYNC H is asserted. 


3-134 


Functional Description 


Table 3-7 DMA Gate Array Signals 


unebenen enden RS e ernennen bebe 


Signal Description 


VVV 


VVV 


Q22-Bus Interface The signals needed to interface to the 
Q22-Bus, both as a slave and master 
device. 


Address Decodes The signals decoded from the 922-Bus 
address lines whenever the DMA gate array 
is not the bus master; can be used for 
selecting devices that need to be 
interfaced to the Q22-Bus. 


Interrupt Inputs The inputs that may be connected to 
interrupt sources external to the DMA 
gate array. 


Address Processor The address and control signals needed to 
Chip Interface interface to the address processor chip. 


Template RAM Interface The address and control signals for the 
template RAM. 


Private Data Bus A 16-bit bidirectional data bus that 
connects the DMA gate array, the template 
RAM, and the address processor chip. 


Cursor Signals The cursor data outputs and the signals 
that control the timing of the cursor 
logic. 


Miscellaneous Signals The signals common to the entire gate 
array but not associated with any one 
group of signals. 


TMM TAM MMMM MMM TMM MMR MTN ATM MMMM MTA MSRM MNT MMMM MMM MTT MMMM MTR INSOMNIA TK 


During the data portion of a Q22-Bus cycle, these lines contain 
read or write data, depending on the type of transfer. Bits 
AD(15:08) are defined as the high byte and bits AD(07:00) are the 
low byte of data. If the DMA gate array is the bus master, it 
outputs data on AD(15:00) during data-out cycles (DOUT H asserted) 
and receives data on AD(15:00) during data~in cycles (DIN H 
asserted). If the template RAM, the address processor chip, or a 
gate array register is being addressed during a slave cycle, the 
gate array receives data on AD(15:00) during data-out cycles (DOUT 
H sserted) and drives data on AD(15:00) during data-in cycles 

(DIN H asserted). 


Functional Description 


CFT 


A (17:16) H -- Addressy Parity (Input/Output, Tri-state) 


During the address portion of Q22-Bus cycles, these two lines are 
used as address lines. If the gate array is not the bus master 
(not performing DMA transfers), A(17:16) H are compared with bit 
01 and bit 00, respectively, of the memory base register. If the 
bits are not equal when SYNC H is asserted, the address decode 
logic is disabled. When it is the bus master (during DMA 
transfers), the DMA gate array drives addresses on these lines 
only during the address portion of cycles. 


When the gate array is the bus master performing a data-out cycle 
(DOUT H asserted), A(17:16) fare driven to the deasserted state 
(all zeros) during the data portion of the cycle. When the gate 
array is a Q22-Bus slave device responding to a data- in cycle (DIN 
H asserted), it drives A(17:16) H to the deasserted state. (This 
disables memory parity detection.) The gate array receives these 
lines at all other times. 


When the DMA gate array is performing a DMA read cycle (DIN H 
asserted), A(17:16) H are used to check for slave memory parity 
errors during the data portion of the cycle. A slave device 
asserts bit Al17 H to inform the gate array (the bus master) that 
it has parity error detection logic. If a parity error occurs on 
the slave memory device, the slave asserts bit Al6 H to indicate 
the error. 


A(21:18) H -- Address (Input/Output, Tri-state) 


During the address portion of Q22-Bus cycles, these lines are used 
as address lines. When it is the bus master (during DMA 
transfers), the DMA gate array outputs addresses on these lines 
only during the address portion of cycles. When the gate array is 
the bus master performing a data-out cycle (DOUT H asserted), 
A(21:18) H are driven to the deasserted state (all zeros) during 
the data portion of the cycle. (This disables bus parity 
detection.) When the gate array is a Q22-Bus slave device 
responding to a data-in cycle (DIN H asserted), it drives A(21:18) 
H to the deasserted state. The gate array receives these lines at 
all other times. 


If the gate array is not the bus master (not performing DMA 
transfers), A(21:18) H are compared with bits 05, 04, 03, and 02, 
respectively, of the memory base register. If the bits are not 
equal when SYNC H is asserted, the address decode logic is 
disabled. 


B87 H ~~ Bank Select 7 (Input/Output, Tri-state) 


B87 H is asserted if 


During the address portion of Q22-Bus cycles, 
the Q22-Bus I/O page is being addressed. 


3~136 


Functional Description 


During the data portion of Q22-Bus DATBI cycles, B87 H is asserted 
to indicate to the slave device that the bus master wants to 
perform a block-mode cycle. The Q22-Bus specification does not 
require the assertion of BS7 during the data portion of Q22-Bus 
DATBO cycles. The DMA gate array asserts BS7 H when it is the bus 
master (performing DMA) during the data portion of both DATBI and 
DATBO cycles. The gate array receives BS7 H at all other times. 


If the gate array is not the bus master (not performing DMA 
transfers), and BS7 H is asserted when SYNC H is asserted, the 
address decode logic is disabled (that is, the address decode 
10910 in the gate array is disabled whenever the Q22-Bus I/O page 
is being addressed). 


WTBT H -~ Write/Byte (Output, Tri-state) 


The DMA gate array asserts WTBT H only when it is the bus master. 
WTBT H is asserted by the bus master during the address portion of 
a cycle to indicate that an output cycle (DATO, DATOB, DATBO) 
rather than an input cycle, is to follow. WTBT H is asserted by 
the bus master during the data portion of a DATOB or DATIOB bus 
cycle to indicate a byte transfer, rather than a word transfer, is 
to take place. 


NOTE 
As a slave, the DMA gate array is 
word-addressable only. As a master, the 
gate array can perform byte transfers. 


SYNC H —— Synchronize (Input/Output, Tri-state) 


The bus master asserts SYNC H to indicate that it has placed an 
address on the bus. The transfer is in process until SYNC H is 
negated. When doing block moves, SYNC H remains asserted until the 
last transfer is completed. SYNC H is not asserted during 
interrupt acknowledge cycles. 


The DMA gate array drives SYNC H only when it is the bus master. 
SYNC H is an input at all other times. 


DIN H —— Data Input (Input/Output, Tri-state) 


If SYNC H is not asserted while DIN H is asserted, the cycle is an 
interrupt acknowledge cycle. The gate array latches the interrupt 
request status on the leading edge of DIN H. 


If DIN H is asserted while SYNC H is asserted, a Q22~Bus read 
cycle is being performed. The addressed slave device drives the 
bus with data, and the master inputs the data. When the gate array 
is a Q22-Bus slave device, it receives DIN H and asserts RPLYO H 
to complete the cycle. 


The DMA gate array outputs DIN H when it is the bus master (and is 
performing a read cycle). The slave device must respond by 
asserting RPLYI H to complete the read cycle. 


3-137 


Functional Description 


ue CCVVVVVVVVVVVVVVVVVV ATOPIC ic OiNAnNNiRANNnidNNNniNiRTaiNiNiRAiNEsiNNRIMNNORNONMRRE 


DOUT H- Data Output (Input/Output, Tri- state) 


DOUT H is asserted by the bus master during data output (write) 
cycles. The bus master asserts DOUT H after it outputs the data to 
the bus. The slave device must respond by asserting RPLYI H to 
complete the write cycle. 

The DMA gate array outputs DOUT H when it is the bus master (and 
is performing a write cycle). When the gate array is a Q22-Bus 
Slave device, it receives DOUT H and asserts RPLYO H to complete 
the cycle. 


RPLYO H -~ Reply Output (Output, Tri-state) 


de DMA gate array is selected as the bus slave, it asserts 
1 in response to DIN H or DOUT H. RPLYO H indicates to the 
dus master that the gate array has placed its data on the bus 

DIN H is asserted), or has accepted data from the bus (DOUT 
1 is . 


When ti 
ie E 


If the DMA gate array is asserting IRQ H when IAKI H is received, 
it places the appropriate interrupt vector on the bus and asserts 
RPLYO H to indicate it has accepted the interrupt acknowledge. 


LVO H is never asserted when the DMA gate array is the bus 


RPLYI H ~~ Reply Input (Input) 


When the DMA gate array is the bus master, RPLYI H is monitored to 
determine when the selected bus slave is ready to complete the bus 
cycle. RPLYI H indicates to the gate array that the slave device 
has placed its data on the bus (when DIN H is asserted), or has 
accepted data from the bus (DOUT H is asserted). 


DMRO H —— Direct Memory Access Request Output (Output, Tri-state) 
The DMA gate array ass e DMRO H to request bus mastership of the 
Q22-Bus. After bus mastership is granted to the DMA gate array, 
the gate array asserts SACK H and deasserts DMRO H. 

DMRI H —— Direct Memory Access Request Input (Input) 

When the DMA gate array is the bus master, it monitors DMRI H to 
stermine if another DMA device is requesting bus mastership. 


t 
Under certain conditions the gate array gives up bus mastership to 
llow another DMA device to acquire it. 


3138 


Functional Description 


DMGI H -- Direct Memory Access Grant Input (Input) 


The MicroVAX CPU asserts DMGI H to indicate it is granting bus 
mastership to a Q22-Bus device. If the DMA gate array is asserting 
DMR H (requesting the bus) when DMGI H becomes asserted, it waits 
for the deassertion of SYNC H and RPLYI H, asserts SACK H, and 
removes DMRO H. (The gate array becomes the bus master.) 

If the gate array does not assert DMRO H when it is received, the 
gate array asserts DMGO H and passes the DMA grant to the next 
Q22-Bus device. 


DMGO H — Direct Memory Access Grant Output (Output, Tri-state) 


The DMA gate array asserts DMGO H, if the DMGI H signal is 
asserted, and not asserting DMRO H (not requesting bus 
mastership). 


SACK H Signal Acknowledge (Output, Tri-state) 


SACK H is asserted by the DMA gate array when it has acquired bus 
mastership of the Q22-Bus. The signal indicates that the gate 
array is accepting bus mastership. The gate array keeps SACK H 
asserted until it gives up bus mastership. 


The DMA gate array requests bus mastership by asserting DMRO H. 
When DMGI H is received and DMRO H is asserted, the gate array 
waits for the deassertion of SYNC H and RPLYI H, asserts SACK H, 
and removes DMRO H. (The gate array becomes the bus master.) 


SACK H also controls the direction of the transceiver for the 
Q22-Bus signals SYNC H, DIN H, DOUT H, WTBT H, and BS7 H. When 
SACK H is asserted, the VCB02 base module transmits the control 
signals. When SACK H is deasserted, the base module receives the 
control signals. 


REF H -- Refresh (Input) 


As bus master, the DMA gate array monitors this signal to 
determine if the slave device is a block-mode device. Block-mode 
Slave devices assert this line along with RPLYI H, if they are 
able to do subsequent data transfers. Slave devices that do not 
support block mode do not assert this line. 


NOTE 
The DMA gate array is a block mode 
master, not a block mode slave device. 


3-139 


Functional Description 


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IRQ H ~~ Interrupt Request (Output, Tri-state) 


is line when it requires an interrupt 

the Q22-Bus. Two 5585 (01 and 02) in the control and status 
register are provided to enable/disable the internally connected 
Interrupt and the external interrupts IRQ] H and IRQ2 H (from 
ddress processor chip and communic cations controller). 


The DMA gate array asserts thi 
tl 2 


IRQ H deasserts when the interrupt request is removed or IAKI H is 
received acknowledging the interrupt. 


joe 
a 


The interrupt priority level of the DMA gate array 
position-dependent. (See Appendix A.) 


IAKI H- Interrupt Acknowledge Input (Input) 


The 10 rOVAX % aàsserts IAKI H to acknowledge an interrupt 

os If the DMA gate array is asserting IRQ H when it receives 

it outputs an interrupt vector and clears the highest 

i : IAKI H is received by the gate array when 

5 the gate array outputs IAKO H to pass the 
to the next 9Q22-Bus slot. 


ior 3 1 el of the DMA gate array is 
8 


TAKO H — Interrupt Acknowledge Output (Output, Tri-state) 


the DMA gate array is not requesting an interrupt and receives 
‘I H the gate array asserts IAKO H. The assertion of this 
propagates the interrupt acknowledge to the next Q22-Bus 


If the DMA gate array receives IAKO H and is re equesting an 
interrupt, the gate array does not assert IAKO H. 

interrupt priority evel of the DMA gate array is 
-ion-dependent. (See 


oe a! 


QINIT H Initialize (Input) 


NIT H is used by the DMA gate array as as 
NJ E 


oftware reset. When 
IT H is asserted, the following states are effec 


ted in the gate 


1% The address decoder is disabled. The memory base register 
has to be rewritten before accessing any locations other 
than the VCBO2 subsystem's 1/0 page control status 

5 


i 


register. 


Ad 


° Control and status register bit 15 is set. All other 
control and status register bits are reset 


ct 


Functional Description 


CCCCCCCCCVVVVVVVVVVVVVVVVVVVVVVVVVV iam MARI eROAA 


a. The DMA logic in the gate array is reset, causing any DMA 
transfers in progress to be aborted. 


4. The 22 bits of the DMA address counter are reset. 
Ds The 22 bits of the DMA byte counter are reset. 

6. The FIFO pointers are reset. (The FIFO is empty.) 
7. The template address counter is reset. 

8. All interrupts are disabled. 

4 The hardware cursor is disabled. 

10. The cursor X position register is reset. 


ll. The cursor Y position register is reset. 


9 


POK L Power Okay (Input) 


POK L must be asserted to enable the DMA gate array to request bv 
mastership. When POK L is deasserted, the DMRO H output 
disabled. (The gate array cannot request bus mastership.) If 
is deasserted while the DMA gate array is the bus master, 
not abort the DMA process. If POK L remains deasserted, the gate 
array is prevented from acquiring bus mastership again after it 
completes the current DMA process. 


BTIMEO L -- Bus Timeout (Open Collector Output, Tri-state) 


BTIMEO L is used to discharge a timing capacitor external to the 
gate array (connected through a current limit resistor).This 
capacitor is used to generate a bus timeout error when the slave 
device fails to assert REPLYI H in response to a DIN H or DOUT H 
data strobe within 10 us (approximate time constant of charging 
circuit). If REPLYI H is asserted before the 10 us limit, the gate 
array deasserts the data strobe (DIN H or DOUT H) and asserts 
BTIMEO L, which discharges the capacitor (preventing a bus timeout 
error). 


BTIMEI H is used to monitor the voltage on the capacitor. Whe en 
BTIMEO L is deasserted, the capacitor begins to charge Sethe 

timing period). If the capacitor voltage exceeds the logic hi 
input threshold of the BTIMEI H input, a bus timeout error occu 


1 — 
20 
S 


a 


When the gate array is a slave device, BTIMEO L is always 
asserted. When the DMA gate array is the bus master, BTIMEO L is 
asserted (when both DIN H and DOUT H are not asserted). 


Functional Description 


r apne gai eatin amigo rd ß ONT 


BTIMEI H —— Bus Time Input (Input, Schmitt Trigger) 


BTIMEI H is used to detect a Q22-Bus timeout when one occurs. When 
the DMA gate array is bus master and asserts DIN H or DOUT H, the 
gate array stops driving BTIMEO L, which allows an external timing 
capacitor to charge. If the slave device has not asserted RPLYI H 
by the time this input exceeds the logic high input threshold, a 
bus timeout error occurs, and the bus timeout bit (05) and DMA 
error bit (07) in the control and status register (CSR) are set. 
tf the DMA interrupt enable bit (01) in the CSR is set, the DMA 
gate array asserts IRQ H (request interrupt service). 


i! 


DTIMEO L. —— DMA Delay Timeout (Open Collector Output, Tri-state) 


DTIMEO L is used to discharge a timing capacitor external to the 
gate array (connected through a current limit resistor). This 
capacitor is used to generate a delay between requests for bus 
mastership by the DMA gate array. DTIMEO L is asserted whenever 
SACK H is asserted. (The gate array is the bus master.) When the 
gate array gives up bus mastership (SACK H is deasserted), DTIMEO 
L deasserts and the timing capacitor begins to charge (begins 
timing the delay). 


DTIMEI H is used to monitor the voltage on the capacitor. Until 
the capacitor voltage reaches the logic high threshold for DTIMEI 
H, the DMA gate array cannot request bus mastership (DMRO H is 
disabled). When the capacitor voltage exceeds the logic high 
threshold of DTIMEI H, DMRO H is enabled and the gate array can 
request bus mastership again. 


DTIMEI H -- DMA Delay Time Input (Input, Schmitt Trigger) 

he voltage on an external timing capacitor. 
When DTIMEI His ow, the DMA gate array does not request bus 
mastership. (DMRO His disabled.) The external capacitor is 
discharged by DTIMEO L whenever the gate array is the bus master. 
When the gate array gives up bus mastership, the capacitor begins 
to charge. After a delay, the capacitor charges to a voltage that 
asserts DTIMEI H, and enables the gate array to request bus 
mastership again. 


DTIMEI H monitors t 
1 


XVRENO L. Transceiver Enable 0 (Output, Tri- state) 


XVRENO L is the enable for the transceiver for the Q22-Bus control 
Signals SYNC H, DIN H, DOUT H, WTBT H, and BS7 H. XVRENO L 
disables the transceiver when the DMA gate array transitions from 
Slave to master and master to slave. 


Functional Description 


ß 


XVRENI H —— Transceiver Enable 1 (Output, Tri-state) 


XVRENL H is the enable for the address and data transceivers for 
the Q22-Bus. XVREN] H disables the transceivers when at the 
leading and trailing edges of DIN H (except for IAK cycles). 
XVRENI H also disables the transceivers when the DMA gate array 
transitions from slave to master and master to slave. 


XVRRCV L — Transceiver Receive (Output, Tri-state) 


XVRRCV I. controls the direction of the Q22~-Bus transceivers for 
address and data. When XVRRCV L is asserted, the VCB0O2 base module 
receives data. When xXVRRCV L is deasserted, the base module 
transmits data. XVRRCV L is asserted/deasserted only when XVRENI H 
is deasserted (except for IAK cycles). 


3.5. 7.2 Address Decodes <- This section describes the signals 
provided by the DMA gate array for decoding Q22-Bus addresses. 
CONSEL L — Console Select (Input) 


CONSEL L is an external Q22-Bus address decode for 8 VCB02 
subsystem's 1/0 page control and status register (CSR If the 
Slave cycle accessing the I/O page CSR is a write Bari che DMA 
gate array writes the data into its memory base address register 
and enables the address decoder. If the slave cycle accessing the 
I/O page CSR is a read cycle, the gate array does not drive the 
AD(15:00) signals. The DMA gate array responds by asserting the 
RPLYO H line for both read and write cycles when CONSEL L is 
asserted. 


TOENB L — I/O Enable (Output, Tri-state) 


When the gate array is not the bus master, it asserts IOENB L when 
it decodes an address in the range VCBO2 memory base address + 
C400 (hex) to VCBO02 memory base address + DFFF (hex). IOENB L is 
used as an enable for an external decoder on the base module that 
segments the 7-Kbyte address block to provide register space for 
the communications controller, the memory page control status 
register, and the color maps (red, green, and blue). The DMA gate 
array does not drive the data bus lines when IOENB L is decoded. 


ROMENB LI. ROM Enable (Output, Tri-state) 


ROMENB L is an address decode for slave cycles that access the 
VCB02 base module's 1 The address range for the ROM is from 
VCB02 memory base addres 

address + 7FFF (hex). 


+ 0000 (hex) to VCBO2 memory base 


Functional Description 


HRSA CFF iii aii iii iain oii iit ii 


3.5.7.3 Interrupt Inputs — The interrupt inputs connected to the 
address processor chip interrupt output and the communications 
controller interrupt output are described in this section. An 
additional interrupt is provided internally to the DMA gate array 
for the DMA logic. Refer to Paragraph 3.5.7.1 for details on the 
Signals IRQ H, IAKI H, and IAKO . 


IRQ(2:1) LI Interrupt Request (2:1) (Input) 


IRQ2 L is connected to the communications controller on the VCBO2 
base module. IRQ] L is connected to the address processor chip on 
the VCB02 base module. The interrupt request signals are used by 
the external devices to indicate to the DMA gate array that 
service by the MicroVAX CPU is required. IRQ2 L and IRQ] L are 
asynchronous inputs that are low-level sensitive. Request for 
service must be held low until the interrupt has been 
acknowledged. An additional DMA interrupt is provided internal to 
the gate array. 


The interrupts are priority encoded, as shown in Table 3-8. During 
an interrupt acknowledge cycle, only the highest priority 
interrupt is cleared. IRQ(2:1) L may be masked by the external 
interrupt enable bit (02) in the control status register. The DMA 
interrupt may be masked by the DMA interrupt enable bit (01) in 
the control and status register. 


Table 3-8 DMA Interrupt Priority Encoding 


Interrupt 
Priority Level 
Highest IRQO Internal DMA interrupt 

IRQ] Address processor chip interrupt 
Lowest IRQ2 Communications interrupt 


snc i Ea 0 ano ee gde edee MASSETER ESSE IRAN dead ones ve ct ee SUL Ss 


Type 


3.5.7.4 Address Processor Chip Interface -~ The signals described 
in this section are the control signals between the DMA gate array 
and the address processor chip. 


AA (7:1) H ~~ Address Processor Address (Output, Tri~state) 
The VCBO2 uses only AA(6:1) H. AA(7) His reserved by Digital for 


Future use. AA(6:1) H select the address processor chip register 
being accessed. 


ADDAS L. -- Address/Data Strobe (Output, Tri-state) 


ADDAS L iS a combination of address strobe and data strobe for the 
address processor chip. The assertion of ADDAS L indicates that a 


3-144 


Functional Description 


MMMM MTN UMA miiirriiniiniiinminiin MRNA TTT MMM MANS I Naim NSIS siN i IOi 


valid address is present on the AA(7:1) H lines, and that the 
Signal ADDWR L is valid. For write cycles to the address 
processor, this indicates that valid data is on the PB(15:00) H 
lines. On read cycles from the address processor, ADDAS L enables 
data onto the data bus from the address processor. The address 
processor chip is word-addressable only. 


ADDWR L -- Address Processor Write (Output, Tri-~state) 


This line indicates a read or write operation to the address 
processor chip. If the signal is asserted when ADDAS L is 
asserted, the gate array is writing the address processor. If the 
line is deasserted when ADDAS L is asserted, the gate array is 
reading from the address processor. 


ADDRQ L -- Address Processor DMA Request (Input) 


AbDBR S L is a status line from the address processor chip that 
indicates the chip is ready for a secondary DMA transfer. The 
ADDRQ L signal is controlled by writing an enable mask to the 
address processor's request enable register. If the logical AND of 
the enable mask and the address processor's status register 
results in any bit being set, the ADDRQ L is asserted. ADDRQ L is 
used to synchronize secondary DMA transfers with the DMA gate 
array. 


3.5.7.5 Template RAM Interface — The signals described in this 
section are the control signals for the template RAM generated by 
the DMA gate array. 


TA(13:01) H -- Template Address (Output, Tri-state) 


The VCBO2 uses only TA(11:01) H. TA13 H and TA12 Hare reserved 
for future use by Digital. TA(11:01) H are address lines for the 
template RAM. The template RAM is word-accessible only. 


RAMWR L <-~ RAM Write (Output, Tri-state) 


RAMWR L. is the write strobe for the template RAM. The data on 
PB(15:00) is written to the template RAM on the trailing edge of 
RAMWR L.. 


RAMOE L -~ RAM Output Enable (Output, Tri-state) 


RAMOE L is the template RAM output enable control line. RAMOE L is 
asserted when the DMA gate array is performing a read cycle from 
the template RAM. RAMOE L is used to tri-state the template Rau“ s 
output drivers when it is not being read. 


3-145 


Functional Description 


3.5.7.6 Private Data Bus — The signals described in this section 
are the data lines that connect the DMA gate array to the address 
processor chip and the template RAM. 


PB(00:15) H ~~ Private Bus (Input/Output, Tri-state) 


These signals provide the data path between the DMA gate array, 
the template RAM , and the address processor chip. Any of these 
devices may receive or transmit data on these signal lines. All 
transfers on this bus are controlled by the gate array. 

in this section 
integrated into 


3.3.7.7 Cursor Signals — The signals described 
are used to generate a 2-plane cursor that can be 
the video data output logic. 


CURA(3:0) H -- Cursor A Plane Data (3:0) (Output) 


CURA(3:0) are the plane A“ cursor as outputs. This parallel 
data is output at one-fourth the Frequency of the VCBO2 
subsystem's video pixel clock, and is connected to an external 
shift register that generates a sinaie bit stream at the full 
VCB02 video pixel clock rate. CURCLK H is the clocking signal for 
CURA(3:0) H. 


CURB(0:3) H -~ Cursor B Plane Data (3:0) (Output) 


CURB(3:0) are the plane "B" cursor data outputs. This parallel 
data is output at one-fourth the frequency of the VCBO2 
subsystem's video pixel clock, and is connected to an external 
shift register that generates a single bit stream at the full 
VCBO02 video pixel clock rate. CURCLK H is the clocking signal for 
CURA(3:0) H. 


CURCLK H <= Cursor Clock (Input) 


CURCLK H is the clock used by all the cursor logic. This 50 
percent duty cycle clock is one-fourth the frequency of the 
VCB02 subsystem's video pixel clock. 


CSYNC L. — Composite Sync (Input) 


CSYNC L is used to generate horizontal and vertical load pulses 
for the cursor Xx and cursor Y counters. CSYNC L must have 
horizontal sync pulses during the vertical syne interval. CSYNC L 
is connected to the address processor chip's CMPSYN output. CSYNC 
L is clocked into the gate array on the rising edge of CURCLK H. 


Functional Description 


i init io SN SN I REORDER NOI 


BLANK H -- Video Blanking (Input) 


BLANK H is used to generate vertical load and count pulses for the 
cursor Y counter, and load pulses for the cursor XK counter. BLANK 
H is clocked into the gate array on the rising edge of CURLCK H. 
BLANK H must remain asserted during the vertical sync interval. 
BLANK H does “not disable the CURA(3:0) or CURB(3:0) outputs. BLANK 
H is connected to the address processor chip's BLANK output. 


„ Miscellaneous Signals — The signals described in this 
section are common to the entire gate array but not associated 
with a particular signal group. 


CLOCK H — Clock (Input) 


This is the system clock for the DMA gate array with a 50 percent 
duty cycle. The rising edge of CLOCK H is used to generate all 
timing in the gate array except the cursor timing. In the VCBO02 
subsystem, CLOCK His one-fourth the video pixel clock frequency. 


GOZ L Go Tri-state (Input) 


When this line is driven low, all tri-state outputs are disabled 
(go tri-state). This pin is for manufacturing testing only. 


3.5.8 Physical Description 

The following sections describe the package pin numbering and 
signal pin assignments of the DMA gate array. The package is a 
ceramic 120 PGA (pin grid array). 


Se debet Package Pin Numbering -- Figure 3-59 identifies the DMA 
gate array's pin numbers from the top view. Figure 3-60 shows the 
pin numbering from the bottom view. The top view is used when 
looking at the hole pattern for the gate array on the component 
side of the printed circuit board. The bottom view is used when 
looking at the pin side of the gate array package, or when looking 
at the hole pattern for the gate array on the etch side of the 
printed circuit board. 


3~147 


F e . e , Suh t t p e Noha BRERA onanNOniNnCiNeNIIKe 


Functional Description 


oo 


IDE AND THE NUMBERS ALONG THE BOTTOM 


ENTIFY THE GRID COORDINATE OF THE PIN. 
LUARES IDENTIFY THE PIN NUMBER. 


50 


0 
w 


1E 


L 
AGRAM ID 
BERS IN Tt 


| 


OF THE D 
N 


0 
+ 


MPT ee 


FRA PIN FOR KEYING THE PACKAGE 


ee 
% 


DICATES AN E; 
DMA Gate Array Pin Diagram (Top View) 


Figure 3-59 


3~148 


Functional Description 


nN 


G 77 75176 | 120-PIN GRID ARRAY 


NOTE: 
THE LETTERS ALONG THE SIDE AND THE NUMBERS ALONG THE BOTTOM 
OF THE DIAGRAM IDENTIFY THE GRID COORDINATE OF THE PIN. 
THE NUMBERS IN THE SQUARES IDENTIFY THE PIN NUMBER. 


THE + SYMBOL INDICATES AN EXTRA PIN FOR KEYING THE PACKAGE 
ORIENTATION. 


THE * SYMBOL INDICATES AN INSULATED STANDOFF FOR HOLDING THE 
PACKAGE UP OFF THE BOARD SURFACE. 


MATION & 


Figure 3-60 DMA Gate Array Pin Diagram (Bottom View) 


3-149 


Functional Description 


n Pin Signal Assignments — Table 3-9 lists the signal 
assignments of each pin in numerical order. The package pin grid 
coordinate, signal name, and the gates used for the receiver 
and/or driver are given for each pin. 


Table 3~9 


RELISTS SIS ISHS SEIES MMOS KOVR RIE 


Pin Grid 
Number 


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Gate Used Gate Used 
For Driver 


Number 


HR SEGREGATION eee 


. 
ee 


dl —— 


hed bed 


32150 


Ce onen unerduneeeedeeneeen 


[ROSES ZZZ Z N Æ⁰ I N nnen 


LDNOUUBUBWWENNWRENWE = O = S 0 PWN EN WEN EWN EN WE Nw 


VCC 

PB1 0 
PBO9 
PBO8 
PBO / 
PB OG 
PB O5 
PB O4 
PB O3 
PB O2 
PB O1 
PB OO 


RAMWR L. 
RAMOE L. 


GND 

VCC 

TA13 
TA12 
TALI 
TA10 
TAOS 
TAOS8 
1A07 


E A 


Signal Name 


eo onmeeusanseannsoincsion 


For Receiver 


bu setae RRR TN beet E SOS REED A DGGE ORDO EERO ASI UPUREA NOD SED ASUS 


TOCHTI 
TLCHTI 
TLCHTI 
TLCHTI 
TLCHTI 
TLCHTI 
TLCHTI 
TLCHTI 
TLCHTI 
TLCHTI 
TLCHTI 


TLCHTI 
TLCHTI 
TLCHTI 
TLCHTI 
TLCHTI 
TLCHTI 
TLCHTI 
TLCHTI 
TLCHTI 
TLCHTI 
TLCHTI 
TLCHTI 


BTS7L 
BTS7L 
BTS7L 
BTS7L 
BTS7L 
BTS7L 
BTS7L 
BTS7L 
BTS7L 
BTS7L 
BTS7L 
BTS1 

8781 


8781 
B78 1 
BT81 
BTS1 
BTS1 
8781 
BTS 1 
BTS 1 
BTS1 
BTS1 
BTS1 
BTS 1 
BTS1 


BTS /L 
BTS7L 
BTS7L 
BTS7L 
BTS7L 
BTS7L 
BTS7L 
BTS7L 
BTS7L 
BTS7L 
BTS7L 
BTS7L 


c INNA ARAN RIM 


deine 


duden 


neemt een mf m 


Aso 


RSAC RSNA SCRA RON MMMM ACD MMMM OMNES SNA SINISE SINR Est belebt, a 


Functional Description 


iii ini Naini tO oii iG eC un NENA 


Table 3~9 


ose aEaOvesrosUspeastEnRRRDINARDHEAES 


Pin 
ee 


MA Gate Array Pin Signal Assignments (Cont) 


beau daes eonon sino 


Grid 
Number 


ee oan canes 


Gate Used 
For Receiver 


Ss RESON REINO vos aeg ee 


Gate Us 6a 


Signal Name For Driver 


BeOS 


\WOPOUDNUMOUM M π N -Z HN Zr ZK ZK ZZ N= RK 2 
rm 
hae 


pe 
e 


ee 


RPLYI H 
RPLYO H 


SACK H 
XVRENI 
XVRENO 
XVRRCV 
DMGI H 
DMGO H 
REF H 

DMRI H 
DMRO H 


H 
L 
L 


IOENB L. 


ROMENB 
GND 
CONSEL 


L 


L 


QINIT H 


POK L 

GOZ L. 

DTIMEO 
DTIMET 
CLOCK 

BTIMEO 
BTIMEI 
IRQ H 

IAKO H 
IAKI H 
IRQ L. 
IRQ] L 
vCC 


CURB 3 ‘A 


2s SUR OSS HOSS 


Sipe oponit NENA 


L 
H 


H 


L 
H 


TLCHTI 
TLCHTI 


TLCHTI 
TLCHTI 
TLCHTI 
TLCHTI 
TLCHTI 
TLCHTI 
TLCHTI 
TLCHTI 
TLCHTI 


TLCHTI 
TLCHTI 


TLCHTI 
TLCHT 


TLCHT 


TLCHT 
TLCHT 


TLCHT 
TLCHT 
TLCHT 
TLCHT 


SCHMDT1 
TLCHT 


SCHMDT1 


TLCHT 


SCHMDT1 


SCHMDT1 


BTS7L 
378 7L 


BTS7L 
BTS7L 
BTS7L 
BTS7L 
BTS7L 
BTS7L 
BTS7L 
BTS7L 
BTS7L 
8781 

87871. 
87871 


BTS7L 
BTS1 
BTS1 
BTS1 
BTS1 
BTS1 
8781 
BTS 1 


BTS] 
BTS 1 


B10 


810 


BTS 1 
8781 


n 


se 


Functional Description 


anne wheel nem 


deem m 


Table 3-9 DMA Gate Array Pi: 


Grid 
mber 


Pin 


Number For Re 


Signal Name 


1 


— eee SS 


po 


2 
oni 


0 


A 
C 
B 
A 
B 
C 
A 
B 
A 


ae 


wD Ww « 


QO 


OD p< 


wo 


Way Dt 


aw 


— 
i ki lo) Ge BD oe Oe OF Ge ðĩ / = OO oo T ᷣ Se eR OS AG 


CURB2 
CURB1 
CURBO 
CURA3 
CURA2 
CURAL 
CURAO 


CURCLK H 


ef Pew a 


BLANK H 
CYSNC H 
ADDRQ L 
ADDWR L. 


VCC 
GND 
ADDAS 


L 


TLCHT 
TLCHT 
TLCHT 
TLCHT 


TLCHTI 
TLCHTI 
TLCHTI 
TLCHTI 
TLCHTI 


8781 
BTS 1 
BTS1 
BTS 1 
BTS1 
BTS1 
BTS1 
BTS 1 
BTS7L 
BTS7L 
BTS7L 
BTS 7L 
BTS7L 


Ho 


Tabl 


Vdd 
Ta = 


Vil 
Vih 


vt+ 
vt- 


ie 
Tih 


Vol 
Voh 


102 


Functional Description 


9 Input/Output Specifications 
e 3-10 lists the VCB02 I/O specifications. 


= 4.75 V to 5.25 V 
09°C to 70°C 


= Low-level input voltage 
= High-level input voltage 


= Schmitt trigger positive edge threshold 
= Schmitt trigger negative edge threshold 


= Low-level input current 
= High-level input current 


= Low~level output voltage 
= High-level output voltage 


= Tri~state leakage output current 


Table 3- 20 Input/Output Specifications 


ao te eK SCL OS DNR et AEE NETS HDPE ONL sage e c ORES OIA AAA ITI 


N 170 Gate Type Condition Min. Max. Unit 


auen 


Tih 


Vol 


Voh 


102 


— . e pff WWW 


TLCHT, TLCHTI Vss 0.8 Vv 
TLCHT, TLCHTI 2.0 Vdd v 
SCHMDT1 4.0 v 


SCHMDT1 1.0 V 


TLCHT Vin = VSS 0.5 
TLCHTI, SCHMDT1 ~10 uA 


TLCHT Vin = Vdd 20 MA 
TLCHTI, SCHMDT1 10 A 


Bl, B10D, BTS1, Iol = 2.0 mA 0.4 v 
BTS7L 
Bl, BTS1, BTS7L Ioh = -1.6 m 2.4 Vv 


B10D N/A * 
(open collector) 


BTS1, BTS7L, B1OD ~10 +10 BA 


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3— 


153 


Functional Description 


306.0 Timing Diagrams 
The following paragraphs contain timing diagrams for selected DMA 
gate array signals. 


Se ded Private Bus Timing — The following paragraphs contain 
the timing diagrams for all cycles on the private bus. The "state" 
changes on the rising edge of CLOCK H. 


Template RAM Write Cycle 
Figure 3-61 shows the timing for write cycles to the template RAM 


caused by slave writes to the template RAM or FIFO register, or by 
DMA writes to the FIFO. 


PExx 


TAxx 


NOTES: 
1. RAMOE LIS NOT ASSERTED DURING THIS CYCLE. 
2. ED 


SIGNA S THAT ARE APPEND ) WITH AN * ARE INTERNAL TO THE GATE ARRAY. 


MUR G98 


Figure 3-61 Template RAM Write Cycle Timing 


Functional Description 


Template RAM Read Cycle 

Figure 3-62 shows the timing for read cycles from the template RAM 
caused by slave reads from the template RAM or FIFO register, or 
by DMA reads from the FIFO. 


state | x [| © [| 1 [ 2 [ 3 | 4 | 5 fF © [| * 
BCNTA* 
BCNTB* 
BCNTC* 
BCNTD* 

TAxx 7 . 4 — 
e 
PBxx 
BDONE L* 
BUSDON H. 


LEB 


NOTES: 
1. RAMWR LIS NOT ASSERTED DURING THIS CYCLE. 
2. SIGNALS THAT ARE APPENDED WITH AN * ARE INTERNAL TO THE GATE ARRAY. 


NRT BQ 


Figure 3-62 Template RAM Read Cycle Timing 


3-155 


Functional Description 


eee 


eee 


neunen NN A ep AAO FP MT NRT IONS ODEON OA ER ON ia iio GOL OA 


slate RAM Read, Address Processor Write Cycle 

re 3-63 shows the timing for cycles that read from the 
plate RAM and write to the address processor chip (caused by 
execution of display lists or processor-to-bitmap DMA). 


als 
qu 


ANN 


P Ec 


BAK 


ADDAS 


AMWR L IS NOT ASS 
IALS THAT ARE / 


NA 1 GRD 


Figure 3-63 Template RAM Read, Address Processor Write 
Cycle Timing 


3-156 


Functional Description 


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eit 


RGR OA 


Address Processor Write Cycle 
Figure 3-64 shows the timing for 
processor chip caused by slave writes. 


sy ok glk quem le gow ow 
address 


= 
* 
. 
ct 
2 
— 
© 
al 
@ 
15 
ct 
O 
ct 
i 


STATE 


BC NTA“ 


BCNTB* 


BCNTC* 


BCNTD* 


PBxx 


AAN 


ADDWR L 


ADDAS L 


BDONE L* 


NOTES: 


Figure 3-64 Address Processor Write Cycle Timing 


Functional Description 


r ANNAN GRENSON 


Address Processor Read Cycle 
Figure 3-65 shows the timing for read cycles from the address 
processor chip caused by slave reads. 


STATE 


BCNTA* 


BCNTB* 


BCNTC* 


AAxx 


ADDWR L 


| 
wa 
| 
N 


NOTES: 
1. RAMOE L AND RAMWR L ARE NOT ASSERTED DURING THIS CYCLE. 
2. SIGNALS THAT ARE APPENDED WITH AN ARE INTERNAL TO THE GATE ARRAY. 


WAR 1 989 


ite 


Figure 3-65 Address Processor Read Cycle Timing 


3-158 


Functional Description 


eee 


eee ame dae ee 


Address Processor Read, Template RAM Write Cycle 

Figure 3-66 shows the timing for cycles that read from the address 
processor chip and write to the template RAM (caused by 
bitmap-to-processor DMA). 


ADDWR L |, 


ADDAS L | / 


TAxx Ke | | 


NOTES: 
1. RAMOE LIS NOT ASSERTED DURING THIS CYCLE. 
2. SIGNALS THAT ARE APPENDED WITH AN * ARE INTERNAL TO THE GATE ARRAY. 


Figure 3-66 Address Processor Read, Template RAM 
Write Cycle Timing 


Functional Description 


iii oN GiiNii REANIM RRO 


3. 5. 10. 2 Q22-Bus Timing -- The following paragraphs contain 
timing diagrams for DMA gate array Q22-Bus master cycles. 
"state" changes on the rising edge of CLOCK H. Timing diagrams 
the slave-to-master and master-to-slave transceiver enable 
direction signals are also provided. 


Slave-to-Master Transition 
Figure 3-67 shows the slave~to-master transition. 


Master~to-Slave Transition 
Figure 3-68 shows the master-to-slave transition. 


Master DIN Cycle 
Figure 3-69 shows the master DIN cycle. 


dim For block-mode transfers, the DMA machine state changes 
From state 23 to state 7. For non-block-mode transfers, 
the DMA machine state changes from state 23 to state 0. 


Zs If REF H is asserted by the slave device during any DMA 
cycle, the DMA gate array attempts 16 transfers, provided 
the DMA byte count is greater than or equal to 31. If REF 


H is not asserted by the slave device during 


transfers, the DMA gate array attempts a maximum of 8 
transfers, provided the DMA byte count is greater than or 


equal to 7. 


3% BUSRQ H and BUSDON H are internal signals and are 


presented on this timing diagram for reference only. 


Master DOUT Cycle 
Figure 3-70 shows the master DOUT cycle. 


1. For block-node transfers, the DMA machine state changes 
from state 23 to state 7. For non-block-mode transfers, 
the DMA machine state changes from state 23 to state 0. 


2% If REF H is asserted by the slave device during any DMA 
cycle, the DMA gate array attempts 16 transfers, provided 
the DMA byte count is greater than or equal to 31. If REF 


H is not asserted by the slave device during 


any 


transfers, the DMA gate array attempts a maximum of 8 
transfers, provided the DMA byte count is greater than or 


equal to 7. 


* 


presented on this timing diagram for reference only. 


BUSRQ H and BUSDON H are internal signals and are 


Functional Description 


INTERNAL DMA | : 
MACHINE STATES r 0 
CLOCKH ft 


DMRO H 


XRVENO L 


XVREN1 H 


XVRRCV L 


MRT Boos 


Figure 3-67 Q22-Bus Timing, Slave-to-Master Transition 


INTERNAL DMA | 2 | 
MACHINE STATES | 3 

CLOCK H 

DMRO H 

DMG! H 

XRVENO L 

SACK H 


XVRENT H 


XVRRCV L 


EPL OG. 


Figure 3-68 Q22-Bus Timing, Master-to- Slave Transition 


3-161 


cription 


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Functional Des 


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CHAPTER 4 
PROGRAMMING INFORMATION 


ee ee 


4.1 PROGRAMMING THE VCBOZ VIDEO SUBSYSTEM 


4.1.1 Hardware Support 
The VCBO 2 video subsystem hardware supports the following 
Features: 

1. The ability to transform, manipulate, and create images 
through a set of bitmap operations called raster 
operations (rasterops) at rates between 0.5 million and 8 
million pixels/s. 

2. A dedicated parallel data path processor for each plane of 
physical memory, resulting in a maximum bandwidth of 256 
million bits/s. 


3. Viewports, by providing clipping, along with horizontal 
and vertical smooth scrolling within a rectangular region. 


4. A text-writing rate of up to 20 thousand characters/s. 
5. Tiling, pattern, and half- tone generation. 
6. Polygon fill. 


7. %Z-axis read and write operations, to set the value of a 
pixel in a single operation. 


8. DMA of address processor commands from MicroVAX memory to 
the address processor. 


9. Storage and execution of address processor command 
"subroutines" in the VCBO2 template RAM. 


4-1 


Programming Information 


r . RENAN 


ee 


Figure 4-1 is a ee ee block diagram of the VCB0O2 video 
subsystem. The essential subsystem components are: 


1. Four or eight planes of bitmap memory. The bitmap is not 
directly accessible from the MicroVAX. 

2. One video processor (data path) chip for each plane of 
bitmap memory. This chip receives input data from the 
bitmap or I/D interconnect, operates on it as directed by 
its control registers, and makes the result available for 
screen refresh and rewrite into the bitmap. 


3. Chip select hardware that determines which set of video 


processor chips (bitmap planes) will participate ina 
scrolling or bitmap update operation. 


DUART 


1 
BITMAP MEMORY 
ADDRE 88 BUS 


BITMAP 7 


| BITMAP 
MEMORY | 


| memory] | 


| TEMPLATE | 
RAM 

| cursoR | 
| RAM | 


[arrmar oars 


| VIDEO | J vive | 


CURSOR 
VIDEO 


gee oR 


2 2 BUS were 


Figure 4-1 VCB02 Video Subsystem 


2 


4—2 


Programming Information 


4. The address processor chip (microsequencer); a custom LSI 
chip that implements the rasterop and scrolling 
algorithms. The outputs of this chip are memory addresses 
and commands to the video processor chips to perform 
rasterops, scrolling, and screen refresh. 


5. The I/D interconnect connecting the address processor chip 
to all video processor chips. This interconnect is used to 
broadcast commands and data to all video processor chips, 
to transfer bitmap data from the video processor chips to 
the address processor chip, and to load the update and 
scroll chip select registers. 


6. The DMA gate array, to accelerate the transfer of data and 
commands between the MicroVAX CPU and the address 
processor. 


The VCBO2 hardware executes a set of raster operations to 
manipulate and create images, and performs horizontal or vertical 
scrolling of any rectangular region on the screen. The VCBO2 
subsystem has a 2-plane programmable cursor, a 256 X 12 bit color 
map, support for a keyboard and a mouse, and a DMA interface. 


4.4.2 Bitmap Memory Organization 
Figure 4-2 shows each 2-dimensional plane of bitmap memory under 
control of a separate video chip. 


PLANE 4 | 


PLANE 3 | 


PLANE 2 


PLANE 1 | 


VIDEO PROC. 


VIDEO PROC. | 


ö 
i 
9 
. 

q 


VIDEO PROC. | 


—»{ video PROC. | 


MR 1 64968 


Figure 4-2 Multiplane Bitmap Memory Organization 


Programming Information 


‘coi sai aR SSN RN DPS yp a Rs GE aa aR Sugoi ay Hoa DR aii NiO 


A pixel is addressed by its Cartesian coordinates referenced to 
the upper left corner of the memory space. The X coordinate 
increases to the right; the Y coordinate increases downward. A bit 
within a plane of memory is addressed by its Cartesian coordinates 
and bitplane number. 


As Figure 4-3 shows, the bitmap is divided into the screen refresh 
area and off-screen memory (which can be used for font and image 
storage). Each plane consists of 1024 X 2048 pixels; of this, 
1024 XK 864 are visible on the screen. The remainder is available 
for fonts and other off-screen images. 


In addition to delineating the part of memory visible on the CRT, 
the screen refresh boundaries also mark that part of memory that 
can participate in scrolling. The actual scrolling boundaries are 
set in the address processor's scroll boundary registers. The 
hardware achieves the visual effect of scrolling by either moving 
data within the scroll boundaries, or in the case of 
down-scrolling, moving the data outside the scroll boundaries up 
and shifting the screen down with respect to the memory origin. 
In either case, the area outside the boundaries remains 
stationary, while the area within the boundaries scrolls. 


REFRESH 
AREA 


1024 * 864 


OFF-SCREEN MEMORY 


1024 X 1184 


MAT B496 


Figure 4-3 Off-Screen and Visible Memory 


4-4 


Programming Information 


4.1.3 Overview of Rasterops 

In the VCB0O2 video subsystem, all image processing in the bitmap 
is done by means of rasterops. A raster is a set of pixels within 
the bitmap that is enclosed by a parallelogram of any orientation. 
A raster operation (rasterop) transforms a rectangular source 
raster, aligned with the X- and Y-axis, into a destination raster. 
As shown in Figure 4-4, the transformation consists of both a 
geometric and a logical component. The geometric transformations 
consist of rotation, scaling, and translation. These are performed 
by the address processor chip. The logical component consists of 
masking, clipping, and combining logic, using pixels in the 
destination. These operations are performed by each video 
processor chip using codes placed in control registers by the 
MicroVAX CPU. 


SOURCE 
RASTER 


GEOMETRIC | ADDRESS PROCESSOR CHIP 
TRANSFORMS | 


(ROTATION, 
SCALING, 
ETC.) 


| COMMANDS 
| AND RASTER 
| PARAMETERS 


MicroVAX CPU 


| LOGICAL FFF 
TRANSFORMS dee PROCESSOR CONTROL 


| REGISTER INPUTS 
(MASKING, —————— 

CLIPPING, 

ETC.) | VIDEO PROCESSOR CHIP 


— DESTINATION 


Figure 4-4 Rasterop Functional Model 


4-5 


Programming Information 


F f e e e UB i ing iii Gi HC nivel 


In the general case shown in Figure 4-5, a rasterop is 
characterized by two source operands, a destination, a 
transformation between sources and destination, and a clipping 
rectangle applied to the destination raster. All operands are 
optional and all can be used in one of the following ways. 


& AS a source of pixels to be logically combined with the 
destination 


@ AS a mask applied to other operands 


As a Source of data to be broadcast on the I/D 
interconnect 


its simplest form, a rasterop copies a rectangular array of 
pixels from one location in the bitmap to another. For example, 
text may be displayed by selecting the appropriate raster from a 
set of rectangular font patterns in an off-screen portion of the 
bitmap and moving it to the location defined by the cursor 
position. In this case, the source is an array of pixels in the 


SECOND 
SOURCE 
OPERAND 


VCBO2 
=O 


(TRANSFORM AND CLIP IMAGE) 


i Uae ARID ADE el 


DESTINATION 
OPERAND f 


CLIPPING RECTANGLE 


RASTEROP OVERVIEW 


NMR) Gow 


Figure 4-5 Rasterop Operand Flow 


Programming Information 


/ NR A Aan Hae NANI ina 


font table, the destination is a rectangular area located at the 
cursor position, and the transformation is a replacement of the 
destination with a copy of pixels from the source. 


Other, more complex, transformations involve rotation, scaling, 
and some logical combination of source and destination pixels. 
The use of these additional features allows the rasterop facility 
to be used for vector generation and a large class of text and 
graphics operations. 


The clipping rectangle facilitates the implementation of 
viewports. It is a mask that overlays the destination, preventing 
pixels outside the boundaries from being overwritten. The results 
of the clipping algorithm are available to the MicroVAX CPU to aid 
in operations such as selecting an object or a menu item. 
Resolution of the clipping boundaries is up to 1 bit vertically 
and 4 bits horizontally. 


The performance of a raster operation depends largely on the 
orientation of the destination raster. With one edge aligned to 
the x direction, data is written into the destination in up to 
16-bit increments, resulting in a maximum rate of 8 million 
pixels/s. If neither edge is aligned with the X-axis, data must 
be written one pixel at a time. Thus, the overall rate decreases 
to 1/16 of the fast mode, or 0.5 million pixels/s. 


4.1.4 Overview of Scrolling 

In the VCBO2 video subsystem, horizontal and vertical scrolling is 
accomplished by high-speed logic within the address processor and 
video processor chips. The logic can move an entire 1024 X 905 
(screen height plus blanking time) scroll region upward or 
horizontally in a single frame time. The scrolling boundaries may 
be set on any vertical pixel boundary and on a horizontal 4-pixel 
boundary. Up-scrolling within a rectangular region simply 
involves using the scrolling hardware to move the contents of the 
region upward by the scroll increment. Conversely, since the 
scrolling logic does not shift the region downward, the hardware 
creates the appearance of down-scrolling by leaving the data 
inside the scrolling region stationary and shifting the 
surrounding data upward. The illusion of down-scrolling is 
produced by offsetting the start of screen refresh in the Y 
direction to compensate for the physical movement of the 
"stationary" data. 


One way to visualize down-scrolling is to consider a matte 
enclosed ina picture frame. If the matte is placed over a photo, 
it would outline some portion of the image. The image can be made 
to move downward with respect to the matte by either moving the 
photo downward or the matte upward. If the matte is moved, the 
appearance of the matte within the frame is held constant by 
shifting the matte and frame together. This is analogous to the 
way the VCB02 video subsystem performs down~scrolling,. Relocating 
the start of the screen corresponds to shifting the picture frame. 


Programming Information 


CC ee rn 


0 the image is to be moved, 
va ke „ the previous example, 
the 5 nd photo together vithin the 
nit Lling rate may vary from 1 to 
may vary from 1 to 905 
ch or jump scrolling may be 
© ¢ 


smoo 
Y dir 


Coordinate Systems and Mapping 
age in the VCB02 video subsystem can be referenced by their 
cartesian coordinates relative to: 


The origin of bitmap memory 


® The origin of the screen 


Any arbitrary point in the bitmap (usually a viewport or 
scrolling region) 


ions will want to specif: location of 
ative to the region origin. Visible objects 
be specified in screen coordinates. Objects 
will be located with respect to memory 
tes, “This 3 . ns how the adde SS processor chip 
— conversions between these frames of reference 
sence of scrolling. 


8 ee 


font 
cS 


Figure 4-6 shows the relati 

screen and memory coordinat 

the same extent. The physical bitmap appears as à large 
rectangular coordinate system that is subdivided into the screen 
refresh area and off- “screen memory. The mapping hardware makes it 
Seem as if the origin of the screen is always coincident with the 
bitmap. 


onship of these spaces. Logically, the 
2 . overlay one another and have 


ion of the screen 
n from the memory 
8 
ben 


— 
ox 
ue 
* 
= 
. 
e 


Because of vertical oslling, the actual posit 
j 0 
1 
r 


2 


ne „ Ne 1 i 
Sh area is displaced in the x directi 
as 5 in Figure 4-7. The extent of th 
en e 

ip. 

u 


area is defined 
its of X and Y.limit registers in the address 
The shaded e ndicates the visible portion of 
shaded part 1e off-screen area reserved for 
e is 55 performed by displacing the 
n relative to I tart. of physical memory. This 
lacement is containee the Y offset register in the 
ssor chip. 


5 


. 


8 


5 


— 
79 
05 
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9 


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Programming Information 


C NPD NURD SNARE SRNR SERDAR 


. t STAG ORRIN A HHA HST NH 


a 


t and Scrolling Regions 


"3 
Q 
— 
1 
oy 
< 
e 
© 
= 
S 
o 
1 
re 


nr — i 
Sadat OFFSET 


ORIGIN © 


e Ra EEN 


Figure 4~7 Screen-to-Memory Mapping 


Programming Information 


‘ean 


"SE Na EFS TS NGC EN a isin A go i aan 


During screen refresh, or when a rasterop address inside the 
11 


screen refresh mits is generated, the address is automatically 


mapped to physical memory by the following algorithm. 


ROUTINE SCREEN TO MEMORY TRANSFORM (X,Y; X _MEMORY,Y MEMORY) 


screen to memory coordinate transformation 


Xx and X are addresses generated by either the screen 
refresh or rasterop processes. 


X MEMORY and Y_ MEMORY are the physical memory coordinates 
. _MEMORY = Y 
X MEM ORV = X 
IF ((X is less than or equal to X L 
(Y is less than or equal to x LITT) 
Y¥_MEMORY (Y + Y_OFFSET) MODULO 


2 


RETURN 


Note the cylindrical screen- to- memory mapping that results from 
the use of modulo arithmetic. 


re 4-8 shows the relationship of the scrolling region to the 


gu 
reen coordinate system. 


Pic 
Scr 
The address processor chip locates the scrolling region with 
respect to the scree origin by the four X and Y 5 nates 


shown. The clipping region is specified to the scrolling region 
Similarly. 


To support viewports and windows, an object (raster) can have an 
address relative to an arbitrary reference point in the screen 
coordinate system. The address processor can conditionally apply 
the coo rc dinates of the reference point and the X and Y index 
value (shown in Figure 4~9) to translate a destination or first 
ress to screen coordinates. 

If the translated value is inside the refresh area, the Y offse 
is automatically applied to convert the address to 1 N 
coordinates. As EDR following algorithm shows, operand indexing 
é the index values are specified by the MicroVAX CPU. 


i 
= 
— 


4-10 


Programming Information 


es ed 


CCC 


Figure 4-8 Scrolling Region 


SCREEN ADDRESS 
SPACE 


ME 04 


Figure 4-9 Address Indexing 


4-11 


Programming Information 


ei ae LLAMAS DALAL aue HAAS mae inion ROROE 


ROUTINE REGION TO_MEMORY_ TRANSFORM (X, Y; X_MEMORY, Y MEMORY) 


X and Y are the . coordinates relative to the 
Start of the scrolling region. 

First assume that indexing is disabled 

_SCREEN = X 

SCREEN = Y 


IF (Indexing is enabled for this raster operand) THEN BEGIN 
SCREEN = X + X_INDEX 
SCREEN = I + Y INDEX 


5 
i 


1% W „ 


1 

1 IF She result is inside the screen refresh area, apply 
i the screen to memory coordinate transform shown 

i 5 
! 
8 


CREEN TO MEMORY TRANSFORM (X SCREEN, V SCREEN; X MEMORY,Y MEMORY) 
RETURN 

5 may be selectively enabled only for the source 1 and 
destination operands. 


Figure 4-10 summarizes address translation for the screen refresh 
5 destination, and source 1 raster operands. The output of 
the sterop computation is an address in screen, memory, or 
oa coordinates. The interpretation is specified, in part, by 
the MicroVAX CPU, which selectively enables indexing for either 
the first 1 or destination operands. Region coordinates 
cannot be used for the second source operand. The re sult, after 
indexing, ae be further mapped by the address processor, if it is 
inside the screen refresh area. 


When tiling is disabled, the origin of the destination raster 
defines the coordinate system for the second source operand. In 
this case, the MicroVAX CPU specifies the second source operand in 
terms of xX and Y¥ offsets from the destin ation, Figure 4-11 shows 
the computation of the second source physical memory address. 


4.1.5.1 V between Rasterops and Scrolling — The 
effects of concurrent scrolling and rasterops are twofold. First, 
the process of down-scrolling may alter the screen-to- memory 
mapping for data that appears Stationary on the screen. Second, 
memory references by the rasterop process may "collide" with the 
scrolling process. These interactions are explained below. 


FIRST SOURCE 
AND DESTINATION 

RASTEROP 

COMPUTATIONS 


REGION 
COORDINATES 


—— — 
| TRANSLATE TO SCREEN N 
»| COORDINATES . 


OPERAND 
INDEXING - 
ENABLE 


TO MEMORY 


Figure 4-10 Address 


| DESTINATION 
| RASTEROP 
| COMPUTATION | 


REGION 
COORDINATES 


| ADD SOURCE2 | 
| OFFSETS —— 


Figure 4—11 


inna ue ane hum men 


TRANSLATE SCREEN 


| COORDINATES . 


SCREEN 
REFRESH 
PROCESS 


1.— xoffskr 
VU 
X LIMIT 


| MEMORY COORDINATES 


Translation 


bq——-- SOURCE 2 X OFFSET 
SOURCE 2 Y OFFSET 


MEMORY COORDINATES 


MR OMG 


Programming Information 


Source 2 Address Computation (Tiling Disabled) 


Programming Information 


oop 


eee mme mmmh r ee 


Effect of Scrolling on Screen and Region Mapping 

The bitmap is divided into the screen refresh area, the scrolling 
region, viewport area, and off-screen memory. The address 
processor chip performs the following coordinate transformations. 


. Sscreen-to-memory mapping, using the Y offset to map 
visible objects to physical memory. 


2 Region-to-screen mapping, using the X and Y index values. 


If scrolling is ignored, the coordinate conversions can be 
performed by simply ; adding the appropriate constants. The effect 
of scrolling is threefold. First, scrolling or dragging a viewport 
effectively changes its location 58 respect to the screen 
origin; therefore, the index shige ist be adjusted accordingly. 
Second, down-scrolling requires adj 2 of the screen- to- memory 
offset. Third, vhen N and scro poem are performed 
concurrently, the use of a single J offset or set of indexes for 
coordinate mapping no longer works. 


To see why a 5 coordinate mappi 
all that sere involves the moveme 
sible data wi the time required to scan one complete frame, 
ring that ti the scrolling hardware makes a sweep of the 

tmap in the jard direction, accessing the data to be moved 
one scan line a time. At any instant, then, the screen is 
divided into two parts: the part above the current scan, 
consisting of data already moved; and the part below the scan, 
consisting of data not yet moved. Thus, during this time, two 
mappings exist between the screen and the bitmap: one for shifted 
data above the scan, and another for unshifted data. Therefore, 
without the features described below, “serambling" would occur due 
to pixels being placed incorrectly in the destination raster or 
Fetched incorrectly from the source. 


ng fails during scrolling, 
nt of some portion of the 


ae —.8 


x, 


The hardware eliminates this scrambling effect by providing an 
extra set of F offset and index registers. These extra registers 
contain the new mappi ng for shifted data. They are automatically 
referenced by the address processor chip when an address is 
generated in the scrolled part of the screen refresh area. The old 
mapping is automatically used for the unscrolled portion. 


The task of updating these registers is left to the MicroVAX CPU. 
To allow a full frame time for this operation, a third set of 
index and offset registers is provided to hold a set of pending 
values. The index values are in the order X coordinate, Y 
coordinate. At the completion of a frame, the address processor 
chip automatically advances the register values. Since all data 
has been scrolled, the "new" values now represent the mapping for 
unscrolled data, and are therefore copied to the "old" registers. 
The pending values become the new values 5 scrolled data. The 
MicroVAX CPU has a full frame time to compute and set up a new set 
of pending values for the next N The 0 of data for this 
pipeline is shown in Figure 4-1 


is 
is 


1 
X 
2. 


a i DARN AG 


Programming Information 


An eSNG NNR NONI 


INDEXES AT START OF SCROLL EROM MicroVAX CPU 


10,38 FRAME WN 


OLD INDEX NEW INDEX PENDING INDEX 


INDEXES DURING SCROLLING FROM MicroVAX CPU 


| FRAME N +1 


OLD INDEX NEW INDEX PENDING INDEX 


INDEXES DURING SCROLLING FROM MicroVAX CPU 


10, 36 | FRAME N + 2 


OLD INDEX NEW INDEX PENDING INDEX 


INDEXES AT SCROLL COMPLETION 


| FRAME N +3 


PENDING INDEX 


MA BGS 


Figure 4-12 Index Registers for 2-Pixel Down-Scrolling 


Note that at the completion of scrolling, the pending index value 
is simply allowed to propagate to the "old" and "new" register 
sets. The index represents the screen coordinates of the upper 
left corner of a region. Scrolling or dragging a _ viewport 
effectively changes its location with respect to the screen 
origin; therefore, the index values must be adjusted accordingly. 
Conversely, if the viewport is not being scrolled, the index 
values are unchanged. 


Programming Information 


iio 


Collisions between Rasterops and Scrolling 

A collision occurs whenever a rasterop and the scroll process try 
to read or write the same memory locations in the bitmap. The 
hardware resolves collisions by suspending the rasterop until the 
scrolling process has moved on. Since scrolling accesses memory 
from the top of the screen to the bottom, the worst case for 
collisions occurs when the processing of one or more raster 
operands scans the screen refresh area in the downward direction. 
In this case, rasterop memory references, trailing behind the 
scroll process, repeatedly collide with scroll memory accesses. A 
way to limit such collisions is to specify the raster operand so 
that it is scanned in the upward direction. In this way, only one 
collision per frame can occur during a rasterop. 


1.6 Additional Operations on Bitmap Data 
addition to conventional raster operations and scrolling, the 


@ Polygon fill, to fill the area between two vectors with 
any source of pixels, such as a solid color, tile pattern, 
or image. 


Transferring data between the MicroVAX CPU and one plane 
in the bitmap, to load a font or save and restore an 


occluded viewport. 


5 A set of Z-axis operations, for transferring one pi 
value between the MicroVAX CPU and the bitmap in a si: 
operation. This function is used to facilitate pixel 
operations that are not supported by the hardware, such as 
flooding or painting within the boundaries of a region 
having an arbitrary shape. In this case, the vVCB02 
hardware maps a pixel vector into a single 16-bit word to 
be read or written into the MicroVAX's address space. The 
VCBO2 can map two pixel vectors into one 16-bit word when 
doing DMA. 


The operations above are all implemented as variations on the 
basic rasterop function. 


4.2 VIDEO PROCESSOR AND ADDRESS PROCESSOR CHIP ARCHITECTURE 
The VCBO02 video subsystem architecture divides all display 
operations into two orthogonal functions: the generation of 
addresses for bitmap data, and logical operations on the data. 
Address generation is performed by the address processor chip. 
Logical operations on the data are performed by the video 
processor chip. 


4~16 


Programming Information 


ipsa ama ahi a denn ii inen 1 1 


The functional relationship between the address processor and 
video processor chips is shown in Figure 4-13. The address 
processor chip broadcasts memory addresses to the bitmap commands 
and data to each video processor chip on the I/D interconnect. 
Each video processor chip, running in lockstep, processes the 
bitmap data as directed by instructions on the I/D interconnect, 
control signals, and instructions in its control registers. 


The I/D interconnect protocol allows any device to become bus 
master. Therefore, during raster operations, the video processor 
chips can serve as sources or destinations for operands. This is 
useful for broadcasting common data, such as character fonts, to 
all the bit planes. Of course, only one video processor chip can 
Serve as the source of data at any one time, while any number of 
chips can receive data. 


10 Q22-BUS 
N DATA 


ADDRESS 
PROCESSOR 


| 1/D INTERCONNECT 


MEMORY ADDRESS COMMANDS AND DATA 


VIDEO 
— PROCESSOR 


MEMORY 
DATA 


VIDEO 

E PROCESSOR 
MEMORY 
DATA 


: TO OTHER PLANES 


MPT DOOG 


Figure 4-13 Address Processor and Video Processor Chips, 
Functional Diagram 


4-17 


Programming Information 


vue e iii aii aati tii ini iin iii 


4.2.1 Address Processor Chip Architecture 
The address processor chip logically supports three separate and 
concurrent processes: 


» CRT screen refresh 
Scrolling 


2 » 


Figure 4-14 shows the relationships of these processes. 


Each process, running concurrently, generates a bitmap address and 
an I/D interconnect command. The arbitrator resolves contention 
for access to shared resources, such as the I/D interconnect and 
bitmap, based on the following requirements. 


® screen refresh cannot be interrupted. 
Scrolling must not be visually disturbed. 


5 Race conditions must be eliminated between the scroll and 
rasterop processes. 


Both screen refresh and scrolling share memory access on a 
"round-robin" basis, with the remaining time allocated for 
rasterops. During simultaneous raster operations and scrolling, 
the arbitrator blocks the rasterop process when its memory 
accesses conflict with those of the scrolling process. 


ee eS ee, SS LS. Sl ee 
ADDRESSES AND 
COMMANDS 


| 


BITMAP MEMORY 


REFRESH 
PROCESS 


_ VIDEO PROCESSOR 
CHIP COMMANDS 


SCROLLING 
PROCESS 


an , ee 


MERA GEO? 


Figure 4-14 Address Processor Chip Data Flow 


4-18 


Programming Information 


4.2.2 Address Processor Chip Interface to the Q22-Bus 

The address processor chip is the gateway to the video processor 
chip, bitmap, and chip select registers. As such, it provides 
access to this hardware through a set of register-level interfaces 
for commands and the interchange of data and status via the 
Q22-Bus. The register format and addressing is also designed to be 
an efficient interface to the DMA gate array. 


4.2.3 Video Processor Chip Architecture 

The function of the video processor chip is to process data 
appearing at its input pins as directed by instructions in its 
control registers, commands on the I/D interconnect, and 
hard-wired signals from the address processor chip. Logically, the 
video processor chip has two data paths: one for rasterops, the 
other for scrolling and screen refresh. 


4.2.3.1 Data Flow for Scrolling and Screen Refresh —— Figure 4-15 
shows data flow through the video processor chip for scrolling and 
refresh. 


The video processor chip reads 128 bits from the bitmap quickly, 
storing the 128 bits in its internal FIFO. This allows the video 
processor to output the data on its video bus at a slower rate, 
while the memory bus is being used for updates and scrolling, 
until another 128 bits is required. 


INPUT FROM BITMAP 


VIDEO 
PROCESSOR 


OUTPUT TO VIDEO SHIFT REGISTER 


MAF-18508 


Figure 4-15 Video Processor Data Flow 
(Screen Refresh/Scrolling) 


4~19 


Programming Information 


COTA eh menge dum is une pu mee endend 


4.2.3.2 Rasterop Data Flow - Figure 4-16 shows the data flow for 
a rasterop. Operands are read and processed as directed by 
internal control registers by the following functional units. 


. Operand fetch logic 
a Combinatorial logic 
0 Masking and clipping logic 


Each rasterop cycle consists of the following events. 
1. The first and second source operands are read in sequence 


and routed to the appropriate functional unit, as directed 
by the control store RAM. 


Bo 


. The destination 18 read and processed, also; it 
automatically becomes the second operand to the logic 
unit. 


3. The logic function specified by the video processor 
control registers is performed. 


4. The output of the logic unit is masked, clipped, and 
written into the destination. 


Steps cae ay and 4 are actually executed in à single 
read-modify-write memory cycle. 


OPERAND DATA (FROM BITMAP OR I/D INTERCONNECT) 


CC 
LC 


OGIC 


OMBINATORIAL | 


MASKING AND 
CLIPPING 


BITMAP 
MEMORY 


MRI G5O9 


Figure 4~16 Rasterop Data Flow 


Programming Information 


me 1 1 1 7 isi i ie iia ei ele 


Video Processor Chip Operand Fetch 

The operand fetch logic routes the operand to the appropriate 
functional logic within the video processor chip, and optionally, 
to broadcast data on the I/D interconnect. 


Figure 4-17 shows how operands are processed. An operand fetch 
cycle is actually divided into two microcycles. During the first, 
internal input data from the bitmap is processed. During the 
second, external data from the I/D interconnect is read, and 
optionally, a copy of the internal operand can be gated onto the 
interconnect. 


BITMAP DATA 


SHIFT BARREL 
CONSTANT Saree 


(FROM AbORESS8 semanas 


| 


FROM i/D INTERCONNECT 
OCR REGISTERS DATA 


i/D 
INTERCONNECT 
OUT 


“INTERNAL” CYCLE “EXTERNAL” CYCLE 


Q | 


ROUTING * FROM OCR 


BIT MASKS LOGIC 
BUCKET UNIT MF. 800 


Figure 4-17 Operand Routing Functions 


Programming Information 


In Figure 4-17, the ganged Switches indicate the data paths for 
each microcycle. The switch state shown is for the internal cycle 


During this time, data from the bitmap is read, rotated into 
alignment with the destination raster, and directed to a 
| al unit 


During the external cycle, data from the I/D interconnect is also 
read and passed, without rotation, to the destination. 
Concurrently, a copy of the aligned internal operand can be output 
to the I/D interconnect. When this occurs, the output becomes the 
external operand for all video processor chips, including the chip 
Sourcing the data. 


The control store RAM specifies: 


The destination of the internal operand 


ion of the external operand 


Whether or not a copy of the internal operand will be 
placed on the I/D interconnect. 


n Figure 4.18. The foreground, 


The logic unit is shown i 

background, and source registers are loaded by the MicroVAX CPU. 
The source register can also be loaded with bitmap data by the 
video processor. The logic unit combines data from the bitmap with 
data from the source register in a way determined by the logic 


function registers. The output of the logic unit is used to agrees 
either a foreground or background value. An output of 1 caus the 
selection of a foreground value (color), an output of 0 eases the 
Selection of a background value (color). The selected for reground 
or background value is further manipulated by the clipping and 
masking logic. 

Masking and Clipping Logic 

The masking and clipping section of the chip is shown in Figure 
419. 


The mask registers can be set up with operands during each fetch 
microcycle by programming the appropriate operand destinations 
into the control store RAM. In most cases, both mask registers 
will require the same value; therefore, sending an operand to mask 
1 V causes a copy to be written into mask 2. To set 
different mask values, the control store RAM is programmed to 
write mask l, followed by mask 2. Each mask is also controlled by 
a register that allows the mask register, or its complement, to be 
used to form the mask value. 


A mask value of 0 in a given bit position specifies that the 
corresponding bitmap location is to be unmodified. A 1 indicates 
that the location is to be replaced with the output of the logic 
unit. 


| LOGIC FUNCTION L 
| REGISTERS | 


| RecisteR 9 [ 


oA FHNW | 
BITMAP ai 
(DESTINATION) 


Figure 4-18 


FROM 
COMBINATORIAL 
LOGIC 


OPERAND 


i 


MASK 4 


RASTEROP 
OPERAND ~~ 


EDGE MASK ; 
FROM ADDRESS 
PROCESSOR 


BITMAP 


Figure 4-19 


CLIPPING MASK 


OUTPUT TO 


Programming Information 


| BACKGROUND | 


|FOREGROUND| | 
| ReGisTER =| 


|REGISTER =| 


FOREGROUND/BACKGROUND | 
SELECT 


TO CLIPPING AND MASKING LOGIC 


0 . t 


Logic Unit 


FROM 
BITMAP 


L FROM CONTROL 
STORE RAM 


FROM CONTROL 
STORE RAM 


MENG 2 


Masking and Clipping 


Programming Information 


icin 


RS ESE SHG SASS ES I AL i i I NS ll ai ed il innit i ll vienna ii iin oN 


Video Processor Chie Control Registers 

The video processor chip contains two sets of registers that can 
be programmed by the MicroVAX CPU to control the execution of 
raster operations: 


* Control store RAM (CSRs) that specify how operands will be 
transferred 


ic and mask control registers that determine iat 
1etion of he logic unit and the polarity of the mask 
i 


iC Logic 
8 t 
egister output. 


Control Store RAM Functions 

The operand fetch logic is controlled by a set of six control 
Store RAMs divided into two banks of three locations. Within each 
bank, one location controls each operand. Every time a rasterop is 
he MicroVAX system must specify the bank of control 


performed, t 

Store RAM to be used. In this way, the software can 5 two 
individual banks, which permits operations n two rasterop 
Steps without need of reloading RAM locations 


The following is a brief description of the control fields. 


2 Internal cycle destination -- Specifie one of the 
following destinations for the internal e 


— The bit bucket 

— The source register 

— 80 mask 1 and mask 2 
9 ask 2 only. 


ee 


External cycle destination — Specifies one 
following destinations for the external operand: 


the 


2 


The bit bucket 
— The source register 
Both mask 1 and mask 2 
8 Mask 2 only. 


I/D interconnect output control — If set, places a copy 
of the aligned internal operand on the I/D interconnect 
during the external operand microcycle. 


Note that every operand fetch cycle involves the execution of an 
internal and an external microcycle. Therefore, for all CSRs 
referenced by an operation, the disposition of data during both 
microcycles must be specified explicitly. If the data from either 
cycle is unwanted, the appropriate destination field to place the 
result in the bit bucket must be set. 


Programming Information 


r f NUR NOTA NSN 


Logic Unit Function Registers 

The logic function control registers determine the operation 
performed by the logic unit and the polarity of the mask register 
output applied to the result. Four registers are available, and 
can be preset by the MicroVAX CPU, but only one is used for a 
given operation. The register number is a parameter of the 
rasterop command, 


The logic unit operates on the output of the background/foreground 
select register and the contents of the destination raster. The 
masks applied to the output determine which pixels in the 
destination raster will be modified. 


The logic function control registers have the following fields. 


0 Logic unit function — One of the following functions can 
be programmed. 


= Output = Zeros 

— Output = NOT (Destination OR SOURCE) 

os Output = NOT (Destination) AND SOURCE 

— Output = NOT (Destination) 

— Output = Destination AND NOT (SOURCE) 
— Output = NOT (SOURCE) 
— Output = Destination XOR SOURCE 
— Output = NOT (Destination AND SOURCE) 
Output = Destination AND SOURCE 
— Output = NOT (Destination XOR SOURCE) 
= Output = SOURCE 
— Output = NOT (Destination) OR SOURCE 
— Output = Destination 
— Output = Destination OR NOT SOURCE 
— Output = Destination OR SOURCE 
* Output = Ones 

. Mask regist . 

t 


1 control —— If set, use the complement of 
mask regist 1 


ie 


0 Mask register 2 control —— If set, use the complement of 
mask register 2. 


4 Source register control — If clear, use the complement of 
the source register. 


® Resolution mode logic for source register control — Tf 
clear, enables resolution mode logic for the source 
register. 


Programming Information 


iat 


CN 


sii SE DS i i Pala ee iii iia li it alii oii iO REDON ANNONA 


4.2.4 I/D Interconnect Protocol 

The I/D interconnect is a multidrop interconnect that can be used 
by the address processor chip and any video processor chip to send 
and receive data. Update and scroll ship select registers are 
connected to the interconnect, and specific address processor 
commands are available for sending data to them. 


The role of the address processor in an I/D interconnect 


transaction is implicitly determined by the function being 
performed. During a processor-to-bitmap transfer, for instance, 
the address processor chip transmits data from the I/D 


interconnect to one or more video processor chips. During a 
cee ea processor transfer, it acts as a receiver. Otherwise, 
unless specified explicitly, the address processor chip neither 
sends, or receives data. 


The role of each video processor chip is determined by the 
contents of its control store RAM and logic function registers. 
During a processor~-to-bitmap transfer, for example, at least one 


video processor chip must be programmed to receive external data 
during the appropriate operand cycle. During a full-plane 
itmap-to-processor transfer, only one video processor chip will 


1 

e programmed to source data on the I/D interconnect. During a 

Z-axis transfer, when part or all of a pixel is being sent to the 

MicroVAX CPU, each video processor chip will be programmed to 

"source" its portion of the pixel value at the appropriate bit 

position on the interconnect. This is the only case where multiple 

Sources are allowed (with the restriction that no two video 

processor chips attempt to drive the same bit position 

Simultaneously). Broadcasting data from one video processor chip 

to others during a rasterop requires the following actions. 

1. The processor selects a memory plane and its associated 
video processor chip to serve as the source of data for 
broadcast to other video processor chips during a raster 
operation. 


ho 


The appropriate 5 ike defined, enclosing the data 
to be broadcast CELY Source, second source, or 
destination). 


3. For the oe broadcasting the data, the CSRs associated 
with the selected operands are programmed to place a copy 
of the data on the interconnect during the external 

microcycle. 


4. For each chip receiving the data, the CSRs associated with 


the selected operands are programmed to receive data 
during the external microcycle. 


_Programming Information 


e t ß eee wehte 


For a given raster operation, the configuration of receivers and 
transmitter can be different for each operand. For example, in a 
system with four planes, numbered 0 through 3, the configuration 
for each operand cycle might be as follows. 


sinensis iit ibis Rai io EN avi i ali ola Nin A rN lai EN Ga RO PGRN HE MARPAC RAP HERDER HEIRED HESS RESINS TIERS AID ONT, 


Cycle Transmitter Receiver 


„ ˙³ r c ONSEN EO SRO IORN ANAESTH CALOSO NRSC SACERHRET SENSES HOARSE RNAI 


Source l Video processor chip 0 Video processor chips J, 2 
Source 2 Video processor chip 2 Video proces Ssor chip 0 


— . p ff d LN ONEONTA ON ASAT ANNES ORSON SATE HII aachen eb ele d eiae nene, 


NOTE 
The hardware does not prevent multiple 
writers on the I/D interconnect. 


The programmer must ensure that multiple writers do not attempt to 
place data on the I/D interconnect "at the same time"; that is, 
during the same operand cycle. If this occurs, the contents of the 
interconnect will be garbled, and electrical failure of the 
input/output circuits is possible. 


4.2.5 Rasterop Process 
This section discusses the algorithms the address processor chip 
uses to generate operand addresses. 


4.2.5.1 Raster Scanning Algorithm — Figure 4-20 shows a raster 
defined by an origin and two vectors that enclose an area 
containing the pixels to be processed. 


The algorithm for generating pixel addresses within the raster 
involves moving one vector along a path traced out by the other 
vector. The vector defining the path is called the "slow" vector; 
it is traversed only once per scan. The other edge vector, called 
the “fast" vector, is traversed at each point along the path 
traced out by the slow vector. Points along each vector are 
computed using Bresenham's algorithm. 


DIRECTION) 
FAST VECTOR 


MTG TO 


Figure 4-20 Raster Scanning 


— 
43 7 
5 Bae 


Programming Information 


ior ia sia i eA ern EIN, 


RHO 


To allow an image to be created with multiple raster operations, 
the vector computation excludes the last point. This feature is 
intended to support "complement mode" writing, in which an image 
is erased by writing its complement back into the bitmap. For this 
to work, all pixels in an image must be written an odd number of 
times. If vector generation included the last point, the first 
point of the adjoining raster would trace over the boundary a 
second time, leaving a residue of unerased pixels. 


For an ideal scanning algorithm, each pixel in the raster would be 
addressed only once during a raster operation, regardless of the 


orientation of the edge vectors. In fact, under certain 
conditions, one of the following will occur. 


1. A pixel within the raster boundaries will be addressed 
more than once during a rasterop. 


2. A pixel within the raster boundaries will not be addressed 
at all during a rasterop. 


These conditions never happen when a vector is parallel to the X- 
or Y-axis, or at right angles to the other edge vector. 


Failure to address a pixel will leave holes in the resulting 
image. The appearance of the image can be partially corrected by a 
hardware feature that, optionally, fills such holes. Hole fill is 
particularly useful when text is written into the bitmap by 
rotating and transforming a rectangular font. 


Addressing a pixel more than once can affect the process of 
erasing an image by writing its complement into the bitmap. In 
such cases, it is advisable to first create the image off screen, 
then manipulate it with a rectangular rasterop. 


Other kinds of distortion arise when a rectangular raster is 
scaled, rotated, or transformed into a parallelogram with angles 
other than 90 degrees. In these cases, information may be lost 
because the number of pixels in the destination raster is not the 
same as in the source. 


4.2.5.2 Specification of Operands for a Rasterop -- A rasterop 
may have the following operands. 


6 A destination raster, with fast and slow vectors of any 
size and orientation. 


5 A primary source raster, called source 1, that can be used 
EOr Spatial transformations on a rectangular’ raster 
(rotation, scaling, etc.) and linear pattern generation. 
The fast vector is always parallel to the Y-axis. 


® A secondary source raster, called source 2, that can be 


used to copy a raster of any shape or orientation, or 
generate a tile pattern. 


4-28 


Programming Information 


SAAR RTA IND 


All operands are optional. The address processor chip allows the 
generation of a specific operand raster to be suppressed, when it 
is not required for a given function. In this case, the contents 
of the associated control store RAM locations in the video 
processor chip are not referenced, and therefore, need not be set 
up by the MicroVAX CPU. 


Destination Operand | 
The destination operand is specified by the following parameters. 


@ The coordinates of the origin. 


* The coordinate system used (either screen or region 
coordinates). 


* The slope and extent (DX and DY) of the slow vector. 
* The slope and extent (DX and DY) of the fast vector. 


Region coordinates may be used when a raster is within a region or 
viewport. In this case, before executing the rasterop, the 
MicroVAX CPU must set up the address processor chip index 
registers with the values required to translate the region 
coordinates to screen coordinates. 


First Source Operand 
The first source operand is a rectangle with edges parallel to the 
X and Y-axis. The fast vector is in the Y direction. The raster 
is defined by the following parameters. 

* The location of the origin. 

. The direction of the fast and slow vectors (+ or-). 


& The coordinate system used (either region or screen 
coordinates). 


e A scale factor relating the length of fast source to fast 
destination vectors. 


© A scale factor relating the length of slow source to Slow 
destination vectors. 


* When linear patterns are generated, the length of the 
pattern is in the X and 1 directions. 


4-29 


Programming Information 


ee ee iii anni Dg lee 


Mapping and Scaling the Source 1 Operand 

During each rasterop cycle, the address processor chip generates 
an address in the source 1 raster, followed by an address for the 
destination. Within that cycle, the v 8 Processor chip combines 
the pixels at the source rian destination as directed by its 
control registers The path traced ee the source and destination 
address pairs over time aoe ee the source-to-destination 
mapping. Figure 4-21, with pixels scaled in 5 by a factor 
of a thousand or So, Shows this relationship for the Simple case 
of two rect b rasters having a width of one pixel and a scale 
Factor of one. The letters indicate pixels being copied from the 
Source to the destination. 


1 
1 


The numbers indicate the time sequence in which each pair of 
Source and destination addresses is computed. At a scale factor of 
Ly a new source address is generated in step with each new 
de ation address. 


ng between the first source and a 


Figure 4-22 shows the mappi 
J | | 
gle with respect to the X-axis, 


destination vector at some an 


Observe —— rotation has introd 
of the destination vector. Thi 
corrected 55 introducing a sc 
destination. 


2 


uced an aberration in the length 
s distortion can be be partially; 
cale factor between the source and 


that at a scale factor of 


To clari med the scaling process, recall t 
source is sampled for each new 


1, precisely 1 new point in the 
point in the des tinat ion. That is, the source and destination 
addresses both have the same rate of change. A change in scaling 
is produced by increasing or decreasi ing the rate of change between 
the source and destination addresses. 


TIME SOURCE 1 DESTINATION TIME 


1 1 
2 2 
3 3 
4 44 


e 


4-30 


eis autem inns 


Programming Information 


aan RN REN RL 


Figure 4-23 shows the variation of source and destination 
addresses with time when the source is scaled up by a factor of 2. 
The numbers indicate the time sequence of each sample. A new 
source sample is taken on every other destination sample, 


ons 


effectively stretching each source pixel by the scale factor. 


TIME SOURCE 1 DESTINATION TIME 


epee: 


TIME SOURCE DESTINATION TIME 


MRT GET G 


Figure 4-23 Source Scaled Up by a Factor of Two 


Programming Information 


R OREN UGHO HN NUMAN ROTOR IW ORRIN SEE TA NMR ARIA OIE RIOTS NS NSIT RUE HAHEI OUTTA aa i Ui i i ARUN HRN 


Figure 4-24 shows what happens when the source is scaled down by a 
factor of 2. At time 1, the address of the source points to pixel 
"A". It is copied to the destination as shown. At time 2, the 
source address is incremented to pixel "B". The destination 
address is unchanged. The copy function overwrites the destination 
with "B'". Because the destination address changes at half the 
rate of the source, two source pixels are compressed into one 
destination pixel as shown. 


Tne 


WP LOST? 


Figure 4-24 source Scaled Down by a Factor of Two 


Programming Information 


e t VrWWTWhyW1 INRA 


A side-effect of down-scaling is that "complement" writing will 
not properly erase an image, since a point in the destination is 
addressed more than once. This problem can be solved by 
manipulating the image in a staging area, then using a rectangular 
rasterop to update the screen refresh area. As the previous 
figures illustrated, regardless of the scale factor, the extent of 
a rasterop is governed by the dimensions of the destination 
raster. That is, the rasterop process completes when one pass over 
the destination raster is made. 


Linear Pattern Generation 

This section discusses how the linear pattern mode in the address 
processor chip can be used to generate a pattern aligned with the 
destination raster boundaries. The source 1 raster is a rectangle 
whose extent is usually proportional to the size of the 
destination fast and slow vectors. In this case, a rasterop simply 
transforms the source into a scaled and rotated copy in the 
destination. In linear pattern mode, the source 1 raster contains 
a pattern that is scaled and replicated within the destination 
raster limits. The parameters of the pattern are the coordinates 
of the source 1 origin and the source 1 extent in the K and 1 
directions. The process for generating a pattern is shown in 
Figure 4-25. 


Basically, linear pattern generation is produced by a simple 
modification of the source 1 raster algorithm, which resets a 
source edge vector when the appropriate pattern limit is reached. 
All other aspects of source 1 operand address computation are 
unchanged. Therefore, the pattern can be scaled by applying the 
scale factors. 


The pattern repeat cycle is determined by the extent of the source 
DX and DY vectors and the scale factor. In Figure 4-25, a scale 
factor of 1 is used. 


SOURCE 1 DESTINATION 


FAST SOURCE SLOW DESTINATION 
SLOW —> ee ae 
SOURCE DX = 5 DX = 3, DY =0 
DY = 2 


+ A + DESTINATION 
O 8 O DX = 10, DVS 


a 
ee 


Figure 4-25 Linear Pattern 


4-33 


Programming Information 


During a fast scan, source addresses are incremented in the X 
direction at a rate determined by the scale factor. When the Dx 
limit is reached, the source address is reset to the beginning, 
and the source fast vector is scanned again to create the pattern 
effect along the destination fast vector. 


Similarly, during a slow scan step, the slow source vector is 
incremented until the DY limit is reached. At that time, the slow 
vector is reset and the pattern is scanned again from the origin. 


Second Source Operand 
The second source operand can be used in one of the following 
ways aie 


6 To generate a tile pattern from a rectangular raster. 


i To e 
1 


py pixels from a source raster having the same shape 
as the de 


% 
e destination. 

When used to generate tile patterns, this operand is defined by 
the following parameters. 


© The origin of the pattern in memory coordinates 
* The length and width of the pattern 


When used to copy a raster, the source origin is specified by an 
offset relative to the unindexed coordinates of the destination. 
The fast and slow source vectors have the same length and 
orientation as the destination vectors, and there is no scaling 
between source and destination. 


> 2 to destination pixels 
1 


Figure 4-26 shows the mapping of source 
h of 


for a destination raster having a width o 


sen 


During each rasterop address cycle, the hardware computes the 
5 dexed 


a 
ly 


source 2 operand address by applying the offset to the unin 
destination address. 


X OFFSET 


* 


ee ee 


Figure 4-26 Mapping of Source 2 to Destination 


Programming Information 


ß ii Mii iO NITRIDE AIR 


Tiling 

Unlike a linear pattern, a tile is always aligned with the X- and 
Y~axis. The tiling logic generates a textured surface that has an 
origin coinciding with the coordinate system of the screen. In 
this way, the tiling of overlapping images is always in 
registration. Tiling an image is equivalent to uncovering the 
surface, revealing the tiled pattern underneath. 


The tile’ dimensions are independent of each other and are 
restricted to powers of two, ranging from 272 to 2°9. The tile 
width may never be less than the memory bus width, but smaller 
tile elements can be defined by repeating the tile elements within 
the cell. For.proper alignment of adjoining tiles, the dimensions 
of the embedded pattern must be multiples of two. 


The key to tile pattern generation is the use of modulo arithmetic 
in the tile address computation. The tile pattern is generated as 
Follows. 


1. The destination address is computed using the raster scan 
algorithm. 


2. The destination address is reduced to a modulus of the 
tile size. 


3. The result of step 2 is added to the source 2 origin. 
Note that tiling is disabled by simply omitting step 2. 


4.2.5.3 Model of Raster Operations —— The model shown in Figure 
4-27 summarizes the rasterop capabilities described in previous 
sections. 


The operands in Figure 4-27 are defined as follows. 


Operand A: Operand B 
Source 1 raster or linear pattern 
Source 2 raster or tile 
Destination raster 
Constant 
I/D interconnect data 


Operand B, Operand C : Source 1 raster or linear pattern 
Source 2 raster or tile 
Destination raster 
Constant 
I/D interconnect data 


The functional units consist of: 


* The map function, which includes the logic register and 
foreground/background selection 


® Mask logic functions that can form the mask from the 
operand or its complement. 


ici oiiininiiiinisiiiiiaii  ii en iia ication mee o nme 


Programming Information 


OPERAND A 


MA-PGG8O 


fied Rasterop Model 


Se 


Figure 4-27 Simpli 


4.2.6 Polygon Fill 
The polygon fill feature uses the rasterop logic to generate a 
8 1 of addresses that cover the space between two edge 
ecto The enclosed space can be filled with a solid color, tile 
5 or image. A fill operation is defined by the two edge 
vectors and a fill vector that is parallel to the X- or Y-axis. 
The first edge vector, called the A vector, is defined by the 
parameters normally used to specify the origin and slope of the 
Slow destination vector. The second edge vector, called the B 
vector, is specified by the source 1 origin, DX and DY parameters. 
The £111 vectors connect points on the A vector to corresponding B 
vector points as shown in Figure 4-28. To permit joining of fill 
areas, the fill stops one point shy of the endpoint. 


3 


4-36 


Programming Information 


c AA NSO HAN 


FILL DIRECT N 


l e e e e e e e e e we ee FH 3 
A „ „ & & eee ee „ „ eee VECTOR 
VECTOR . „ „ & „ „ „ „ b „ & b d % „ „ „ b b K 


„ „ & & 6 „ „ „ „ 6 % „ „ 6 „ „ % O . 
. e OO e e e e ee we . e 


* . he 


END 


MRTG? 


Figure 4~28 Polygon Fill 


At completion, the address processor chip retains the final source 
and destination addresses. These can be used as the origins for a 
subsequent fill operation. In this case, only the new slopes would 
have to be specified. 


The fill operation is defined by the following parameters. 


8 The fill direction, which is parallel to either the X- or 
Y-axis. When there is a choice, the X-axis should be 
selected for performance reasons. 


® The A edge vector, specified using the destination slow 
vector origin, DX and DY. 


8 The B edge vector, specified using the source 1 origin, Dx 
and DY. The source origin need not be coincident with the 
destination. However, it must be possible to connect the 
source and destination origins with the first fill vector. 
Also, the edge vectors may intersect. When this occurs, 
filling continues, but the direction of the fill vector is 
reversed. 


The destination pixels are within the trapezoid enclosed by the A 
and B vectors. The source pixels are determined by the second 
source operand specified. 


A special case of the fill operation allows a polygon to be filled 
from a baseline that is parallel to the X- or Y- axis. In this 
instance, only the X or Y component of the source 1 vector must be 
specified, depending on the fill baseline. 


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Source 1 operand Disak 
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Source 2 operand: 


45 


Can be disabled, 
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4.2.6.1 Polygon Fill | odel 
oe mode] shown in ur 


rions described N The 
follows. 


summarizes the polygon fill 
I 


erands in Figure 4-29 are define 


eee 


enen; 


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a NET 


MR. 


Programming Information 


MCT MMO A MMMM imi MMT mmm IAM MTNA NAMM MMM ANIA nin ite 


eee 


Operand A: Operand B 
Source 2 raster or tile 
Destination trapezoid 
Constant 
I/D interconnect dat 


Operand B, Operand C: Source 2 raster or tile 
Destination trapezoid 
Constant 
I/D interconnect data 


4.2.6.2 Side Effects of the Fill Algorithm -- When filling a 
polygon, the program must account for the following side effects. 


1. Filling does not include the last point on the edge 
vector. Therefore, the firmware must account for any 
unfilled vertices that result. 


2. When regions are abutted or the edge vectors intersect, 
interior points may be addressed twice with the usual 
adverse effect on complement writing. 


To understand the problem with adjoining areas, a closer look at 
the algorithm is required. In minimizing the occurrence of 
doubling, the fill algorithm attempts to draw only one fill vector 
between edge vectors at a given X or Y coordinate. Figure 4-30 
shows successive points along the unfilled edge vectors. Because 
of the finite resolution, any vector~approximation algorithm will 
occasionally generate two points in succession that have the same 
X or Y coordinate. To ensure that only one fill vector is drawn 
between edges, the address processor chip connects only the 
outermost points along the fill direction. 


A VECTOR B VECTOR 
f N 
2 2 
3 3 
456 456 
789 789 


Figure 4-30 Edge Vectors Before Fill 


4~39 


Programming Information 


eehte 


Figure 4-31 replicates Figure 4-30, but with the fill vectors 
drawn in. The X marks the last point on each edge vector. 


If the fill is continued from the end points shown in cha 4-31, 
the next fill vector will be coincident with the last vec chor 
drawn. This is shown in Figure 4-32. The “doubled" points are 
marked with an asterisk. 


Since only the outermost points are connected, doubling will not 
occur when the edge vectors are outboun d. This is shown in the 
Figures 4-33 and 4-34, which illustrate successive fill operations 


. 
with diverging edge vectors. 
In Figure 4-33, point 6 is the A vector end point. The fill 
operation terminates one point before this, at point his 
is not the outermost point along the fill axis, no 
drawn. Continuing the f as shown in Fi 
in doubling. 


i 
53 1 
111 vector 18 
= 1 


P pitts 
n F 
1 gure 4-34 does not resul 


ol 
il 


In general, joining two fill areas results in doubling any time at 
least one of the previous edge vectors approaches the opposite 
vector with a slope of less than 1:2 (with the longer component in 
the fill direction). One way to compensate for doubling in 
complement mode is to write the doubled pixels an "odd" number of 
times. A partially effective algorithm involves ö’ the next 
area fill with a fill command, using a unit vector inbound, 
followed by a unit vector outbound. The inbound vector draws a 
Single fill. The outbound vector e the edge vector 
without drawing a fill vector. The first fill vector drawn by the 
area fill command will address the doubled points for the third 
time. This approach fails when the edge vector has a slope that 
results in three or more points along the same fill vector at the 
endpoint. It is recommended that you avoid complement mode Writing 
for polygon fill. 


A VECTOR B VECTOR 
1 1 
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2 2 
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3 3 
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7 8 9 7 8 9 


ooo N 4 h οο NN 


MR 4 


Figure 4-31 Filled Area 


4-40 


Programming Information 


VVVVVVCVVUVUVVU ina 


aS eee lee 


A VECTOR B VECTOR 


OOO OHHH OR OHO OG ORO OO & @ 
OOOO OCH POCO e e e e n e e e OOOH HOO 
3 3 
OC OOORO OOOH e e e e e e e e OOOH OH OHH HG 


4 5 6 4 5 6 


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7 8 9 10 7 89 10 

„ ee GEE ib bab bob tb aba 

11 11 


POOR OOOOH OHO HG 


Figure 4-32 Filled Area Continuation Showing Doubling 


A VECTOR B VECTOR 


3 2 1 1 
i 6 OG 


COCO CH HOC HEHOHHR HT OCHO e e e 


2 
@ 

654 456 
X++ x 


MA Boge 


Figure 4~33 Diverging Edge Vectors 


A VECTOR B VECTOR 


32 4 123 
CUOMO e n OH e n e e OD HO OOO SG @ ® 
654 456 
OCC OH OOH OHHH OHHH 6 OHO OH HOG 
8 7 789 
oe 


COR CCH e n ee e n OHH HOH HOH eH OHO HOOD 


9 
eo 
11 10 12 11 10 


DAP TOG? 


Figure 4-34 Filled Area with Diverging Edges 


NS fe 
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ood alow 
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trar 


sor/Bitmap Tr 


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BI tmap- to- Processor 


Single-Plane 


4.2.7.1 


RAM 


WE 


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Programming Information 


MMMM MMMM TMM MMM’ MMM MR MMAR MMM ß RM MRM . r IAT Emme ANTI TANNIN 


The series of raster addresses are generated by traversing the 
fast and slow destination vectors. The 5 address is computed 
by adding the offsets from the destination ster to the source 1 
origin. Each time the fast vector is 5 a step along the 
Slow vector is taken. 


As mentioned earlier, the mapping between data in the bit 
the contents of the I/D interconnect is determined by the gi 
supplied for the destination raster. To see how this works, 
realize that the smallest unit of transfer between the bitmap and 
video processor chip is a single 16-bit word whose bitmap address 
is a multiple of 16. These limits are termed “natural memory 
Serio Sates For a normal rasterop, the video processor cl ip must 

lign the source operand so that the position of a bit er ive to 
e raster ö is preserved when the data is to the 
destination. Thi almost always results in a differe tween 
the location of Ge bit relative to the natural boundaries of the 
source and destination. 


ee 


wa 


shown in Figure 4-35. The vertical lines denote word 
the bitmap. 


— 
Se 


As indicated in Figure 4-35, the alignment of raster contents can 
be preserved by shifting the data relative to the natural word 
boundaries. The shift amount is equal to the difference between 
the x coordinate of the source and the X coordinate of the 
destination, converted to a modulus of 16. The resulting I/D 
interconnect data word is a copy of the source, after it has been 
aligned with the corresponding word in the destination . 
Because the destination is not written, the destination addre 
can be used to simply align the raster within the I/D interco 

data word. In some cases, it is desirable to align the Y edg 
the raster with bit 0; therefore, a destination origin of 0, 
used, and destination indexing is disabled. 


65 
5 
i 
i 


oe 
0 


e of 
QO is 


e 


. 
2 


5 1 


.ustrates 
yr various 
ng pixel 
is. Each 


To further show the effect of shifting, Figure 4-36 111 

how a Sot raster is packed into system memory fo 

destination raster X addresses. Note that increasi 

addresses in X correspond to increasing b positi 
8 i 6 


i it r 
character represents the state of one bit in refresh memo 


1 
© 
a 


. 


e 


Figure 4-35 Source-to- Destination Alignment 


Programming Information 


C UGS GSR i a NA SOA Gl Rain ele ila 


BITMAP MicroVAX CPU 


SOURCE 1 ORIGIN AT 15,0 


n DESTINATION AT 0, 0 


000000000000001 X DESTINATION AT 1,0 
XXXXXXXXXXXXXXO 
QOO0000000000001 X 


IXXXXXXXXXXXXXNN DESTINATION AT 15, 0 
XQOOOOO0000000000 
LP ,©,9,9,9,9,0,0.6. 0.0.9.0. 9 4 
KOOOOOOOOCO00000 


MPO GG29 


Figure 4-36 Bitmap-to-Processor Mapping (Simple Case) 


a 


15 


The X symbols in Figure 4-36 represent bits read in from areas to 
the left or right of the source due to the shifting needed to 
align the source raster with the destination. Observe how the 
destination alignment effects the number of MicroVAX memory 
locations required to store the data. When the left edge of the 
source raster is aligned with bit 0 of the destination, 16-bits of 
Source data are contained in a single 16-bit word in the 
destination. When the left edge is not aligned, the source data 
spans two 16-bit words in local memory. 


Figure 4-37 shows a more general case, where the source raster is 
larger than the memory bus width and local memory word size. 


From the example shown in Figure 4-37, it is clear that the space 
to store a raster in local memory depends partly on the alignment 
of the destination raster origin. The space computation is 
performed by: 


1. Determining the number of natural words in the bitmap that 


would be spanned by the destination fast vector 


2. Multiplying this value by the height of the destination 
raster. 


Based on the above, the following procedure can be derived. 
Compute the number of natural words spanned by the 
fast vector. Only integer division is used. 


Truncate the starting address to a word boundary. 


ae gu get Gee Bee soe 


4-44 


Programming Information 


in 


* 
— 


:= (DESTINATION X/16) * 16 


Compute the endpoint in the X-axis and round up to 
the nearest word boundary. 


Compute the endpoint coordinate. 


X2 := DESTINATION X + DESTINATION_X_LENGTH 
! 

! Round up to a multiple of the word size. 
' 

X2 : ((X2 + 16)/16 ) * 16 


Compute the number of words spanned by the X vector. 


Sa go See 


X WORDS = (ABS (X2 - X1))/16 


Compute the total number of words required. 


aS ee oe 


N WORDS = X_WORDS * ABS (DESTINATION Y LENGTH) 


Of course, all of the above can be simplified by suitable 
optimization. 


BITMAP 
SOURCE 1 ORIGIN AT 15,0 MicroVAX CPU 


15 33 15 


10000000000000001 1 —— 0000000000000 DESTINATION AT O. 0 
10000000000000001 1 MKXKKKKKKAKAKK AM I 
4 f OO0000000000000 

1 


1 
1 
1 
; 


RASTER XXXXXXXXXXXXX 


WIDTH 


000000000000001 X DESTINATION AT. 0 
XXXXXXXXXXXXIIO 
00000000000000 1 
XXXXXXXXXXXXIIO 


XXX XXXXXXXXX DESTINATION AT 15, 0 
100000000000000 
XXXXXXXXXXXXXX! 
XXXXXXXXXXXXXN 
100000000000000 
XXXXXXXXXXNXX XX 


WPL TOG 3G 


Figure 4-37 Bitmap-to-Processor Mapping (General Case) 


4-45 


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Programming Information 


VVV 


4 


The portion of the data word that is outside the raster boundaries 
is masked out. Since the output is not rotated, it is the 
responsibility of the local processor to ensure that the data is 
aligned properly before being written to the bitmap. 

To visualize the problem, consider the example shown in Figure 
4-39, The short vertical lines mark addresses in the bitmap that 
are multiples of the memory bus width. 


In Step 1 of Figure 4-39, data is transferred from the bitmap that 
results in each 16-bit bitmap segment being shifted into alignment 
with bit 0 in local memory. In Step 2 the contents of local memory 
is later written back into the bitmap at the same location from 
which it was read, but without the shifting required for proper 
alignment. 


Since each memory word is written into the bitmap, so that it is 
aligned with the natural boundaries, the image is shifted left 
with respect to its original position. The part outside the raster 
limits is actually masked, and the part of the image adjacent to 
the right boundary is replaced with the random data that was in 
the high-order bits of local memory. 


BITMAP SYSTEM MEMORY 


INCREASING 
MEMORY 
ADDRESSES 


115 
BITMAP 
TRANSFER 


ee 


IX XXX XX 


|ASTEF 


STEP 2 - PROCESSOR-TO-BITMAP TRANSFER 


AEP ee 


Figure 4~39 Alignment Error Example 


Programming Information 


AAO SAS RRO UGE EHS DSB ARNO DUT A RO Dio TN Poin i Eis aR oN Nae iii 


The corrective alignment of output data can be accomplished by: 


1. Aligning the data on inpu from the bitm des based on 
Knowledge of where the output raster will be located 


Emulating the video processor chip barrel shifter function 
on output 


& 
8 
. 


3. Forcing a raster to be aligned on natural bus-width 
boundaries. 


The first method is suitable for pete and restoring an image in 
place of using a DMA device. In this case, the number of words to 


be transferred is computed as 19 755 in the previous section. on 
the bitmap~to-processor transfer, the video processor chip 
automatically performs the required alignment. The resulting 


1 


raster is then transferred to local memory, and the following 
parameters are saved. 
. The parameters of the original raster, including the 
origin and dimensions 


6 The number of vords transferred 
To restore the image, the aid eke raster is defined using the 
parameters ne earlier, and the DMA device is requested to 
transfer the specified number of words. The output is 


automatically masked to the raster boundaries. 


e goal is to emulate the video processor 
chip barrel shifter by shifting the data based on the difference 
etween the xX coordinate of the input and output rasters (modulo 
). During the bitmap-to-processor transfer, the data may be 
j 
oe 


In the second case, th 
S 


ligned in any convenient manner by specifying the destination 
raster address appropriately. On output to the bitmap, the shift 
is performed by the MicroVAX CPU, concatenating adjacent words as 
required. The net shift amount, between input and output, must 
equal the difference computed as described above. The disadvantage 
of this method is that, on abe it is not amiable to processing 
by a DMA engine. 


Sh 


The third on ethod is also useful when the ultimate destination is 
not known. ‘thi 8 N lends itself to a DMA processor, but 


incurs added overhead for an additional rasterop. In this case, 
the input raster parameters for the bitmap-to-processor transfer 
are modified by truncating the origin and rounding up the X 
dimension so that both are a multiple of 16. The raster is stored 
in system memory using the modified dimensions. 


Restoring the image is a 2-step process. First, the image is 
transferred to a staging area in off-screen memory using the 
aoe ted dimensions. It is then moved to the ultimate destination 

Sing the original raster 5 ons. Data outside the raster 
limits is masked out (that is, the i 


xo 5 


xternal area is not modified). 


Programming Information 


inp 


4.2.7.3 Z-Axis Processor/Bitmap Transfers -- Z-axis transfers 
move the contents of a raster, aligned with the X- and Y-axis, to 
or from local memory one pixel at a time. Each data word 
represents up to 8 bits of pixel value. 


Since each transfer involves only one pixel, there are no 
requirements for shifting or alignment. Data is transferred by 
scanning the fast vector, which sweeps out a path defined by the 
Slow vector. Like a rasterop, the scanning algorithm does not 
trace out the last point. Therefore, the raster parameters must be 
adjusted accordingly. 


Z-Axis Bitnap- to- Processor Transfers 

Z-axis transfers from the bitmap to the processor move the 
contents of a source raster that is aligned with the X&— and 
Y-axis. The operation is defined by the following parameters: 


. The raster size — Defined by the magnitude of the fast 
and slow destination vectors. The fast vector must be 
parallel to the X-axis, and the slow vector parallel to 
the Y-axis. 


e The raster origin — Defined by the coordinates of the 
source 1 operand. 


The number of words transferred is equal to the total number of 
pixels enclosed by the raster. 


Z~Axis Processor-to-Bitmap Transfers 

Z~axis transfers from the processor to the bitmap fill a 
destination raster with pixel values contained in local memory. 
The following parameter defines the transfer. 


e A destination raster defined by the origin and extent of 
the destination operand 


. 


As for the bitmap- to- processor transfer, the number of pixels is 
defined by the total number of pixels enclosed by the raster. 
4.3 ADDRESS PROCESSOR CHIP DESCRIPTION 

The interface from the MicroVAX CPU to the video processor chips 
and bitmap is through a set of address processor chip registers 
that: 


Set system and CRT timing 


Le 
2. Hold rasterop and scrolling parameters 
3. Control address processor chip operation. 


Unless otherwise specified, all registers are vrite-only, and 
numerical registers contain a 14-bit, 2's complement value 
(including sign). The upper 2 bits are unused and must be set to 
Zero. 


In some cases, loading a register causes a specific system action 
to be taken. This is noted in the register's description. 


4-49 


Programming Information 


ieee F d ß r eT a ine NEON ee tN CNR OOH RU 


4.3.1 Coordinate Systems 
In the VCBO2 video subsystem, images are referenced through two 
Cartesian coordinate systems: 

1. Memory coo 


‘dinates, refere 
physical bitme 


* referenced to the origin of the 

tmap memory space 

2. Screen coordinates, referenced to the upper left corner of 
the CRT. 


In either case, X increases to the right and Y increases downward. 
32 Address Processor Chip Commands 


address processor chip commands are written into one of the 


4. 
All 
following registers. 


05 The COMMAND register, for update commands. 


ID SCROLL COMMAND register, to load an I/D 
terconnect command while a rasterop is in progress. The 
contents of the high byte are ignored. 


nd port is provided for the video proc 3 
form loading of various scrolli ing an 
without 1 ng with rasterops in progress. The sole function 
of this ae. Ee to issue I/D interconnect hehe Therefore, t 
contents of the high byte are ignored. 


a 


The scroll comme 
registers 
¢ 


* 
rer 
** 
rhs 


4.3.2.1 Rasterop Command -- 


The following video processor chip registers must be set up. 


@ For each enabled operand: 


© 
2 
ie 
Sea 
eS 
Pa 
. 
. 
- 
8 
. 

2 
e 
Sede 
seg 
— 


The in the selected bank. Within each bank, 
he address processor chip makes the following assignment of 
CD bes A. Pe re 

SRS to operands. 


fe 
05 


we 
See 


. 
* 


a 


os 
ee 

ee 
ae 


va 


oar 
a . 
5 Fe 

e, 


Bank 


Bank 0 
Bank 0 


ae 
43 
e, 
ee 
40 
fy 


® The logit ction register specified in the command word. 


4-50 


Programming Information 


ionic wel i etl io i EUR ei eer i aie ui ii eG tii iin ß t OA NE OG NER NN REPRO ODI 


a 


The following address processor chip registers must be set up. 


e Destination operand parameters: 


DESTINATION __X Destination X origin 
DESTINATION Y Destination Y origin 
FAST DEST DX Destination fast Dx 
FAST DEST Dx Destination fast DY 
SLOW. DEST __ Dx Destination slow Dx 
SLOW DEST Dx Destination slow DY 


5 If the source 1 operand is enabled: 


FAST SOURCE 1 Dx Fast source 1 DX increment 
SLOW SOURCE 1 DY Slow Source 1 DY increment 


SOURCE I X Source 1 X origin 


bonkbedeken hen 


SOURCE 1 ¥ Source 1 X origin 


FAST SCALE Fast vector scale factor 
SLOW SCALE Slow vector scale factor 


® tf the source 2 operand is enabled: 


SOURCE 2 & Source 2 X origin 

SOURCE 2 Y Source 2 Y origin 

SOURCE 2 SIZE Source 2 height, width and tiling 
enable flag 


en 


MODE set as follows. 


€1:0> Set to one of the following values. 


0 = Normal mode. Source area is determined from 
the scaled destination area. 
10 = Linear pattern mode. 


4 > Hole fill enable, as required. 

> First source indexing enable, as required. Will 

usually be set, if the first source is within a 

Pee ea 

<6> Destination indexing enable, as required. Will 
usually be set, if the destination is within a 
region. 

<7> Pen down, as required. Set based on whether or not 

the destination raster is to be written. 


4~5] 


Programming Information 


nenen hu eee enn 


Rasterop Protocol 

The following protocol is used to initiate a rasterop. 
ROUTINE NEW RASTEROP (Video processor chip parameters, 
address processor chip parameters) 


This entry point is called when starting a new rasterop. 
That is, when the last function issued through the command 


a 


register is different from the one to be issued. 


See gee Goss 


1 Wait until it is safe to load all registers. 

WAIT UNTIL STATUS <address output complet an IS SET 

Load Video Processor chip parameters 

Load Address Processor chip parameters 

Load Rasterop Command 

RETURN 

The following protocol is used when continuing a rasterop. 
Continuation is defined as a repetition of the last rasterop 


command, modifying only the source 1 and destination operands. 


ROUTINE CONTINUE A_RASTEROP (COMMAND, SOURCE I X,SOURCE 1 », 
DESTINATION X,DESTINATION Y) 


! This routine is called when a rasterop command is to be 

{ continued with the only change being the origin of the first 
! tre and destination operands. This mode is useful when 

! writing text into the bitmap. 

{ Wait until it is safe to reload the source 1 and destination 
i 


origins. 
WAIT UNTIL STATUS <Initialization complete> IS SET 


LOAD Address Processor chip with SOURCE 1 X, SOURCE 1 Y, 
DESTINATION X, DESTINATION Y 


! COMMAND must be identical to the last command. 
LOAD Address Processor chip with COMMAND 


= 


RETURN 


The following protocol is sed when any address processor chip 


ac 


rasterop parameter is to be modified. To improve throughput, it is 
executed while addresses from the previous rasterop are still in 
the pipeline. The following are the parameters that may be 


modified. 


4-52 


Programming Information 


FAST SOURCE 1 Dx 
FAST SOURCE 1 Dx 
SOURCE 1 xX 
SOURCE 1 Xx 
DESTINATION X 
DESTINATION Y 

FAST DEST Px 

FAST DEST Dx 

SLOW DEST Dx 

SLOW DEST Dx 

FAST SCALE 

SLOW SCALE 

SOURCE 2 X 
SOURCE 2 Y 
SOURCE 2 SIZE 
RASTEROP MODE 


ROUTINE MODIFY A RASTEROP (COMMAND, Address Processor chip 
parameters) 5 

! This command allows the next rasterop to be started as soon as 
the address processor chip has completed address generation from 
! the previous rasterop, but before all the previous addresses 
! have been used by the video processor chip. 
1 The command word must be identical with the last command. 


! Wait for rasterop address computation to finish. 
WAIT UNTIL STATUS <rasterop complete> IS SET 


LOAD address processor chip parameters 

LOAD command register with next rasterop function (COMMAND) 

RETURN 

4.3.2.2 Processor/Bitmap Transfers —— The following commands 

transfer the contents of a single plane or a series of pixel 

values between the MicroVAX CPU and a raster in the bitmap, 

Single-Plane Processor-to-Bitmap Command 

Implicit Inputs: 

The planes not receiving data are disabled, either through the 

chip select hardware or by programming the CSR in each video 

processor chip appropriately. 

The following video processor chip registers must be set up. 

@ Control store RAM —— Set up to receive data from the I/D 
interconnect during the external cycle. Other fields are set 
up as required. 


® Logic function control register 


5 3 
Al Wee e 


Programming Information 


Rt ee UNE ER RN OURS t I FT IONS ge ß SURO REC ei aii 


The following address processor chip parameters must be set up. 


ODE set as follows. 


<4> Hole 5111 ‘weenie = 0 
55 ion indexing AS 1 


= 
* 
pee 
Led 
& 
@ 
cr 
pee 
= 
ee 
rr 
goede 


INATTION X X origin of output raster 
INATION Y Y origin of output raster 
_DEST Px Length of output fas st vector 
_DEST. DY Y component of fast vector = 0 
DEST DX X component of slow vector = 0 
“DEST Ds Length of output slow vector 


ST SCALE 
SLOW SCALI 


Single-Plane Bitnap- to- Processor Command 

Implicit Inputs: 

The planes not transmitting data are disabled, either through the 
hip select hardware or by programming the CSR in each video 

rocessor chip appropriately. 

The following video processor chip register must be setup: 

up to transmit data to the I/D 


terconnect during the external cycle. Other 
lds are ignored. 


Control Store RAM Se 


The following address processor chip parameters must be set up. 
6 MODE set as follows. 


5 mode = 00 (normal mode) 
le fill enable = 0 

ce 1 indexing As required. 
tination indexing As required. 


jodie 


x orig n of input raster 
Y origin of input raster 


i 
gi 
Length of input fast vector 


PAS component of fast vector = 0 

SL. X component of slow vector = 0 

S LOW _ Length of output slow vector 

SOURCE 1 Dx Must have the same sign as the destination 


fast vector 
CE . Must have the same sign as the destination 
| slow vector 
FAST SCALE = Unity 
SLOW SCALE = Unity 


Programming Information 


Z-Axis Processor-to-Bitmap Command 
Implicit Inputs: 
The following video processor chip register must be set up. 


® Logic function control register 10 must be set up to copy the 
pixel value into the bitmap. 


The following address processor chip parameters must be set up. 


@ MODE set as follows. 


<1:0> Rasterop mode = 00 (normal mode) 

<4> Hole fill enable = 0 

<6> Destination indexing As required. 

<7> Pen down As required. 

DESTINATION X X origin of output raster 
DESTINATION IV Y origin of output raster 

FAST DEST Dx Length of output fast vector 
FAST DEST Dx * component of fast vector = 0 
SLOW DEST Dx X component of slow vector = 0 
SLOW DEST DY Length of output slow vector 


FAST SCALE = Unity 
SLOW SCALE = Unity 


Z~Axis Bitmap-to-Processor Command 
Implicit Inputs: 
The following address processor chip parameters must be set up. 


5 MODE set as follows. 


<1:0> Rasterop mode = 00 (normal mode) 

<4> Hole fill enable = 0 

252 Source 1 indexing As required. 

<7> Pen down As required. 

SOURCE 1 X X origin of input raster 
SOURCE 1 Y Y origin of input raster 

FAST DEST Px Length of input fast vector 
FAST DEST DN Y component of fast vector = 0 
SLOW DEST Dx X component of slow vector = 0 
SLOW DEST DY Length of input slow vector 


FAST SCALE = Unity 
SLOW SCALE = Unity 


SOURCE 1 Dx Must have the same sign as the input 
fast vector 
SOURCE 1 DY Must have the same sign as the input 


Slow vector 


Programming Information 


‘svat 


sisi ine f TF US AN GT Oi 


4.4 VIDEO PROCESSOR CHIP DESCRIPTION 


4 Z~Axis Addressing Mode 

ne Z-axis addressing mode reduces and, in most cases, eliminates 

he adverse effect on performance caused by the addition of more 

bitmap memory planes. Certain graphics operations executed by the 

MicroVAX CPU, such as flooding or painting an area, require that 

he 8 of a pixel be processed in the MicroVAX system's memory. 
out hardware assistance, assembling all the components of a 

. requires intervention by the MicroVAX CPU to: 


—8 


1. Read the data in every plane or subplane 


2. Perform the required shifting and masking functions to 
extract each component of the pixel 


3. Combine the extracted pixel component with the result. 


Once the operation is complete, a reverse procedure is needed to 
set the state of the bitmap. Obviously, therefore, system 
performance degrades as the number of memory planes increases. 


With Z-axis addressing, on the other hand, logic within each video 
processor chip can be used to assemble or digs ssemble up to 
16-bits of pixel va tue in a single transaction. A further 
performance improvement can be achieved by using the DMA support 
to perform the actual processor-to-bitmap transfer. 


The video processor chip's Z-axis logic: 


* Inserts bitm ap data at the correct position in the word 
for a bitmap-to~-processor transfer 


® Extracts data from the correct position in the word for a 
processor~to-bitmap transfer. 


Figure 4-40 shows the relationship of address to position for a 
4~plane system. 


ip is numbered with its Z-axis address. As 


Each video processor j 8 i 
4 through 15 of the data word are unused. 


Figure 4-40 shows, bi 


NOTE 
On a Z-axis bitmap to processor 
transfer, the value of unused bits are 
undefined. 


The maximum value of a pixel is determined by the number of 
physical memory planes. 


Programming Information 


e r ß N a UU i nau coN 


i/D INTERCONNECT DATA 


4 deem e . 160 5 0 4 e 
10 0 e. sol ib 5 = 


Figure 4-40 Z-Axis Addressing 


Here are some things to remember about Z-axis processing: 


1. A video processor chip can have any Z-axis address, if it 
does not overlap the address assigned to another video 
processor chip. 


2. The states of unused bits are undefined. These bits must 
be set to some known state before referencing the pixel 


value. 


4.4.2 Z~Axis Register Loads 

The video processor chip foreground, background, source, and 
scroll fill registers are set to specific colors by the MicroVAX 
CPU. To facilitate this, the Z-axis register load function is 
provided to perform similarly to the Z-axis processor-to-bitmap 
transfers. Namely, in one I/D interconnect transaction, each video 
processor chip in à block extracts data from that portion of the 
I/D interconnect specified by the bit address. The bits of the 
selected register will either be set to all 1s or all Os, 
corresponding to a 1 or 0 in its bit position in the data word. 


4-57 


CHAPTER 5 
DIAGNOSTICS 


e aco ni NSD NEN Oli i oS Eel ff 


se | OVERVIEW 

This chapter contains information on diagnostic and console 1/0 
firmware that will aid the user in isolating VCB02 module faults 
at the field-replaceable uf nit (FRU) level. The 022-Bus VCBO2 video 
Subsystem is a multiplane bitmapped graphics controller that 
provides enhanced graphics processing capabilities to VAXstation 
II/GPX workstations. The hardware allows the user to install VCBO2 
modules of 4 or 8- planes where one specific address has been 
reserved as a secondary alternate console device. 


ae 


ae the 


The diagnostic VCBO2 ROMs total 16 kilobytes and resi 
VCB02 base module. Power-up self-test and console 1/0 Su 
provided by the diagnostics. The power-up self-test is a 
test, invoked by the KA630 ROM, that quickly tests the VCBO 
subsystem. The power-up self-test verifies the VCBO02 ¢ 
bitmap memory, video signals, interrupts, DMA, DUART, 
and mouse or tablet. 


The console I/O support provides suff 
the input and output for the console PEC 
ROM. Some of the functions include ini 
put character poll, and put character. 


555 
Seeds 
N 
8 
rT 
poke 
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22 0 
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eer 
@ 


5.2 OPERATION 

When the KA630 CPU module is powered on, it begins execut 
console program that resides in the KA630 ROM. Determining 
was invoked on power-up, the KA630 ROM performs the fo 
steps before any video display device is referenced. 


Le TOY chip verification. If the battery is too low or the 
battery backed-up RAM contains an invalid checksum, t 
clock is stopped and the time is zeroed. The console 
language and keyboard information is cleared, causing a 
language query later for the operator. 


= 


Each page of memory is checked until five good pages 
found. These pages will be used for the console page, 
console stack, system memory bitmap, and diagnost 
scratch space. 


See A diagnostic is run to verify that the Q22-Bus is 
arbitrating. 


Diagnostics 


en muten tene 


The next step is 


to determine wie type of eas Beata! device is 
P esent. The types 


r of video splay devices clude the primary 
alternate console display 3 se (VCB0I - . I/II) or the 
Secondary alternate console device, such as the VCBO2 (MicroVAX 
IT/GPX workstations) or none at all. The console program reads 
address 20001E92H followed by . 20001F0O0 OH. If either address 
responds „ the console program 
the U.S. font able, the base address 
table, the add 8 

Keyboard f in 


loads the base address of 
of the multinational font 

a of the keycode translation routine, and the 
flag into the proper entries of the console page. 


If address 20001E92H responded correctly, control passes to the 
VCBOI power-up self-test, which resides in the KA630 ROM. The test 
checks the VCBO1l and updates the missing entries of the console 
page. 


If address 20001E92H responded incorrectly and address 20001F00H 


responded correctly, the console program maps the VCBO2 ROM, 
checksums the VCB0O2 ROM, finds and checksums the VCB02 power-up 
self-test file, and passes control to the VCBO02 power—up 
self-test. The test checks the VCBO2 and updates the missing 
entries of the console page. No other VCB02 in the system is 
affected. 


After the console device has been selected and tested, the KA630 
ROM uses that device for console input and output. Other software 
applications have the ability to use the console I/O functions 
indirectly through the KA630 ROM via specified KA630 ROM addresses 
or the console pages Specific applications include power-up, bug 
checks, and halt situations. 


Dace IMPLEMENTATION 


8 Performance 
The power-up self-test provides 90 percent fault 


detection/isolation to the FRU level. The VCBOZ video subsystem's 
FRUS include the following. 


® VCB0O2 base module 
® First VCB0O Z 4-plane module 
0 Second VCB02 4- plane module 
LK201 keyboard 
& Three- button ci 5 mouse 
0 Optional digitizing tablet 
For an 8-plane video subsystem, the power-up self-test executes in 


under 30 seconds. The ‘diagnostic code is contained in 16 kilobytes 
of ROM space. 


wi 
i 
— 


& 4 
8 8 


Diagnostics 


5.3.2 Compatibility 

The diagnostic code is compatible with the KA630-A processor, the 
KA630-A console program, the self-test responses specified for the 
keyboard/mouse/tablet, and the MicroVAX diagnostic ROM 1.0 format. 


. Hardware Failure 

Failures may be nonfatal or fatal. A nonfatal error inhibits 
further testing of an operation or function of the device. This 
applies specifically to manufacturing, where external loopback 
connectors are attached in place of the respective manual input 
devices such as a keyboard or mouse. When a nonfatal error occurs, 
the power-up self-test saves the error information and continues 
testing the video subsystem. If no other error occurs, the 
power-up self-test updates the lights, and passes control to the 
KA630 ROM with the error information. A nonfatal error does not 
override a fatal error or a second nonfatal error. 


A fatal error inhibits further testing of the device. Most of the 
power-up self-test's errors are categorized as fatal. When a fatal 
error occurs, the power-up self-test saves the error information, 
updates the VCB02 lights, and passes control to the KA630 ROM with 
the error information. Fatal errors override nonfatal errors. 


. Unexpected Traps 
The power-up self-test treats unexpected traps as fatal errors. 


oe ee. Power Failures 
The diagnostic does not handle power failures. 


5.3.6 Restrictions 


rc 


ar The diagnostic must be executed on a KA630 system. If 
is attempted on any other system, the code may 
improperly invoked, or not at all. 


ob 
i 


24 The diagnostic tests a single VCB02 video subsystem 
residing at the secondary alternate console address, 
2001FOOOH. It does not test any additional VCB02 video 
subsystems residing at other addresses. However, the 
diagnostic is callable, so higher level software, such as 
MicroVMS and ULTRIX, can execute the self-test on any 
VCB02 video subsystem. 


a5 The power-up self-test does not isolate faults to the 
component level. 


4. The diagnostic supports the character set supported by 
the KA630 ROM, which includes ASCII-printable characters, 
Digital's multinational- printable characters, carriage 
return, line feed, backspace, and bell. This excludes the 
remaining 7-bit control characters, 8-bit control 
characters, delete, and all escape sequences. 


Diagnostics 


5.4 DIAGNOSTIC OPERATIONAL REQUIREMENTS 


5.4.1 Hardware 
The diagnostic operational requirements for hardware are: 


Ls KA630 system. 


2. VCB02 base module, first 3 ae “plane module, and 
optional se : 


3. LK201 keyboard and optional VSXXX-AA mouse or optional 
VSXXX-BA tablet. External loopback connectors can be 


attached to both keyboard and mouse ports. 
4. VR260 monochromatic or VR290 color monitor. 


5.4.2 Software 
The diagnostic operational requirements for software are: 


ae The KA630 system lights are up¢é 
power-up self-test, which updates tt 


— 
— 
1 
<i 
OC 
us 
— 
ho 
Pi 
beds 
aS 


2. Memory must be configured as shown in Figure 5-1. 


Hy 


Qn ASSASSIN ORR NR RDI SOS IES KON ORAS RNR 


CONSOLE PAGE 


wangen nnz ene ebenen ele SMBUS 


STACK 


r . 


cee 
ee 


Ca a ede enen aaenumeemn 


SYSTEM MEMORY BITMAP 


e . vo RR NIN 


SYSTEM MEMORY BITMAP BASE ADDRESS 


DIAGNOSTIC SCRATCH (2 OF 2) 


SYSTEM MEMORY BITMAP BASE ADDRESS ~ 200H 


DIAGNOSTIC SCRATCH (1 OF 2) 
SYSTEM MEMORY BITMAP BASE ADDRESS 400H 


LOW MEMORY 
Figure 5-1 Memory Configuration Required 
for Power-Up Self-Test 


5-4 


Diagnostics 


cr The console page is configured as listed in Table 5—1. 


4. Rll must contain the base address of the console page. 


Table 5-1] Console Page Configuration 


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6 eser t n 


— . GME RAIS DN EB MEH ESSE SEU HN SRNR SHR AHORA HAR ONCE S HORAN ¶ ¶ · ¶ · · / / / 


00H (R11) 


18H (R11) 
1CH (R11) 
20H (R11) 
24H (R11) 
28H (R11) 
2CH (R11) 
30H (R11) 
34H (R11) 
38H (R11) 
3CH (R11) 
40H (R11) 
44H (R11) 
48H (R11) 
4CH (R11) 
4DH (R11) 
4EH (R11) 
4FH(R11) 
50H(R11) 
51H (R11) 
52H (R11) 
53H (R11) 
54H (R11) 
55H (R11) 
56H (R11) 
57H (R11) 
58H (R11) 
5CH (R11) 
60H (R11) 
64H (R11) 
68H (R11) 
6CH (R11) 
7OH(R11) 


AFFH (R11) 


. e e pff NS IR A HS IHN OAS IR SRS 


Reserved for KA630 RON 


* 


Reserved for KA630 ROM 

Get character 

Put character poll 

Put character 

Console enable and bus reset 
Console enable and reset 
Console reset N 

Keyboard put character 
Software service 

VCB0O2 I/O space CSR 

US font table base address 
Multinational font table base address 
Keycode translate character 
Current character row 

Minimum character row value 
Maximum character row value 
Reserved 

Current character column 
Minimum character column value 
Maximum character column value 
Reserved 

Reserved for keyboard flags 
Reserved 

Reserved 

Reserved 

VCB02 memory space CSR address 
Wait 1 millisecond 

Reserved 

Boot memory base address 
System memory bitmap base address 
System memory bitmap length in bytes 
Reserved for KA630 ROM 


Reserved for KA630 ROM 


Deo 


CCC 


Diagnostics 


iia 


Da The VCBO2 ROM must be properly mapped, and the diagnostic 
i side in the proper address space, and be 
verified by the checksum specified in the MicroVAX 
diagnostic ROM format 1.0 before executing the power-up 

self-test. 


6. In kernel mode, all addresses must agree with the memory 
management state: if physical, all addresses must be 
physical; if virtual, all addresses must be virtual. 

5.5 FUNCTIONAL DESCRIPTION 
Dis wa Power-Up Self-Test 


See lod Parameters Passed and Returned — Tf the power-up 
self-test is invoked on power-up, no parameters are passed when 
the VCBO2 ROM is executed on power-up. If the Bowe rcp self-test 
is invoked by software control, the 5 parameters must be 


passed: function code, console page base address, system control 
block addr ess, bus adapter offset, 1 vector offset, bitmap 
Q22-Bus eer maximum interrupt priority level, minimum 
interrupt priority level, and a console page. The function code 


Should be 1. Any other band tion code will execute "no operations" 
and return a successful status. Refer to the calling sequence for 
the proper method to pass the parameters. 


NOTE 
When invoking the power-up self-test by 
software control, it is important that 
the addresses agree with the memory 
management state. For example, if memory 
management is on, the addresses should 
be virtual. 


If the power-up self-test passes, the procedure returns RO with a 
value of 1, and RI with a 0. If the power-up self-test fails, the 
procedure returns RO with a value of 0, and Rl with an error code. 
If external loopback connectors are attached and the power-up 

self-test passes, the procedure returns RO with a value of 2, and 
R1 with an error code. Refer to Table 5-2 for the error code 
definitions. 


9.5.1.2 VCBO2 Diagnostic LEDs — The VCB02 base module diagnostic 

LEDS or lights (see Figure 1-1) are lit on power-up. The power-up 
self-test must properly update the VCBO02 lights and inform the 
user of the status of the VCB02 video subsystem. When the power-up 
self-test is invoked by the KA630 ROM, the VCB02 lights are 
updated by the VCBO02 ROM to indicate that the power-up self-test 
is being executed. When the power-up self-test is completed, the 
VCBO2 lights are updated to indicate the status of the subsystem. 
If the VCBO2 lights are out, either the system is functioning 
correctly, or the lights are not working. Otherwise, the VCBO02 
lights identify the failing FRU, as listed in Table 5-3. 


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Diagnostics 


sie ec neunten ene 


_Table a- 2 Error Codes 
ETror 
. . 
0 Everything is e r 
1 Unexpected machine check or VcBO2 interrupt. 
2 Register access or data fault. 
3 Template RAM fault. 
4 Address processor failed to interrupt. 
8 Address processor interrupt status fault or too many 
address processor interrupts. 
6 Hardware initialization fault. 
7 Update video processor enable chip select fault. 
8 Bitmap memory data path fault. 
(first VCBO2 4-plane module) 
9 Bitmap memory data path fault. 
(second VCB02 4- plane module) 
10 Bitmap memory data fault. 
(first VCBO2 4- plane module) 
11 Bitmap memory data fault. 
(second VCB02 4- plane module) 
12 Bitmap memory address fault. 
(first VCBO2 4-plane module) 
13 Bitmap memory address fault. 
(second VCBO2 4—-plane module) 
14 Bitmap memory fault. 
(VCBO2 base module) 
15 Right scroll fault. 
(first VCBO2 4-plane module) 
16 Right scroll fault. 
(second VCB02 4-plane module) 
17 Right scroll fault. 
(VCB02 base module) 
18 Down scroll fault. 
(first VCBO2 4-plane module) 
19 Down scroll fault. 
(second VCB02 4-plane module) 
20 Down scroll fault. 
(VCBO02 base module) 
2 DMA to bitmap failed to interrupt. 
22 DMA from bitmap failed to interrupt. 
23 Data fault during DMA transfer. 
24 Video processor fault during DMA test. 
(first VCBO02 4-plane module) 
25 Video processor fault during DMA test. 
(second VCB02 4- plane module) 
26 Address processor fault during DMA test. 
(VCBO02 base module) 
27 DMA interrupt status fault or too many DMA interrupts. 
28 Cursor B failure during horizontal sync test. 
29 Horizontal sync did not occur. 
30 Draw boundary lines failure. 
31 _Cursor B failure during green tes ting. 


Diagnostics 


Table 5—2 _Error Codes (Cont) 
Error 
Number Description 
32 Green color map i 
33 Cursor B failure during red testing. 
34 Red color map failure. 
35 Cursor B failure during blue testing. 
36 Blue color map failure. 
37 DUART failed to interrupt. 
38 DUART interrupt status fault, too many DUART 
interrupts, or data error. 
39 Keyboard or loopback not connected properly. 
40 Keyboard failure. 
41 Mouse loopback not connected properly. 
42 Mouse failure. 
43 Power- up self test initialization failure. 


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Table 5-3 _VCBO2 Light Definitions 
Aion 
D6 8 7 Description 


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During Power-Up_ Self- Test 


* * * Hardware state on power-up. 
0 0 = Executing power-up self-test. 
xX X X One of the 1 definitions described below. 


After Power- up 8 sel f- rest 
No faults detected. 

VCB02 base module fault. 

First VCBO2 4-plane module fault. 

Second VCBO02 4-plane module fault. 

Not used, 

Keyboard fault. 

Mouse or tablet fault. 

Catastrophic. 


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Diagnostics 


The symbol D6 represents the bottom LED; the symbol D8 represents 
the middle LED, and the symbol D7 represents the top LED. 


5.5.1.3 Register Access and Data Test — This test reads the 
secondary alternate console CSR and verifies the VCBO2 has a valid 
configuration. Valid configurations include: either a first VCB02 
4-plane module, or first and second VCB02 4~plane modules. If no 
VCBO02 4-plane modules, or only the second VCB02 4-plane module, 
are detected, an error is reported. The test reads each address on 
a word boundary within the register mapping space, and verifies 
that each address on a word boundary responds properly. The test 
does not read the VCBO02 ROM, template RAM, and "not used" address 
space. The VCBO02 ROM is assumed to be working correctly. The 
template RAM is verified in a succeeding test. 


The test writes a set of patterns, reads, and compares the 
patterns with all readable and writable registers, The patterns 
include the following. 


5555. 
AAAAH 
3333H 
OFOFH 
OOFFH 


The registers include the DMA address counter, DMA byte count, 
FIFO register, vector base, and memory base register. The vector 
base is initialized. 


5.5.1.4 Template RAM Test <-~ This test writes a set of 
patterns, reads, and compares the patterns with the first template 
RAM address. The patterns include the following. 


5555H 
AAAAH 
3333H 
OFOFH 
OOFFH 


The remaining test consists of three passes. The first pass writes 
a 5555H pattern from the first template RAM address through the 
last template RAM address. The second pass reads and compares the 
pattern, and writes an AAAAH pattern from the first template RAM 
address through the last template RAM address. The final pass 
reads and compares the pattern, and writes a 5555H pattern from 
the last template RAM address through the first template RAM 
address. 


Diagnostics 


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ö Address Processor Test — This test verifies that the 
address processor can function and interrupt. The test sets up the 
hardware to handle address processor interrupts, issues the 
"cancel" address processor command, and waits for an address 


processor interrupt generated by the I/D data transmit ready line. 


5.5.1.6 Address Processor and Video Processor Initialization Test 
This test initializes the address processor and video processor 
hardware. 


oes re es Update Video Processor Enable Chip Select Test — This 
test verifies the video processor chip selection. It begins by 
initializing point [0,0] for all the planes: 

1. Select all planes. 

2% Using one processor~to~bitmap Z-mode command, write a 0 


to point [0,0] of all the planes. 


The video processor selection for the first plane is tested with 
the following steps. 


E Select the first plane and deselect the other planes. 
2. 


Using one processor-to- bitmap Z-mode command, write a 1 
to point [0,0] of all the planes. This operation affects 

only the first plane because it vas the only plane 
selected. 


3. Using one bitmap-to- processor Z-mode command, read point 
[0,0] from all planes. 


4. Compare the results. Point [0 35 of the first plane 
should be 3 1, and the remaining point for the other 
planes should be a 0. 


Point [0,0] is again initialized for all the planes. The sequence 
performed for the first plane is repeated for each of the 
remaining planes, but references to the first plane are replaced 
by those for the plane being tested. 


5-10 


Diagnostics 


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5.5.1.8 Bitmap Memory Test — This test verifies the hardware 
related to the bitmap memory for all the planes. The test consists 
of three sections: data path and chip selection, data, and 
addressing. The data path and chip selection section verifies the 
data path to the bitmap memory and chip selection. Using a 
processor-to-bitnap X-mode command, a set of 32-bit patterns are 
written to point [0,0] through point [31,0] for all planes. Using 
a series of bitmap-to-processor X-~mode commands, the pattern is 
read from the first plane and compared to the pattern, and read 
from the second plane and compared to the pattern. This continues 
until every plane is read and compared. The patterns include the 
following. 


55555555H 
AAAAAAAAH 
333253358 
OFOFOFOFH 
OOFFOOFFH 
OOOOFFFFH 
87654321H 


The data section verifies that all bits in all planes of bitmap 
memory can be set and cleared correctly. Using one scroll fill 
command, a 55H type pattern is written to each address of bitmap 
memory for all planes. Using a series of bitmap-to-processor 
X commands, the pattern is read from each address of the first 
plane and compared, and read from each address of the second plane 
and compared. This continues until every address of every plane is 
read and compared. Using the scroll fill command, an AAH-type 
pattern is written to each address of bitmap memory for all 
planes. Using the same series of bitmap-to-processor X commands, 
the pattern is read from each address of the first plane and 
compared, and read from each address of the second plane and 
compared. This continues until every address of every plane is 
read and compared. 


The address section verifies the bitmap memory addressing. Using 
the processor-to~bitmap 2 command, a set of 32-bit patterns are 
written into a set of bitmap memory addresses for all planes. 
Using a rasterop function, each plane is complemented. Using the 
bitmap-to-processor X command, the pattern is read from the set of 
bitmap memory addresses for the first plane and compared to the 
32-bit complemented pattern set. The remaining plane reads the 
complemented values in exactly the same way. The address pattern 
is a floating 0 and floating 1. It is listed from the lowest value 
to the highest value in Table 5~4. 


Diagnostics 


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Address 


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3FBFCH 


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3FEFC 
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3FFEC 
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66666666 
777777778 
88888888 
99999999 
AAAAAAAAH 
BBBBBBBBH 
CCCCCCCCH 
DDDDDDDDH 
EEEEEEEEH 
FFFFFFFFH 
OO000000H 
11111111 
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55555555H 
66666666H 
777777778 
88888888H 
99999999H 

AH 


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88888888 
777777778 
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585 
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99999999H 
88888888H 
777777774 
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55555555H 
44444444H 
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11111111 
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Diagnostics 


ß GR 


ee a Right Scroll Test — This test verifies the scrolling 
logic in the video processors, and the timing logic associated 
with the video processors, memory, and the address processor. To 
test this function a scroll region will be established and filled 
with a known color with a rasterop function. The scroll boundaries 
must be on a nibble boundary to use the barrel shifter in the 
video processor to the fullest. The scroll function causes the 
video processors to scroll the region, exactly half the distance 
of the region. In order to test the right scroll function fully, 
the maximum value of 15 is used. A right scroll of 15 pixels 
actually develops into a scroll of 16 pixels in the bitmap. 
Therefore, the scroll region is 32 pixels wide, with the first 
half filled with AAAAs and the second half filled with 5555s. The 
horizontal scroll registers is set up to: 


Scroll K min. = 4 

Scroll X max. = scroll X min. + 8 
Scroll Y min. = 0 

Scroll Y max. = scroll Y min. + 32 
(Video processor) scroll constant = 3 


After the scroll function is performed, the bitmap reads back from 
each plane, and verifies that both the scroll fill color is in the 
left half of the block and the old left half has moved to the 
right half of the block. A different value of the scroll fill 
color is used in each video processor (the value is the same as 
the video processor's logical number: 1, 2, 3, etc.). In addition, 
the area just outside the scrolling region is checked to verify 
that the scroll edges are correct. Figure 5-2 illustrates the 
changes of the test. 


PLANE 1 (BEFORE) PLANE 2 (BEFORE) 


AAAAAS5555 | 
55 


AAAAASS 
AAAAASS 


5 
5 


55 
5 


5 | AAAAAS55555 | 


PLANE 1 (AFTER) PLANE 2 (AFTER) 


22222 AA AAA 


2 222 2 A A A A A 


enn ss eee, 


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Figure 5-2 Right Scroll Test Changes 


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Diagnos tics 


VVV 


5. 5.1.10 Down-Scroll Test —— Down-scrolling is implemented by 
forcing all the video processors to scroll up all data outside the 
scroll region, and fill the top of the area within the scroll 
region with the fill color for the same number of scan lines as 
the distance scrolled down. 


tion, an area of memory is filled with a known 
own—-scroll is performed. Reading the bitmaps 
the 1 is properly performed. In addition, a 
cted of the system's ability to scroll some bitmaps 
lling others. This also tests ee scroll enable 

resides on the I/D bus. The vertical scroll 


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The ee to be scroll is filled with a known pattern of AAAAS 
(see Figure 5-3), while the rest of the bitmap is filled with a 
pattern of zeros. The sc: 1 fill register of each video processor 
is loaded with the logical ascending order of bit patterns from 
1111 to 8888. After the scroll is complete, the bitmap region 
verifies that it: 


8 Scrolled, if the plane was selected 


® Filled, 


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0 Region exterior for proper edge masking by the address 
processor and video processor. 


2 DMA Test — The FIFO and DMA operations are checked by 
erforming a processor-to-bitmap transfer of 65 words immediately 
Ollowed by a bitmap<-to-processor transfer of 65 words. After this 
e data sent is 5 bisa the data received. To verify the 


2 


interrupts, the test is "interrupt driven." 


5.1.11 
ir 


Presence of the 


1.12 Video Synchronizat 
is v itoring the sync detect 


zontal sync pulse 


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Diagnostics 


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PLANE 2 (BEFORE) 


genuine OCEAN 


AAAAAAAAAA 
A A A H A HA A HA A HA 


Naehe uin umme hui ele 


A A A A A A HA A HA A 
A AA A A HA A A A A 


NET (AFTER), PLANE 2 (AFTER), 
OLL DISABLED aioe L - ENABLED 


AAAAAAAAAA 
AA A A A A HA A A HA 


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Figure 5-3 Down-Scroll Test Changes 


5.5.1.13 Video Signal Level Test — This test checks the data path 
from the Q22-Bus to the complementary output of the video DACs. It 
also checks the accuracy of the video DACs to within 2 LSBs. The 
resolution of the comparators determines the final delta value 
that is blasted into the VCBO2 ROM for the final product. This 
means the two LSBs of each color map register address may, or may 
not, be checked by the self-test. 


During this test the color map register's red, green, and blue 
entries are loaded 3 times; once for each group of 9 lines. This 
test requires 27 frames of displayed screen data to complete. Nine 
horizontal lines are drawn on the screen, as listed in Table 5~5. 


Table 5-5 Horizontal Scan Line Pixel Values 


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Line Value 


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20H 8~plane o 
40H 8-plane only 
80H 8 — Plane only 


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Diagnostics 


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To test the green set of pixel values, the color map locations are 
loaded with the patterns listed in Table 5-6. 


ae detection, the preceding test must be 
jing. The remaining color map locations are 
5 background pattern. 


To ensure address fa 
completed before contin 
loaded with the followir 


ine denten de ebenes ＋W＋＋＋＋＋＋＋＋＋W＋＋＋＋＋＋＋＋V—— 


CMR Red MR Gre CMR Blue Expected Results: 
Value Value Value B-GT-R G~GT-B R-GT-G 


＋＋＋＋＋P— 


B- D B+DV DBH 1 1 0 


esse VVV 


To test the red set of pixel values, the color map locations are 
loaded with the patterns listed in T. 


lt detection, 
ing. The remaini 
1g background pat 


the preceding test must be 


ng color map locations are 
tern. 


To ensure address fau 
completed before continu 
loaded with the followir 


VVV 


CMR Red f Green MR Blue Expected Results 
Value Value Value B-GT-R G~-GT-B ROT 


ues, the color map locations are 


To test the blue set of p al C 
R 1 18 Table 5-8. 


loaded wi 


To ensure address fault detection, the preceding test must be 
complete ed before continuing. The remaining color map locations are 
loaded with the following background pattern. 


= 
rr 


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CMR Green CMR Blue Expected Res egies: 
Value Value B~GT-R G-GT~B R-GT-G 


GDV DBH GDV 1 1 0 


The DV, or delta value, is 10. 
Le en _DUART Test ~~ Using local loopback operating mo 


de, 
‘les the DUART in face by transmitting and receiving a 
it patterns at 4800 baud. The patterns include: 


To verify the interrupts, the test is “interrupt-driven." 


Diagnostics 


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_Table 5-6 Color Har Ragister Green Pixel Value Test 
CMR CMR Red CMR Green CMR Blue Expected Neale 
Address Value Value Value B-GT- R _G-GT- 5 R-GT-G 
G+DV 55H 
1 GDV AAH 
2 G+DV 33H 
4 GDV CCH 
8 GDV OFH 
1 
2 


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LOH GDV FOH 
20H GDV FFH-DV 
40H G+DV OOH+DV 
80H G+DV EFH 


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Table 3 Color Map Register Red Pixel Value Test 


CMR CMR Red CHR Green CMR Blue Expected Neu 
Address Value Value B-GT~ R I R-GT-G 


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CMR CMR Red CMR Green CMR Blue ebe e 

Address Value Value Value 3 * _G~GT~B R~GT-G 
BD B+DV 55H 
B-DV B+DV AAH 
B-DV B+DV 33H 
B~DV B+DV CCH 

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Diagnosti 


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n anual Input Devices Test — This test verifies the 
manual input devices connected to the DUART's ports. The test 
sends the “test command" (FDH) to the keyboard port to invoke its 
self-test, and waits one second for a response from the device. If 
the device responds with four bytes, and the third byte is zero, 
the test continues. If the device responds with one byte of value 
FDH, the test logs a hard error and continues. Otherwise, the test 
interprets a device control to the KA630 
ROM. 


rh 


E 
fatal error, and returns 


The test sends the "test 5 (T ASCII) to the other port. If 
the keyboard port received four bytes, and the 5 ce responds 
with four bytes, and che third byte is less than 20H (or the 

j i to respond), t test continues. If the . port 
12 byte of valu 
u 


@ ir 
1 PDE and the device responds with one 
e T the 


he 
received e ; 
test logs a hard error and continues. 


byte of val 


NOTE 
The device connected to the mouse/tablet 
port is considered an optional device. 
This means that in the customer's 
environment, a mouse or tablet that is 
improperly connected may not be reported 
as an error. 


5.5. 1. 16 Calling Sequence -~ 


Power-Up-Initiated 


; Set up the console page, stack, bitmap (used as work buffer), 
; diagnostic scratch pages. 


MOVW #°X3F, @#QDSS$GW_IOCSR 


m 


; Find base address of executable code in "DIAGO * 111 
| 1 return in Rn. 


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5-18 


Diagnostics 


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Software-Initiated 
; Suggested literal values 


SISTSK IPLMAX = “X17 
SISTSK IPLMIN = “X2 
SIS TSK DVC VEC = 140 
818 TSK BUSADP = “X200 
SISTS K FNCCODE — 1 


Maximum interrupt priority level 
Minimum interrupt priority level 
Device vector offset 

Bus adapter offset 

Function code 


‘Se %“¢ Se Be Se 


; Set up the console page, stack, bitmap (used as work buffer), 
; diagnostic scratch pages, change to kernel mode. 


ile 


Map VCBO02 ROM 


; 

MOVW #°X3F, @#ODSSSGW_IOCSR 
; Find base address of executable code in "DIAGO " file 
; and return in Rn. 
; Pass parameters. Note that some physical addresses can easily 
; be obtained, but most Q22-Bus addresses and virtual addresses 
* cannot. 


Branch if error 

Maximum interrupt priority level 
Minimum interrupt priority level 
Bitmap Q22-Bus base address 
Device vector offset 

Bus adapter offset 

System control block base address 
Console page address 

Function code (should be 1) 


BLBC RO, ERROR 

PUSHL #SISTS$K_IPLMAX 
PUSHL #SISTS$K_IPLMIN 
PUSHL #SIST$K_BITMAPQBUS 
PUSHL #SISTS$K_DVCVEC 
PUSHL #SISTS$K_BUSADP 
PUSHL SISTS$L_SCBB 

PUSHL SIST$L_CPADR 
PUSHL #SIST$K_FNCCODE 


Se £2, Ge Se = Be = Be SS 


* Pass control to self-test. 

CALLS #8, (Rn) 

Seen Console 1/0 

5.5.2.1 Put Character Poll -- This routine is called to determine 
if a character can be displayed. No parameters are passed to the 
routine. If a character can be displayed, the routine returns RO 
with bit 0O set to 1. If a character cannot be displayed, the 
routine returns RO with bit O cleared to 0. 

Calling Sequence 


: Rll contains the base address of the console page. 


Put a character? 
No, wait 


JSB @CPSA_PUTCHRPOLL (R11) 
BLBC RO, LOOP 


Se Se 


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5.5.2.2 Put Character -- This routine is called to di 
character. Rl is passed containing the "zero extended" ASCII 
of the character to be displayed. If the character is dis 
suc ccessfully, the routine returns RO with bit 0 set to 1 
character is displayed unsuccessfully, the routine returns 
bit O cleared to 0. 


NOTE 
The routine should be used with the put 
character poll routine. It uses the US 
ASCII font table and multinational font 
table in the KA630 RO 


Calling Sequence 


; Rll contains the base address of the console page. 


Put à character? 

No, wait 

Pass ASCII value of "A" 
it the character 

ch if error 


88 @CPSA_PUTCHRPOLL (R11) 
BLBC RO, LOOP 

OVZBL AAA, RI 

JSB @CPSA_PUTCHR (R11) 
BLBC RO, ERROR 


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2 


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5.2.3 Get Character -~ This re is called to determine if a 
character has been received, and if so, return the character. No 
parameters are passed. If a character is available, the routine 
returns Rl with the “zero extended" ASCII value of the character, 
and RO with bit 0 set to 1. If a character is not available, the 
routine returns Rl with arbitrary data and RO is cleared to 0. If 
the keyboard code is a shift code like "control," "shift," and 
"lock," or introducer code like “compose character," the routine 
returns RO with bit O cleared to 0. 


NOTE 
Get character calls the keycode 
translate character routine. There are 
no provisions for timeouts. 


ale 


Calling Sequence 
; Rll contains the base address of the console page. 


LOOPIL: 

JSB @CPSA_GETCHR(R11) 
BLBC RO, LOOPI 

PUSHL RI 


Get a character? 
No, wait 
Yes, store it 


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R 
PO PL. R1 
@ 
i 


aCPSA_ _PUTCHRPOLL (R11) 
JE Ney ae 
JSB 


Echo the Character 
BLB C i 


Branch if error 


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2 ct 
8 
. 
as 
iv 
2 
a 


5-20 


_Diagnostics 


5.5.2.4 Enable VCB02 ROM and Console Bus Reset — This routine is 
called to initialize the hardware for console output after a bus 
reset. Refer to Table 5-9. If the VCBO2 is initialized 
successfully, the routine returns RO with bit 0 set to 1. If the 
VCBO02 is initialized unsuccessfully, the routine returns RO with 
bit O cleared to 0. The software service routine is called if 
initialized. 


NOTE 
This is not provided by the VCBO2 ROM. 
The routine calls N reset. 
Calling Sequence 
; Rll contains the base address of the console page. 


JSB @CPSA_ENBUSRESET (R11) F Enable ROM and bus reset 
BLBC RO, ERROR : Branch if error 


fabre 9 "9 Bus Reset and 9 Defaults 


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. e OE NDIA OR 


Default ‘Setting 
9 page 
Software service Called if baal Zero 


Address e 
Scroll X min. 8 * en . i 
Scroll X max. 8 * (Character column max. + 1) 
Scroll Y min. * (Character row min.) 
Scroll Y max. * (Character row max. + 1) 
Clip X min. (Character column min.) 
Clip X max. (Character column max. + 1) 
Clip x min. (Character row min.) 
Clip Y max. (Character row max. + 1) 
Fast source 1 Dx 
Fast source 1 DY 
Source 1 X origin 
Source 1 x origin 
Fast destination Dx 
Fast destination DY 
1 destination Dx 
Slow des tination D LS 


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* * 


** 
* 


Lf ae 


Ww 


Diagnos Stics 


ANN iia Oita i 


Table 5-9 Bus 


VVV 


5222 


Reset and Reset Defaults (Cont) 


Default Setting 
Video 588 cessor 

Reso Meier. mode 0 

Bus width CH 
scroll constant 60H 
Video processor O plane address 0 
Video processor 1 plane address 1 
Video processor 2 plane address 2 
Video processor 3 plane address 8 
Video processor 4 plane address A 
Video processor 5 plane address 5 
Video processor 6 plane address 6 
Video processor 7 plane address 1 
Mask 1 FFFFH 
Source FFFFH 
Fill 0 
Left scroll boundary 0 
Right scroll boundary FFFFH 
Background color 0 
Foreground color FPFFH 
CSR 0 28H 
CSR 1 4 

CSR 2 0 

CSR 4 24H 
CSR 5 8H 
CSR 6 1 
Entry Red Green Blue 

0 0 0 0 

i 255 200 255 

2 0 0 0 

: 255 255 295 

4A 0 0 0 

5 255 209 255 


Diagnostics 


Table 5-9 Bus Reset and Reset Defaults (Cont) 


Default Setting 


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DUART 


e SOUR EOS EOE ES SHER ESP BUS OS SEO EHR RGSS RRO RED 


Channel A 


Character length 8 

Parity Off 

Baud rate 4800 

Transmitter Reset and enabled 
Receiver Reset and enabled 


Channel B 


Character length 8 

Parity Odd 

Baud rate 4800 

Transmitter Reset and enabled 
Receiver Reset and enabled 


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N Enable VCBO2 ROM and Console Reset — This routine is 
called to initialize the hardware for console output after a 
reset. Refer to Table 5-9. If the VCBO02 is initialized 
successfully, the routine returns RO with bit 0 set to 1. If the 
VCBO02 is initialized unsuccessfully, the routine returns RO with 
bit O cleared to 0. The software service routine is called if 
initialized. 


NOTE 
This is not provided by the VCB02 ROM. 
The routine calls N reset. 


Calling Sequence 
; Rll contains the base address of the console page. 


JSB @CPSA_ENRESET (R11) ; Enable ROM and reset 
BLBC RO, ERROR : Branch if error 


Me De 28 N Reset -- This routine is called by the reset, bus 
reset, and power-up to initialize the hardware for console output. 
Rl is passed containing a function code, where: 


= Reset 
Bus reset 
= Power-up self-test reset. 


25 


Diagnostics 


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Refer to Tables 5-9 and 5-10. If the VCBO2 is initialized 
successfully, the routine returns RO with bit 0 set to 1. If the 
VCBO02 is initialized unsuccessfully, the routine returns RO with 
bit 0 cleared to 0. 


Calling Sequence 
; Rll contains the base address of the console page. 
MOVL #RESETSK FNCCODE, RI Pass function code 


= 7 
JSB @CPSA_NRESET (R11) ; Reset console 
BLBC RO, ERROR F Branch if error 


Table 10 W “Up Defauits 


1 See n 


Console Page Diagnostics 

e row Minimum row 
Minimum row 0 

Maximum row 56 

Current column Minimum column 
Minimum column 0 

Maximum column 127 

. service 0 


Address Processor 


Request enable 

Interrupt enable 

I/D data FIFO cleared 

Command Issued cancel command 

Mode 

Scroll 

scroll 
] 
1 


oo a 


X min. 
X max. 
¥Y min. 
Y max. 


0 

0 

1 
Scroll 0 
Scroll 8 
Pause 0 
offset 0 
1 scroll constant 2 
Pending x index 0 
Pending Y index 0 
New X index 0 
New 1 index 0 
Old X index 0 
Old * index 0 
CIip 0 
Clip 1 
Clip min. 0 
Clip Y max. 8 
Fast source 1 DX 8 
Fast source 1 DY ] 


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* 


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Mäx. 


Ao eK 


Diagnostics 


Table 5-10 


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Power-Up Defaults (Cont) 


Default 


bomann eke 


Setting 


sinless e ea a gUNOIN Banga 


Source 1 X origin 
Source 1 Y origin 
Destination X origin 


destination 
destination 
destination 
destination 
scale 
scale 


Fast 
Fast 
Slow 
Slow 
Fast 
Slow 


DX 
DY 
DX 
DY 


0 
0 
0 
Destination Y origin 0 
8 
0 
0 
1 


Source 
Source 
Source 


2 X origin 
2 X origin 
2 height and width 


count 0 
count 1 
count 2 
count 3 


scan 
scan 
scan 
scan 
scan 
limit 
limit 
scan 
scan 
scan 
scan 
scan 


count 
count 
count 
count 
count 
scan count 
Xx scan count 
Sync phase 


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Video Processor 


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— e ß ORT HD SSS SHON AFOSR HOR ASS SSIES SH 


Resolution mode 
Bus width 

Scroll constant 
Video processor 


SE HERRON IRIE 


configuration 


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plane address 


Video 

Video 

Video 

Video 

Video 

Video 

Video 

Mask 1 
Source 
Fill 


processor 
processor 
processor 
processor 
processor 
processor 
processor 


plane 
plane 
plane 
plane 
plane 
plane 
plane 


aug GR UF) de Gs AP e CO 


address 
address 
address 
address 
address 
address 
address 


Left scroll boundary 
Right scroll boundary 
Background color 
Foreground color 

CSR 0 


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P 


FPFFFH 
0 
FFFFH 
0 
FFFFH 
28H 


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Diagnostics 


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Table 5-10 Power-Up Defaults (Cont) 


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Setting 


T 


oO 


R 
R 
R 


ip 


8 
2 


= 
= 


a 


2 
— 


„„ 


* 
Ue 
a 


Bitmap Memory 


All zeros. Only the first plane is used. 


Color Map 


Entry Red Green 


ae apes ENC SSSA OSES OSIRIS SS SS NON 


nt 


54 
255 


DUART 


Channel A 


Character length 8 

Parity rr 

Baud rate 4800 

Transmitter Reset and enabled 
Receiver Reset and enabled 


Channel B 


Character length 8 

Parity Odd 

Baud rate 4800 

Transmitter Reset and enabled 
Receiver Reset and enabled 


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828 


. e T if 


Table 5-10 Power-Up Defaults (Cont) 
Default Setting 
Keyboard 

Main array keys Down 
Numeric keypad keys Down 

Delete key Down 
Return, tab keys Down 

Lock, compose keys Down 

Shift, control keys Down/up 
Horizontal cursor keys Down 
Vertical cursor keys Down 

Edit keys Down 
Function keys Down 


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5.5.2.7 Keyboard Put Character — This routine is called to send a 
character to the keyboard, which responds with functions such as 
illuminating the keyboard LEDs and sounding the bell. RO is passed 
containing the base address of a string terminated with a zero 
byte. If the character is sent to the keyboard successfully, the 
routine returns RO with bit 0 set to 1. If the character is sent 
to the keyboard unsuccessfully, the routine returns RO with bit 0 
cleared to 0. 


Calling Sequence 


> Rll contains the base address of the console page. 

Pass string (sound bell) 
Send to keyboard 

Branch if error 


MOVAB BELLST, RO 
JSB @CPSA_KBDPUTCHR (R11) 
BLBC RO, ERROR 


oy 


se ee we 


BELLST: .BYTE “XA7, 0 : String to sound bell 


5.5.2.8 Software Service -- This routine is used to provide 
extended software functions to higher level software applications, 
such as operating systems. When the entry is zero, no additional 
function is performed. When the entry is nonzero, it is expected 
to contain an address of a subroutine. The subroutine is called 
with Rl containing a function code. The higher level software 
application is responsible for providing the address of the 
routine. Currently, function code 1 has been defined as saving the 
state of the alternate console device. 


Diagnostics 


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Calling Sequence 
; Rli contains the base address of the console page. 


Routine? 


TSTL @CPSA_SWSERV(R11) n 
Branch if no 
f 


C 
BEQL OKIP 
MOVL | 


1 Pass function code 
JS6B @c 


Save state 


N VCB02 1/0 Space CSR Address — This entry contains the 
address of the VCB02 I/O space CSR address. If the software is 
executed in physical, the address should be one of the following. 


a? 


gr, 
See 


(secondary alternate console) 


geet 


2 ty 


HO) POON & ND 


oo 
nie 
wens 


4 


es 
oo 
eee 


= El ped 
2S 


Peat . 8 8 e „ 


N N N NO 


tay Pay ry ry 


NOTE 
This is not provided by the VCB02 RC 


5.5. 2.10 U. 8. Font ane ~~ This entry contains the base address 
of the character font table for displaying U.S. characters. The 
table is used by the put 25 aracter routine. 


NOTE 
This is not provided by the VCBO2 ROM. 


1Itinational Font Table -~ This entry contains the base 
ress of the character font table for displaying multinational 
aracters. The table is used by the put character routine. 


7 NOTE 
This is not provided by the VCB02 ROM. 


5.5. 2.12 Keycode Translate Character -- This entry contains the 
sadness of a routine responsible for A N “the "shift," "shift 
lock," and "control" key state, and for properly translating the 
keyboard codes to the correct character representation. It is used 
by the get character routine. R2 is passed with the keycode value. 


NOTE 
This is not provided by the VCB02 ROM. 


528 


Diagnos tics 


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Calling Sequence 
: Rll contains the base address of the console page. 


MOVZBL #KEYCODESK, R2 ; Pass keycode 
JSB @CPSA_ KBDX (R11) ; Translate keycode 


5, 5, 2.13 Row and Column Parameters — The current character row 
and column contain the position of the next character to be 
displayed in character units. The minimum character row and column 
contain the minimum values in character units. The maximum 
character row and column contain the maximum values in character 
units. The minimum and maximum values are used to modify the 
console window size. 


ns the 
are is 
address, such as 


| VCBO2 N ry Space CSR Base — This entry contai 
se . of the VCBO2 memory space CSRs. If the softe 
sxecuted in physical mode, this is a physical 
303FO0000H. 


NOTE 
This is not provided by the VCB02 ROM. 


jwoeee lo ait 1 Millisecond — The wait 1 millisecond routine is 
used to create a delay of 1 millisecond. No parame eters are passed. 
It is recommended that future implementations of this routine use 
the stack, and specifically not use any gener ral-purpose registers. 
For example: 


CPSWAITMS: 


Set counter 
Delay loop 
Clean up stack 
Exit 


MOVL IMS SK, -( 
LOOP: SOBGTR (8 
TS TL (SP)+ 

RSB 


SP) 
P), LOOP 


&- Ss Se Se 


NOTE 
This is not provided by the VCBO2 ROM. 


Calling Sequence 
; Rll contains the base address of the Console Page. 


JSB @CPSA_WALITMS (R11) ; Delay 1 millisecond 


APPENDIX A 
222 BUS SPECIFICATION 


ß AE ERNIE HOISTING 


A. 1 GENERAL DESCRIPTION 

The Q22-Bus, also known as the extended LSI-~-11 Bus, is the low-end 
member of Digital's bus family. All of Digital's microcomputers, 
such as the MicroVAX I, MicroVAX II, and MicroPDP-1l, use the 
QO22-Bus. 

The Q22-Bus consists of 42 bidirectional and 2 unidirectional 
Signal lines. These form the lines along which the processor, 
memory, and I/O devices communicate with each other. 


. data, and control information are sent along these 
7 N n 1 2 2 
ignal lines, some of which contain time-multiplexed information. 
the lines are divided as follows. 


pads 


0 Sixteen multiplexed data/ address lines — BDAL<15:00> 


e Two multiplexed address/parity lines — BDAL<17:16> 
% Four extended address lines — BDAL<21:18> 


. Six data transfer control lines — BBS7, BDIN, BDOUT, 
BRPLY, BSYNC, BWTBT 


® Six system control lines -~ BHALT, BREF, BEVNT, BINIT, 
BDCOK, BPOK 

* Ten interrupt control and direct memory access control 
lines -- BIAKO, BIAKI, BIRQ4, BIRQ5, BIRQ6, BIRQ7, BDMGO, 
BDMR, BSACK, BDMGI 


In addition, a number of power, ground, and space lines are 
defined for the bus. Refer to Table A-1 for a detailed description 
of these lines. 


The discussion in this Appendix applies to the general 22-bit 
physical address capability. All modules used with the KA630-A CPU 
module must use 22-bit addressing. 


Most Q22~Bus signals are bidirectional and use terminations for a 
negated (high) signal level. Devices connect to these lines via 
high-impedance bus receivers and open collector drivers. The 
asserted state is produced when a bus driver asserts the line low. 


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Q22-Bus Specification 


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Table 1 Signal Assignments 


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BDALO AU2 
BDALI A 
BDAL2 BE2 
BDAL3 B 
BDAL4 3 
BDALS Ba 
BDAL6 BRK 2 
BDRL7 BL 2 
BDAL8 BM 2 
BDALY BN2 
BDAL1O BP2 
BDAL11 

BDAL12 BS2 


IALL5 BV2 
IAL16 ACI] 
DAL1?7 AD1 
BDAL18 BCl 

BDAL19 BD1 
1 BE 
5 BFI 


CONTROL 


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Data eal 


BDOUT AE2 
BRPLY AF2 
BDIN AH2 
BSYNC 02 
BWTBT AK2 
BBS7 AP2 


Interrupt Control 


BIRQ7 BPI 
BIRQ6 ABL 
BIRQ5 AAI 
BIRQ4 AL2 
BIAKO AN2 
BIAKI AM2 


DMA Control 
BDMR AN 
BSACK BNI 


BDMGO AS2 
BMDGI AR2 


Q22- ‘Bus Specification 


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Table A~1 eae . Wan 


Pin ‘Assignment 


System Control 


+5B (battery) or AS1 
+12B (battery) 
+12B 881 


GND AT 1 
GND BC 2 
GND B01 
GND BM1 
e BT 1 


neonate 


er PRES 
sSparel AE 1 
SSpare3 AH] 
SSpare8 BHI 
SsSpare2 AF1 
MSpareA AK1 
MSpareB ALL 
MSpareB BKI 
MSpareB BLI 
PSparel AUL 
Sp. BUL 


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Q22-Bus Specific cation 


isaac 


A.3 DATA TRANSFER BUS CYCLES 
Data transfer bus cycles are listed and defined in Table A-2. 


These bus cycles, executed by bus master devices, transfer 32-bit 
words or 8-bit bytes to or from slave devices. In block mode, 
multiple words may be transferred to 5 word addresses, 
starting from a single bus address. The bus signals listed in 
Table A-3 are used in the data transfer operations described in 
Table A-2. 


one 


1 A— Data e F 


Bus Cycle Function (with Rewpect 
Mnemonic to the Bus Master) 
DATI Data word Read 
DATO Data word Write 
DATOB Data byte output Write-byte 

DATIO Data word input/output Read~modify-write 
DATIOB Data word input/byte output Read-modify-write byte 
DATBI Data block input Read block 

DATBO Data block output Write block 


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Table A ~3 Bus Signals 3 mere . 


Mnemonic Description. Function 


BDAL (21: 000 L 22 8 lines BDAL<15 -00> L are used for 
word and byte transfers. 
BDAL<17:16> L are used for 
extended addressing, 
memory parity error (16), 
and memory parity error 
enable (17), functions. 
BDAL<21:18> L are used for 
extended addressing beyond 
256 Kbytes. 


BSYNC L. Bus cycle control Indicates bus transaction 
in progress. 


BDIN L Data input indicator Strobe signals. 


BDOUT L Data output indicator Strobe signals. 


BRPLY L Slave's acknowledge of Strobe signals. 
bus cycle 


BWTBT L Write/byte control Control signals. 


BBS? 1/O device select Indicates address is in 
the 170 page. 


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These 


DATBO. 


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Bus Cycle Protocol 


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170 
do 
applications 


as DMA buffers, 


DATI 
operation. 
consists 
transfer 
BDIN I. 


— The 
of 
port 

100 


(the upper 4 K address space). 
oe respond to addresses 


During 


Q22- ~Bus Specification 


Memory devices . 
in the I/O page; however, some system 
may permit memory to reside in the I/O page for use 
read-only memory bootstraps diagnostics, etc. 
DATI bus cycle, shown 
DATI, data is 
16-bit word transfe 
tion of the 
ns (minimum) 


in Figure A-l, is a read 
input to the bus master. Data 
rs over the bus. During the data 
DATI bus cycle, the bus master asserts 
after BSYNC L is asserted. The slave 


device responds to BDIN L active as follows. 


0 


Ass 


a 


— 


BUS MAS TE 
(PROCESSOR OR DEVICE) 


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CE MEMORY 
de Zi 00 1 


S DEVIC 


8 en E 
„ ASSERT BSYNC 


0 ASSERT BDIN L 


INPUT TRA 
‘DATA AND 
TING BDIN 


TERMINA 
‘i 


T 
NEGATE BSYNC 


Asserts 
timeout) 
before 


erts 


information 
(maximum) 


b 9 8 8 


BRPLY L. 
after 
BDAL bus 


Ons (minimum) 
receiving BDIN 
driver data bits 


avoid bus 
(maximum) 


(8 ns maximum to 
L, and 125 ns 
are valid. 


BDAL<21L00> L. with the addressed data and er 
0 ns (minimum) after receiving BDIN, and 
after assertion of BRPLY. 


ror 
2 


R SLAVE 
| (ME MORY OR DEV CE) 


TT 


WITH 


1 


1 THE r ADDRESS FROM 
LAND 


— 
DECO DE ADDRESS 
* STORE’ DEVICE SELECTED” 
OPERATION 
INPUT DATA, 
„ PLACE DATA ON BDAL < 15:00> L 
_--* ASSERT BRPLY L 
— 1 
AN SEER 
RESPOND 
NL neee, a 
OPERATION oe ETEO 


hat Oe Bh 


Figure A-l DATI Bus 


Cycle 


Q22~Bus Specification 


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When the bus master receives BRPLY L, it does the following 


® Waits at least 
data at BDAL< 
used for transmi 


00 ns deskew time and then accepts input 
000 L bus receivers. BDAL <17 
ing parity errors to the maste 


3 


® Negates BDIN L 200 ns (minimum) to 2 us (maximum) after 
BRPLY L goes active. 


The slave device responds to BDIN L negation by negating BRPLY L 
and removing read data from BDAL bus drivers. BRPLY L must be 
negated 100 ns (maximum) prior to removal of read data. The bus 
master responds to the negated BRPLY L by negating BSYNC L. 
Conditions for the next BSYNC L assertion are as follows. 


2 BSYNC L must remain negated for 200 ns (minimum). 


s BSYNC L t not become asserted within 300 ns of previous 
BRPLY L negation 


Figure A~2 shows DATI bus cycle timing. 


NOTE 

Continuous assertion of BSYNC L retains 
control "of the bus by the bus master, 
and the previously addressed slave 
device remains selected. This is done 
for DATIO(B) bus cycles where DATO or 
DATOB follows a DATI without BSYNC L 
negation and a second device addressing 
operation. Also, a slow slave device can 
hold off data transfers to itself by 
keeping BRPLY L asserted, which causes 
the master to keep BSYNC L asserted. 


DATO (B) ~~ DATO 
Data is trans 85 


B), shown in Fig 
1 ( 
from t! 


4 


ed in 32-bit words 


( , 1S a write operation. 
r K 
e bus master to the slave device. 
th i 
5 
r 


~3 K 

0) or 88-bit bytes (DATOB) 
The data transfer output 
fF a bus cycle when BWTBT I. 
ed by the bus master, or immediately following an 
rt of a DATIO(B' | € 


1e b 
can occu apes the addressing portion o 
has bee assert 
input transfer pa 


Gi 
155 
. 


8 data transfer portion of a DATO(B) bus cycle comprises a data 
setup and deskew time and a data hold and deskew time. 


the bus master 


During the data setup and deskew time, 
100 ns after 


cf 
data on BDAL<15:00> L at leas st 2r BSY asser 
BWTBT L remains negated for the length of the bus ‘cycle. I 
trans 358 is a byte trans fer, BWTBT L remains asserted. If 
the tput of a DATIOB, BWTBT L becomes asserted and lasts the 
dapat ion of the bus cycle. 


me PR or Wf 


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Q22-Bus Specification 


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TIMING AT SLAVE DEVICE 


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Figure A-2 DATI Bus Cycle Timing 


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During a byte transfer, BDAL<00> L selects the high or low byte. 
This occurs while in the addressing portion of the cycle. If 
asserted, the high byte (BDAL<15:08> L) is selected; otherwise, 
the low byte (BDAL<07:00> L) is selected. An asserted BDAL 16 L at 
this time forces a parity error to be written into memory if the 
memory is a parity-type memory. BDAL 17 L is not used for write 
operations. The bus master asserts BDOUT L at least 100 ns after 
BDAL and BDWTBT L. bus drivers are stable. The slave device 
responds by asserting BRPLY L within 10 us to avoid bus timeout. 
This completes the data setup and deskew time. 


During the data hold and deskew time, the bus master receives 
BRPLY L and negates BDOUT L, which must remain asserted for at 
least 150 ns from the receipt of BRPLY L before being negated by 
the bus master. BDAL<17:00> L bus drivers remain asserted for at 
least 100 ns after BDOUT L negation. The bus master then negates 
BDAL inputs. 


1 
h 


The 


During this time, the slave device senses BDOUT L negation. 
he bus 


data is accepted and the slave device negates BRPLY L. Th 
master responds by negating BSYNC L. However, the processor does 
not negate BSYNC L for at least 175 ns after negating BDOUT L. 
This completes the DATO(B) bus cycle. Before the next cycle, BSYNC 
L must remain unasserted for at least 200 ns. Figure A-4 shows 
DATO(B) bus cycle timing. 


DAITO(B) — The protocol for a DATIO(B) bus cycle is identical to 
the addressing and data transfer portions of the DATI and DATO (B) 
bus cycles, and is shown in Figure A-5. After addressing the 
device, a DATI cycle is performed as explained earlier; however, 
BSYNC L is not negated. BSYNC L remains active for an output word 
or byte transfer [DATO(B)]. The bus master maintains at least 200 
ns between BRPLY L negation during the DATI cycle and BDOUT L 
assertion. The cycle is terminated when the bus master negates 
BSYNC L, as described for DATO(B). Figure A-6 illustrates DATIO(B) 
bus cycle timing. 


QO22-Bus Specification 


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A-12 


Q22-Bus Specification 


aN 


BUS MASTER SLAVE 
(PROCESSOR OR DEVICE) (MEMORY OR DEVICE) 


ADDRESS DEVICE/MEMORY 
® ASSERT BDAL <21:00> L WITH 
ADDRESS 
@ ASSERT 8887 
ADDRESS 18 


F THE 
5 f 
» ASSERT BSY 


HE 1/0 PAGE 


N 
L 


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Hy 
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DECODE ADDRESS 
„ STORE “DEVICE SELECTED” 
_ OPERATION 
te 
REQUEST DATA 
„ REMOVE THE ADDRESS FROM 
BDAL <21:00> L 
„ ASSERT BDINL — eae 
> INPUT DATA 
® PLACE DATA ON BDAL <15:00> L 
„ ASSERT BRPLY L 
ti 
TERMINATE INPUT TRANSFER = 
„ ACCEPT DATA AND RESPOND BY 
TERMINATING BDIN L 


COMPLETE INPUT TRANSFER 
„ REMOVE DATA 
„ NEGATE BRPLY L 
ro 
| 9 — 

OUTPUT DATA 

® PLACE OUTPUT DATA ON BDAL & 15:00 L 

„ (ASSERT BWTBT L IF AN OUTPUT 

BYTE TRANSFER) 
„ ASSERT BDOUT L 


TAKE DATA 


@ RECEIVE DATA FROM BDAL LINES 
® ASSERT BRPLY I 


TERMINATE OUTPUT TRANSFER 
® REMOVE DATA FROM BDAL LINES 
e NEGATE BDOUTL 


OPERATION COMPLETED 
® NEGATE BRPLY I 


TERMINATE BUS CYCLE 
@ NEGATE BSYNCL 
(AND BWTBT LIF IN 
A DATIOB BUS CYCLE) 


MR ee 


Figure A-5 DATIO or DATIOB Bus Cycle 


Q22-Bus Specification 


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Figure A-6 DATIO or DATIOB Bus Cycle Timing 


Q22~Bus Specification 


A. 4 DIRECT MEMORY ACCESS 

The direct memory access (DMA) capability allows direct data 
transfer between I/O devices and memory. This is useful when using 
mass storage devices (for example, disks) that move large blocks 
of data to and from memory. A DMA device needs to know only the 
starting address in memory, the starting address in mass storage, 
the length of the transfer, and whether the operation is read or 
write. When this information is available, the DMA device can 
transfer data directly to or from memory. Since most DMA devices 
must perform data transfers in rapid succession or lose data, DMA 
devices are provided the highest priority. 


DMA is accomplished after the processor (normally bus master) has 
passed bus mastership to the highest-priority DMA device that is 
requesting the bus. The processor arbitrates all requests and 
grants the bus to the DMA device electrically closest to it. A DMA 
device remains bus master until it relinquishes its mastership. 
The following control signals are used during bus arbitration. 


BDMGI L DMA grant input 

BDMGO L DMA grant output 

BDMR L DMA request line 

BSACK L Bus grant acknowledge 
A.4.1 DMA Protocol 


A DMA transaction can be divided into three phases: 


1. Bus mastership acquisition phase 
2. Data transfer phase 
3. Bus mastership relinquishment phase. 


During the bus mastership acquisition phase, a DMA device requests 
the bus by asserting BDMR L. The processor arbitrates the request 
and initiates the transfer of bus mastership by asserting BDMGO L. 


The maximum time between BDMR L assertion and BDMGO L assertion is 
DMA latency. This time is processor-dependent. BDMGO L/BDMGI L is 
one signal that is daisy-chained through each module in the 
backplane. It is driven out of the processor on the BDMGO L pin, 
enters each module on the BDMGI L pin, and exits on the BDMGO L 
pin. This signal passes through the modules in descending order of 
priority until it is stopped by the requesting device. The 
requesting device blocks the output of BMDGO L and asserts BSACK 
L. If BDMR L is continuously asserted, the bus hangs. 


During the data transfer phase, the DMA device continues asserting 
BSACK L. The actual data transfer is performed as described 
earlier. 


The DMA device can assert BSYNC L for a data transfer 250 ns 
(minimum) after it received BDMGI L. and its BSYNC L bus receiver 
becomes negated. 


22~Bus Specification 


RNA OT ISSIR TIE IRI ORDO HIN ISSIR NA IHR ADDN RNA A RUM BHO HF BR GORE RU il IH 0 OL A UG ON NN i Raa emu nN saaNnalmneNensenmanonsnenainn 


10 


During the bus mas tership rel inquishment phase, the DMA device 
gives up the bus by negating BSACK L. This occurs after completing 
(or ere the last data transfer cycle (BRPLY L negated). 

BSACK UL. ay be negated up to a maximum of 300 ns before negating 
BSYNC L. le A~7 shows the DMA protocol, and Figure A-8 shows 
DMA request/grant timing. 


NOTE 
. 8 are eee 


etl to “the use “eg the bus sor other 
System functions, such as memory refresh 
(if required). 


KDJ11- BUS MASTER 
(MEMORY | eae 1 N 


REQUEST BUS 
— ~~ @ ASSERT BDMRL 


GRANT BUS CONTROL 7 
„ NEAR THE END OF THE te 
CURRENT BUS CYCLE 
(BRPLY L 1S NEGATED) 
ASSERT BDMGO L AND 
INHIBIT NEW PROCESSOR eh si | 
GENERATED BYSNC L FOR — ee ACKNOWLEDGE BUS 
THE DURATION OF THE “wm ~MASTERSHIP 
DMA OPERATION. © RECEIVE BOMG 
— @WAIT FOR NEGATION OF 
a* BRPLY L 
TERMINATE GRANT ae 
SEQUENCE | 
® NEGATE BDMGO L AND 
WAIT FOR DMA OPERATION ~~ - 
TO BE COMPLETED — — 
—m EXECUTE A DMA DATA 
TRANSFER 
„ ADDRESS MEMORY AND 
TRANSFER UP TO 4 WORDS 
OF DATA AS DESCRIBED 
FOR DAT, OR DATO BUS 
CYCLES 
® RELEASE THE BUS BY 
TERMINATING BSACK L 
(NO SOONER THAN 
Ars ie PROCESSOR 8 NEGATION OF LAST BRPLY L) 
aoe a gee AND BSYNC L. 
OPERATION a 
® ENABLE PROCESSOR. 
GENERATED BSYNC L 
(PROCESSOR IS BUS WAIT 4 uS OR UNTIL 
MASTER) OR ISSUE ANOTHER FIFO TRANSFER 
ANOTHER GRANT IF BDMR IS PENDING BEFORE 
L IS ASSERTED, REQUESTING BUS AGAIN 


WM ee 


Figure A~7 DMA Protocol 


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Figure A-8 DMA Request/Grant Timing 


A. 4. 2 Block Mode DMA 

For * throughput, block mode DMA may be implemented on a 
device for se with memories that support this type of transfer. 
In à block “node transaction, the starting memory address is 
asserted, followed by data for that address, and data for 
consecutive addresses. 


By eliminating the assertion of the address for each data word, 
the transfer rate is almost doubled. The DATBI and DATBO bus 
cycles are described below. 


Q22-Bus Specification 


inicio 


5 Lo ps Rg i Onis CAR Ei iii in 


A. 4. 2. 1 DATBI — The device addressing portion of the cycle is 
the same as described earlier for other bus cycles. (See Figure 
A-9.) The bus master gates BDAL<21:00>, BBS7, and the negation of 
BWTBT onto the bus. 


The master asserts the first BDIN 100 ns after BSYNC, and asserts 
BBS7 a maximum of 50 ns after asserting BDIN for the first time. 
BBS7 is a request to the slave for a block mode transfer. BBS7 
remains asserted until a maximum of 50 ns after the assertion of 
BDIN for the last time. BBS7 may be gated as soon as the 
conditions for asserting BDIN are met. 


The slave asserts BRPLY a minimum of 0 ns (8 ns maximum to avoid 
bus timeout) after receiving BDIN. It asserts BREF concurrently 
with BRPLY if it is a block mode device capable of supporting 
another BDIN after the current one. The slave gates BDAL<15:00> 
onto the bus 0 ns (minimum) after the assertion of BDIN, and 125 
ns (maximum) after the assertion of BRPLY. 


The master receives the stable data from 200 ns (maximum) after 
the assertion of BRPLY until 20 ns (minimum) after the negation of 
BDIN. It negates BDIN 200 ns (minimum) after the assertion of 
BRPLY. 


The slave negates BRPLY 0 ns (minimum) after the negation of BDIN. 
If BBS7 and BREF are both asserted when BRPLY is negated, the 
Slave prepares for another BDIN cycle. BBS7 is stable from 125 ns 
after BDIN is asserted until 150 ns after BRPLY is negated. The 
master asserts BDIN 150 ns (minimum) after BRPLY is negated, and 
the cycle is continued as before. (BBS? remains asserted and the 
Slave responds to BDIN with BRPLY and BREF.) BREF is stable from 
75 ns after BRPLY is asserted until 20 ns (minimum) after BDIN is 
negated. 


If BBS7 and BREF are not both asserted when BRPLY is negated, the 
Slave removes the data from the bus 0 ns (minimum) and 100 ns 
(maximum) after negating BRPLY. The master negates BSYNC 250 ns 
(minimum) after the assertion of the last BRPLY, and 0 ns 
(minimum) after the negation of that BRPLY. 


A. 4. 2. 2 DAT BO — The device addressing portion of the cycle is 
the same as shown in Figure A-10. The bus master gates 
BDAL<21:00>, BBS7, and the assertion of BWTBT onto the bus. 


A minimum of 100 ns after BSYNC is asserted, data on BDAL<15:00> 
and the negated BWTBT are put onto the bus. The master then 
asserts BDOUT a minimum of 100 ns after gating the data. 


The slave receives stable data and BWTBT from 25 ns (minimum) 
before the assertion of BDOUT to 25 ns (minimum) after the 
negation of BDOUT. The slave asserts BRPLY 0 ns (minimum) after 
receiving BDOUT. It also asserts BREF concurrently with BRPLY if 
it is a block mode device capable of supporting another BDOUT 
after the current one. 


A-18 


Q22~Bus Specification 


a NSS 


5 1 — ban 


SIGNALS AT BUS MASTER 


TBS? 


R/TDAL | TADDRESS| | Xxxxx | R DAT. 


Tsync | 13 


＋ be | 


TIMES ARE MIN. EXCEPT WHERE “ DENOTES MAX. 


WANT OOO 


Figure A-9 DATBI Bus Cycle Timing 


SIGNALS AT BUS MASTER 


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TIMES ARE MIN. EXCEPT WHERE “*” DENOTES MAX. 


Figure A-10 DATBO Bus Cycle Timing 


Q22~Bus Specification 


eee nh nee 


The master negates BDOUT 150 ns (minimum) after the assertion of 
BRPLY. If BREF was asserted when BDOUT was negated, and the master 
wants to transmit more data in this block mode cycle, the new data 
is gated onto the bus 100 ns (minimum) after BDOUT is negated. 
BREF is stable from 75 ns (maximum) after BRPLY is asserted until 
20 ns (minimum) after BDOUT is negated. The master asserts BDOUT 
100 ns (minimum) after gating new data onto the bus and 150 ns 
minimum after BRPLY negates. The cycle continues as before. 


If BREF was not asserted when BDOUT was negated, or if the bus 
master does not want to transmit more data in this cycle, the 
master removes data from the bus 100 ns (minimum) after negating 
BDOUT. The slave negates BRPLY O ns (minimum) after negating 
BDOUT. The bus master negates BSYNC 175 ns (minimum) after 
negating BDOUT, and 0 ns (minimum) after the negation of BRPLY. 


A. 4.3 DMA Guidelines 


1. Systems with memory refresh over the bus must not include 
devices that perform more than one transfer per 
acquisition. 


2. Bus masters that do not use block mode are limited to four 
DATI, four DATO, or two DATIO transfers per acquisition. 


ters that do not monitor BDMR are 


3. Block mode bus ma: 
: nsfers per acquisition. 


4 
limited to eight tra 


4. If BDMR is not asserted after the seventh transfer, block 
mode bus masters that do monitor BDMR may continue making 
transfers until the bus slave fails to assert BREF, or 
until they reach the total maximum of 16 transfers. 


as 


A. 5 INTERRUPTS 

The interrupt capability of the Q22-Bus allows an I/O device to 
temporarily suspend (interrupt) current program execution and 
divert processor operation to service the requesting device. The 
processor inputs a vector from the device to start the service 
routine (handler). Like the device register address, hardware 
fixes the device vector at locations within a designated range 
below location 001000. The vector indicates the first of a pair of 
addresses. The processor reads the contents of the first address, 
the starting address of the interrupt handler. The contents of the 
second address is a new processor status word (PS). 


The new PS can raise the interrupt priority level, thereby 
preventing lower-level interrupts from breaking into the current 
interrupt service routine. Control is returned to the interrupted 
program when the interrupt handler is ended. The original 
interrupted program's address (PC) and its associated PS are 
Stored on a stack. The original PC and PS are restored by a return 
from interrupt (RTI or RTT) instruction at the end of the handler. 
The use of the stack and the Q22-Bus interrupt scheme can allow 
interrupts to occur within interrupts (nested interrupts), 
depending on the PS. 


Q22~Bus 


K tical iAH DH aE AHO I OC ein pon 


Specification 


Interrupts can be caused by Q22-Bus options or the MicroVAX CPU. 
Those interrupts that originate from within the processor are 
called “traps". Traps are caused by programming errors, hardware 
errors, special instructions, and maintenance features. 


i a 
3 
10 jn 


The following are Q22-Bus signals used in interrupt transactions. 


BIRQ4 
BIRQ5 
BIRQ6 
BIRQ?7 
BIAKI 
BIAKO 


Interrupt request priority level 4 
Interrupt request priority level 5 
Interrupt request priority level 6 
Interrupt request priority level 7 
Interrupt acknowledge input 
Interrupt acknowledge output 


a ee ia ee ea a 


BDAL<21:00> Data/address lines 
BDIN L Data input strobe 
BRPLY L Reply 


A.5.1 Device Priority 
The Q22-Bus supports the following two methods of device priority. 


1. Distributed Arbitration — Priority levels are implemented 
on the hardware. When devices of equal priority level 
request an interrupt, priority is given to the device 
electrically closest to the processor. 


2. Position-Defined Arbitration -- Priority is determined 
solely by electrical position on the bus. The closer a 
device is to the processor, the higher its priority is. 


A. 5. 2 Interrupt Protocol 

Interrupt protocol on the Q22-Bus has three phases: the interrupt 
request phase, interrupt acknowledge and priority arbitration 
phase, and interrupt vector transfer phase. Figure A-1l shows the 
interrupt request/acknowledge sequence. 


The interrupt request phase begins when a device meets its 
specific conditions for interrupt requests. For example, the 
device is ready, done, or an error has occurred. The interrupt 
enable bit in a device status register must be set. The device 
then initiates the interrupt by asserting the interrupt request 
line(s). BIRQ4 L. is the lowest hardware priority level and is 
asserted for all interrupt requests for compatibility with 
previous Q22 processors. The level at which a device is configured 
must also be asserted. A special case exists for level 7 devices 
that must also assert level 6. For an explanation, refer to the 
discussion below on arbitration involving the 4-level scheme. 


— ONAN MMMM ALLMAN LLNS AL OO ET ASS 


Interrupt Level Lines Asserted by Device 


uten sRUDIIN RNASE OCHRE — ß SEED MAREE EOIN MMMM NMR RMA e TSA OT IN, 


4 BIRQ4 L 

é BIRQ4 L, BIRQS L 

6 BIRQ4 L, BIRQ6 L 

7 BIRQ4 L, BIRQ6 L, BIRQ7 L 


ß AMAA A EAN SIE nnonsienienssiaaniRcERRONRE SOR DEENNIETANTAR uebi ER HSIN NEO EOND INN 


ti aioon lbelken eum. 


Q22-Bus Specification 


a a OS RRO ONS NIRA i 


STROBE INTERRUPTS 
® ASSERT BDIN L 


| 
| 


GRANT REQUEST 
® PAUSE AND ASSERT BIAKO L 


RECEIVE VECTOR AND 
TERMINATE REQUEST 

® INPUT VECTOR ADDRESS 

® NEGATE BDIN L AND BIAKOL 


PROCESS THE INTERRUPT 

@ SAVE INTERRUPTED PROGRAM 
PC AND PS ON STACK 

@ LOAD NEW PC AND PS FROM 
VECTOR ADDRESSED LOCATION 

® EXECUTE INTERRUPT SERVICE 
ROUTINE FOR THE DEVICE 


Figure K-11 


; DEVICE 


INITIATE REQUEST 
me & ASSERT BIRO L 


—_— nonce vane e 
“ay — 
RECEIVE BDIN L 
® STORE “INTERRUPT SENDING” 
IN DEVICE 
; “nt eggs — 
RECEIVE BIAKI L 
@® RECEIVE BIAKI L AND INHIBIT 
BIAKO . 
@ PLACE VECTOR ON BDAL < 15:00 > 
@ ASSERT BRPLY I 
aw woe ® NEGATE BIRO L 
— e esac 
i ee 9 
COMPLETE VECTOR TRANSFER 
® REMOVE VECTOR FROM BDAL BUS 
awe » ® NEGATE BRPLY L 


1 


e e 


Interrupt Request/Acknowledge Sequence 


Q22-Bus Specification 


The interrupt request line remains asserted until the request is 
acknowledged. 


During the interrupt acknowledge and priority arbitration phase, 
the LSI-11/23 processor acknowledges interrupts under the 
following conditions. 


l. The device interrupt priority is higher than the current 
PS<7:5>. 


2. The processor has completed instruction execution and no 
additional bus cycles are pending. 


The processor acknowledges the interrupt request by asserting BDIN 
L, and 150 ns (minimum) later asserting BIAKO L. The device 
electrically closest to the processor receives the acknowledge on 
its BIAKI L bus receiver. 


At this point, the two types of arbitration must be discussed 
separately. If the device that receives the acknowledge uses the 
4-level interrupt scheme, it reacts as follows. 


1. If not requesting an interrupt, the device asserts BIAKO L 
and the acknowledge propagates to the next device on the 
bus. 


2. If the device is requesting an interrupt, it must check 
that no higher-level device is currently requesting an 
interrupt. This is done by monitoring higher-level request 
lines.The table below lists the lines that need to be 
monitored by devices at each priority level. 


In addition to asserting levels 7 and 4, level 7 devices 
must drive level 6. This is done to simplify the 
monitoring and arbitration by level 4 and 5 devices. In 
this protocol, level 4 and 5 devices need not monitor 
level 7 because level 7 devices assert level 6. Level 4 
and 5 devices become aware of a level 7 request because 
they monitor the level 6 request. This protocol has been 
optimized for level 4, 5, and 6 devices, since level 7 
devices are very seldom necessary. 


Device Priority Level Line(s) Monitored 
BIRQ5, BIRQ6 
BIRQ6 
BIRQ7 


iii. 


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Q22-Bus Specification 


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3. If no higher~level device is requesting an interrupt, the 
acknowledge is blocked by the device. (BIAKO L is not 
asserted.) Arbitration logic within the device uses the 
leading edge of BDIN L to clock a flip-flop that blocks 
BIAKO L. Arbitration is won, and the interrupt vector 
transfer phase begins. 


4. If a higher-level request line is active, the device 
disqualifies itself and asserts BIAKO L to propagate the 
acknowledge to the next device along the bus. 


iming must be considered carefully when implementing 
interrupts. See Figure A-12. 


If a single-level interrupt device receives the acknowledge, it 
as follows. 
1. If not requesting an interrupt, the device asserts BIAKO L 
and the acknowledge propagates to the next device on the 
bus. 


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Q22~Bus Specification 


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2. If the device was requesting an interrupt, the acknowledge 
is blocked using the leading edge of BDIN L, and 
arbitration is won. The interrupt vector transfer phase 
begins. 


The interrupt vector transfer phase is enabled by BDIN L and BIAKI 
L. The device responds by asserting BRPLY L and its BDAL<15:00> L 
bus driver inputs with the vector address bits. The BDAL bus 
driver inputs must be stable within 125 ns (maximum) after BRPLY L 
is asserted. The processor then inputs the vector address and 
negates BDIN L and BIAKO L. The device then negates BRPLY L and 
100 ns (maximum) later removes the vector address bits. The 
processor then enters the device's service routine. 


NOTE 
Propagation delay from BIAKI L to BIAKO 
L must not be greater than 500 ns per 
Q22-Bus slot. 


The device must assert BRPLY L within 10 
us (maximum) after the processor asserts 
BIAKI L. 


A.5.3 Q22-Bus 4—-Level Interrupt Configurations 

If you have high-speed peripherals and desire better software 
performance, you can use the 4-level interrupt scheme. Both 
position-independent and position-dependent configurations can be 
used with the 4-level interrupt scheme. 


Figure A-13 shows the position-independent configuration. This 
allows peripheral devices that use the 4-level interrupt scheme to 
be placed in the backplane in any order. These devices must send 
out interrupt requests and monitor higher-level request lines as 
described. The level 4 request is always asserted from a 
requesting device regardless of priority. If two or more devices 
of equally high priority request an interrupt, the device 
physically closest to the processor wins arbitration. Devices that 
use the single-level interrupt scheme must be modified, or placed 
at the end of the bus, for arbitration to function properly. 


Figure A-14 shows the position-dependent configuration. This 
configuration is simpler to implement. A constraint is that 
peripheral devices must be inserted with the highest-priority 
device located closest to the processor, and the remaining devices 
placed in the backplane in decreasing order of priority (with the 
lowest-priority devices farthest from the processor). With this 
configuration, each device has to assert only its own level and 
level 4. Monitoring higher-level request lines is unnecessary. 
Arbitration is achieved through the physical positioning of each 
device on the bus. Single-level interrupt devices on level 4 
should be positioned last on the bus. 


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A-26 


922-Bus Specification 


A.6 CONTROL FUNCTIONS 

The following Q22-Bus signals provide control functions. 
BREF L Memory refresh (also block mode DMA) 
BHALT L Processor halt 
BINIT L Initialize 
BPOK H Power OK 
BDCOK H DC power OK 

A. 6.1 Memory Refresh 


If BREF is asserted during the address portion of a bus data 
transfer cycle, it causes all dynamic MOS memories to be addressed 
simultaneously. The sequence of addresses required for refreshing 
the memories is determined by the specific requirements for each 
memory. The complete memory refresh cycle consists of a series of 
refresh bus transactions. A new address is used for each 
transaction. A complete memory refresh cycle must be completed 
within 1 or 2 ms. Multiple data transfers by DMA devices must be 
avoided since they could delay memory refresh cycles. This type of 
refresh is done only for memories that do not perform on-board 
refresh. 


A.6.2 Halt 

Assertion of BHALT L for at least 25 ns interrupts the processor, 
which stops program execution and forces the processor 
unconditionally into console I/O mode. 


A.6.3 Initialization 

Devices along the bus are initialized when BINIT L is asserted. 
The processor can assert BINIT L as a result of executing a reset 

instruction as part of a power-up or power-down sequence. BINIT L 
is asserted for approximately 10 us when reset is executed. 


A. 6. 4 Pover Status 

power status protocol is controlled by two signals, BPOK H and 
BDCOK H. These signals are driven by an external device (usually 
the power supply). 


A.. BDCOK H 

When asserted, this indicates that de power has been stable for at 
least 3 ms. Once asserted, this line remains asserted until the 
power fails. It indicates that only 5 us of de power reserve 
remains. 


A. 6. 6 BPOK H 

When asserted, this indicates there is at least an 8 ms reserve of 
dc power, and that BDCOK H has been asserted for at least 70 ms. 
Once BPOK has been asserted, it must remain asserted for at least 
3 ms. The negation of this line, the first event in the power~fail 
sequence, indicates that power is failing and that only 4 ms of dc 
power reserve remains. 


A~27 


Q22-Bus Specification 


D SOS OAG RLRPaCUSoiniiia i aii: 


A.6.7 Power~Up/Down Protocol 

Power-up protocol begins when the power supply applies power with 
BDCOK H negated. This forces the processor to assert BINIT L. When 
the dc voltages are stable, the power supply or other external 
device asserts BDCOK H. The processor responds by clearing the PS, 
meee point status regis ster (FPS), and floating point exception 
registe (FEC). BINIT L is asserted for 12.6 us, and then negated 
For 110 us. The processor continues to test for BPOK H until it is 
asserted. The power supply asserts BPIK H 70 ms (minimum) after 
BDCOK H is asserted. The processor then performs its power-up 
sequence. Notmal power must be maintained at least 3.0 ms before a 
power~-down sequence can begin. 


A power-down sequence begins when the power supply negates BPOK H. 
When the current instruction is completed, the processor traps to 
a power-down routine at location 24. The end of the routine is 
terminated with a halt instruction to avoid any possible memory 
corruption as the de voltages decay. 


When the processor executes the halt instruction, it tests the 
BPOK H signal. If BPOK H is negated, the processor enters the 
power-up sequence. It clears internal registers, generates BINIT 
L, and continues to check for the assertion of BPOK H. If it is 
asserted and de voltages are still stable, the processor performs 
the rest of the power-up sequence. Figure A-15 shows 


te 


power-up/power~-down timing. 


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Figure A-15 Power-Up/Power~-Down Timing 


A-28 


QO22-Bus Specification 


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A. 7 Q22-BUS ELECTRICAL CHARACTERISTICS 
SIGNAL LEVEL SPECIFICATION 


Input Logic Levels: 


TTL Logical Low 0.8 Vdc (maximum) 
TTL Logical High 2.0 Vde (minimum) 


Output Logic Levels: 


TTL Logical Low 0.4 Vde (maximum) 
TTL Logical High 2.4 Vde (minimum) 
A. 7.1 Load Definition 


AC loads make up the maximum capacitance allowed per signal line 
to ground. A unit load is defined as 9.35 pF of capacitance. DC 
loads are defined as maximum current allowed with a signal line 
driver asserted or unasserted. A unit load is defined as 210 HA in 
the unasserted state. 


A. 7. 2 120-Ohm Q22-Bus 

The electrical conductors interconnecting the bus device slots are 
treated as transmission lines. A uniform transmission line, 
terminated in its characteristic impedance, propagates an 
electrical signal without reflections. Since bus drivers, 
receivers, and wiring connected to the bus have finite resistance 
and nonzero reactance, the transmission line impedance is not 
uniform, and introduces distortions into pulses propagated along 
it. Passive components of the Q22-Bus (such as wiring, cabling, 
and etched signal conductors) are designed to have a nominal 
characteristic impedance of 120 ohms. 


The maximum length of interconnecting cable, excluding wiring 
within the backplane, is limited to 4.88 m (16 ft). 


A. 7.3 Bus Drivers 

Devices driving the 120-ohm Q22-Bus must have open collector 
outputs and meet the following specifications. 

DC SPECIFICATIONS 


Output low voltage when sinking 70 mA of current: 0.7 V 
(maximum). 


Output high leakage current when connected to 3.8 Vdc: 25 pA 
(even if no power is applied, except for BDCOK H and BPOK H). 


These conditions must be met at worst-case supply temperature, 
and input signal levels. 


A-29 


Q22-~Bus Specification 


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AC SPECIFICATIONS 
Bus driver output pin capacitance load: Not to exceed 10 pF. 
Propagation delay: Not to exceed 35 ns. 


Skew (difference in propagation time between slowest and 
fastest gate): Not to exceed 25 ns. 


Rise/fall times: Transition time (from 10% to 90% for positive 
transition, 90% to 10% for negative transition) must be no 
faster than 10 ns. 


A. 7.4 Bus Receivers 
Devices that receive signals from the 120-ohm Q22-Bus must meet 
the following requirements. 


DC SPECIFICATIONS 
Input low voltage (maximum): 1.3 V. 
Input high voltage (minimum): 1.7 V. 


Maximum input current when connected to 3.8 Vdc: 80 uA (even 
if no power is applied). 


These specifications must be met at worst-case supply 
voltage, temperature, and output signal conditions. 


AC SPECIFICATIONS 
Bus receiver input pin capacitance load: Not to exceed 10 pF. 
Propagation delay: Not to exceed 35 ns. 

f 


Skew (di 
t 


erence in propagation time between slowest and 
fastes ): 


iffe 
gate Not to exceed 25 ns. 

A. 7.5 Bus Termination 

The 120-ohm Q22-Bus must be terminated at each end by an 
appropriate terminator, as shown in Figure A-16. This is to be 
done aS a voltage divider with its Thevenin equivalent equal to 
120 ohms and 3.4 V (nominal). This type of termination is provided 
by an REVII-A refresh/boot/terminator, BDV11-AA, KPV11-B, TEVII, 
or by certain backplanes and expansion cards. 


A-30 


Specification 


+5 V 


330 N 2 


120 2 250 $2 
— BUS LINE » BUS LINE 
TERMINATION TERMINATION 
680 N 2 
MR-6033 
Figure A-16 Bus Line Terminations 


Fach of the several Q22-Bus lines (all signals whose mnemonics 
start with the letter B) must see an equivalent network with the 
following characteristics at each end of the bus. 


Input impedance 120 ohm +5%, ~15% 

(with respect to ground) 

Open circuit voltage 3.4 Vde +5% 

Capacitance load Not to exceed 30 pF 
NOTE 


The resistive termination may be 
provided by the combination of two 
modules. (The processor module supplies 
220 ohms to ground. This, in parallel 
with another 220-ohm card, provides 120 
ohms.) Both terminators must reside 
physically within the same backplane. 


A.7.6 Bus Interconnecting Wiring 
A.7.6.1 Backplane Wiring — The wiring that connects all device 


interface slots on the Q22-bus must meet the following 
specifications. 


1. The conductors must be arranged so that each line exhibits 
a characteristic impedance of 120 ohms (measured with 
respect to the bus common return). 


2. Crosstalk between any two lines must be no greater than 5 
percent. Note that worst-case crosstalk is manifested by 
simultaneously driving all but one signal line and 
measuring the effect on the undriven line. 


A~31 


Q22-Bus Specification 


ee — 8 


measured between the 
na the far-end terminator module 
ening « „ cables, backplane 
le etch, etc.) must not exceed 20 


3. DC resistance of the signal path, as 


near-end terminator e 
(including all interv 
wiring, connector-modul 
ohms. 


4. DC resistance of the common return path, as measured 
between the near-end terminator and the far-end terminator 
module (including 411 intervening connectors, cables, 
5 wiring, connector-module etch, etc.) must not 

exceed an equivalent of 2 ohms per signal path. Thus, the 
composite signal return path dc 5 must not exceed 


é 
2 ohms divided by 40 bus lines, or 50 milliohms. Note that 
although this common return path is nominally at ground 
potential, the conductance must be part of 9 5 bus wiring. 
The specified low impedance return path must be provided 
by the bus wiring as distinguished from the common system 
or power ground path. 


A. 7. 6. 2 Intra- Backplane Bus Wiring — The wiring that connects 
the bus connector slots within one contiguous backplane is part of 
the overall bus transmission line. Owing to implementation 
co nce of 120 ohms may 


19 
nstraints, the nominal characteristic impeda 
not be achievable. Dist 188856 wiring capacitance in excess of the 
amount required to ae eve the nominal 120-ohm impedance may not 


exceed 60 pF per signal line per backplane. 


A.7.6.3 Power and Ground — Each bus interface slot has connector 
pins io for the following dc voltages. The maximum allowable 
current per pin is 1.5 A. +5 Vde must be regulated to 5 percent 
with a maximum ripple of 100 mV pp. +12 Vdc must be regulated to 3 
percent with a maximum ripple of 200 mV pp. 


1 


5 +5 Vde — Three pins (4.5 A maximum per bus device slot) 
0 +12 Vde — Two pins (3.0 A maximum per bus device slot) 
= pees ~~ Eight pins (shared by power return and signal 
NOTE 
Power is not bussed between backplanes 


on any interconnecting bus cables. 


SYSTEM CONFIGURATIONS 


OY 
ee 


22 Bus Systems can be divided into two types: 


1. Systems containing one backplane 
2. Systems containing multiple backplanes 


A-32 


hain esi iG i iia eka i ein Nii ii RHR ou um iia 


Q22-Bus Specification 


Before configuring any system, three characteristics for each 
module in the system must be known: 


® Power consumption —— 5 Vde and +12 Vde current 
requirements. 


® AC bus loading —— The amount of capacitance a module 
presents to a bus signal line. AC loading is expressed in 
terms of ac loads, where one ac load equals 9.35 pF of 
capacitance. 


2 DC bus loading -- The amount of de leakage current a 
module presents to a bus signal when the line is high 
(undriven). DC loading is expressed in terms of de loads, 
where one de load equals 210 A (nominal). 


Power consumption, ac loading, and de loading specifications for 
each module are included in the Microcomputer Interface Handbook. 


NOTE 
The ac and de loads and the power 
consumption of the processor module, 
terminator module, and backplane must be 
included in determining the total 
loading of a backplane. 


Rules for configuring single~backplane systems 


1. When using a processor with 220-ohm termination, the bus 
can accommodate modules that have up to 20 ac loads 
(total) before additional termination is required. (See 
Figure A-17.) If more than 20 ac loads are included, the 
other end of the bus must be terminated with 120 ohms, and 
then up to 35 ac loads may be present. 


BACKPLANE W 
35.6 CM (141N 


. 
2 
x 
= 
a 
= 


OPTIONAL | 


35 AC LOADS 
20 DC LOADS 


PROCESSOR TERM 
MA-6034 


Figure A~17 Single-Backplane Configuration 


A-33 


2 2 Bus 


= 


Spe ifi cation 


budget mee igen 


With 120-ohm processor termination, up to 35 ac loads can 
be used without additional termination. If 120-ohm bus 


termination is added, up to 45 ac loads can be configured 
in the backplane. 


The bus can accommodate modules up to 20 de loads (total). 


nal lines on the backplane can be up to 35.6 cm 


for configuring multiple-backplane systems 


Figure A-18 shows that up to three backplanes may make up 
the system. 


The signal lines on each backplane can be up to 25.4 cm 
(10 in) long. 


Each backplane can accommodate modules that have up to 22 
ac loads (total). Unused ac loads from one backplane may 
not be added to another backplane if the second backplane 
loading will exceed 22 ac loads. It is desirable to load 
backplanes equally, or with the highest ac loads in the 
First and second backplanes. 


DC loading of all modules in all backplanes cannot exceed 
20 loads (total). 


Both ends of the bus must be terminated with 120 ohms, 
This means the first and last backplanes must have an 
impedance of 120 ohms. To achieve this, each backplane may 
be lumped together as a single point. The resistive 
termination may be provided by a combination of two 
modules in the backplane — the processor providing 220 
ohms to ground in parallel with an expansion paddle card 
providing 250 ohms to give the needed 120-ohm termination. 
Alternately, a processor with 120-ohm termination would 
need no additional termination on the paddle card to 
attain 120 ohms in the first box. The 120-ohm termination 
in the last box can be provided in two ways: the 
termination resistors may reside either on the expansion 
paddle card, or on a bus termination card (such as the 
BDV11). 


The 5 connecting the first two backplanes is (are) 
61 cm (2 ft) or more in length. 


The cable (s) connecting the second backplane to the third 
backplane is (are) 122 cm (4 ft) longer or shorter than 
the cable(s) connecting the first and second backplanes. 


The combined length of both cables cannot exceed 4.88 m 
(16 ft 


The cables used must have a characteristic impedance of 
120 


Q22~Bus Specification 


c TONNER sini 50 1 n iis 1 


__ BACKPLANE WRERER — — 
35.6 CM (14 IN) MAX | 


20 AC LOADS MAX 


Sack LANE WIRE 
| 25.4 CM (10 IN) MAX 


ADDITIONAL 
CABLES AND 
BACKPLANE 


20 AC LOADS MAX 


_ BACKPLANE WIRE | | 
25.4 CM (10 IN) MAX — 


CABLE / 


ben p, ye — —— — 
TERM 


20 AC LOADS 


NOTES: 


1. TWO CABLES (MAX) 4.88 M (16 FT) (MAX) 
TOTAL LENGTH. 


2.20 DC LOADS TOTAL (MAX). 


AR. 6035 


Figure A-18 Multiple- Backplane Configuration 


4 
al 


Q22-Bus Specification 


i ee 


hene 


A. 8.1 Power Supply Loading 

Total power requirements for each backplane can be determined by 
obtaining the total power requirements for each module in the 
backplane. Obtain separate totals for +5 V and +12 V power. Power 
requirements for each module are specified in the Microcomputer 
interfaces Handbook. 


When distributing power in multiple-backplane systems, do not 
attempt to distribute power via the Q22-Bus cables. Provide 
Separate, appropriate power wiring from each power supply to each 
backplane. Each power supply should be capable of asserting BPOK H 
and BDCOK H Signals according to bus protocol; this is required if 
automatic power-fail/restart programs are implemented, or if 
specific peripherals require an orderly power-down halt sequence. 
The proper use of BPOK H and BDCOK H signals is strongly 
recommended. 


9 MODULE CONTACT FINGER NTIFICATION 
yital's plug-in modules all use the same contact finger (pin) 
tification system. A typical pin is shown in Figure 


The Q22-Bus is based on the use of quad-height modules that plug 
into a 2-slot bus connector. Each slot contains 36 lines (18 lines 
on both the component side and the solder side of the circuit 
board). 


Slots, row A, and row B include a numeric identifier for the side 
of the module. The component side is designated Side 1, the solder 
side is designated side 2, as shown in Figure A-20. Letters 
ranging from A through V (excluding 6, I, o, and Q) identify a 
particular pin on a side of a slot. Table A-4 lists and identifies 

the bus pins of the quad-height module. A bus pin identifier 
ending with a 1 is found on the component side of the board, while 
a bus pin identifier ending with a 2 is found on the solder side 
of the board. 


The positioning notch between the two rows of pins mate: 
protrusion on the connector block for correct module positi 


MPT G5 8o 


Figure A~19 Typical Pin Identification System 


Q22-Bus Specification 


NO 


a 


— 


— — 


ROW C 


ee 

e 

es 
ee 


15 


SIDE 2 
SOLDER SIDE 


SID 
COMPONENT SIDE 


0 


Figure A-20 Quad-Height Module Contact Finger Identification 


A~-37 


Q22-Bus Specification 


Table Ap a Bus Pin Identifiers 


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Bus Pin "Mnemonic (s) De escription 


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AAL BIRQS L Inte errupt request N level 5. 
AB BIRQ6 L Interrupt request priority level 6. 


AC 1 BDAL16 L Extended address bit during addressing 
protocol; memory error data line during 
data transfer protocol. 


ADI BDAL17 L Extended address bit during addressing 
protocol; memory error logic enable 
during data transfer protocol. 


AE1 SSPARE1] Special Spare — Not assigned or bussed 
(alternate +5B) in Digital's cable or backplane 
assemblies; available for user 
connection. Optionally, this pin may be 
used for +5 V battery (+5 B) backup 
power to keep critical circuits alive 
during power failures. A jumper is 
required on Q22-Bus options to open 
(disconnect) the +5 B circuit in systems 
that use this line as SSPARE1I. 


AF1 SSPARE2 rua Spare ~~ Not assigned or bussed 
i Jigital's cable or backplane 
assemblies; available for user 
interconnection. In the highest-priority 
device slot, the processor may use this 
pin for a signal to indicate its RUN 
state. 

AH] SSPARE3 Special Spare — Not assigned or bussed 

SRUN Simultaneously in Digital's cable or 
5 . available for user 

e An alternate SRUN 

nay be connected in the 

ority set. 


AJ] GND Ground —— System signal ground and de 
1 


AK MSPAREA Maintenance Spare -~ Normally connected 
together on the backplane at each option 
location (not a bussed connection). 


ALI MS PAREB Maintenance Spare — Normally connected 
together on the backplane at each option 
loca ation (not | a _bussed eC ee. 


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A-38 


Q22~-Bus Specification 


Table A-4 Bus Pin Identifiers (Cont) 


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Bus Pin Mnemonic (s) Description 
GND Ground —— System signal ground and de 
return. 


ANI] BDMR L Direct Memory Access (DMA) Request ~~ A 
device asserts this signal to request 
bus mastership. The processor arbitrates 
bus mastership between itself and all 
DMA devices on the bus. If the processor 
is not bus master (it has completed a 
bus cycle and BSYNC L is not being 
asserted by the processor), it grants 
bus mastership to the requesting device 
by asserting BDMGO L. The device 
responds by negating BDMR L and 
asserting BSACK L. 


API BHALT L Processor Halt -- When BHALT L is 
asserted for at least 25 us, the 
processor services the halt interrupt 
and responds by halting normal program 
execution. External interrupts are 
ignored but memory refresh interrupts in 
222 are enabled if W4 on the M7264 and 
M7264-YA processor modules is removed 
and DMA request/grant sequences are 
enabled. The processor executes the ODT 
microcode, and the console device 
operation is invoked. 


AR] BREF L Memory Refresh -~ Asserted by a DMA 
device. This signal forces all dynamic 
MOS memory units requiring bus refresh 
signals to be activated for each BSYNC 
L/BDIN L bus transaction. It is also 
used as a control signal for block mode 
DMA. 


CAUTION: 

The user must avoid multiple DMA data 
transfers (burst or hot“ mode) that 
could delay refresh operation if using 
DMA refresh. Complete refresh cycles 
must occur once every 1.6 ms if 
required. 


r r AL EAL LDELILBLLECLELPL LLL LLL 


A~ 39 


Q22-Bus Specification 


Se 


wie Pin 


ian 


l A~4 


“Mnemonic (s) 


ASI 


AT 1 


AU] 


AVI 


BD1 


BE] 


A-40 


+12 B or +5 B 


GND 


PSPARE 1 


BDCOK H 


BPOK H 


SSPARE4 
BDALI18 L. 
(22-bit only) 


SSPARE5 
BDALI9S L. 
(22-bit only) 


SSPARE6 
BDAL20 L 


SS PARE 7 
BDA 1. 2 1 L 


Description 


currently not used dur ing data time. 


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Bus Pin C 3 


{so ORISA BENCHES oases SSSI ONES ECAR RE buena, 


112 Vdc or +5 V 1 b power to 


keep critical circuits alive during 
power Failures. This signal is not 


bussed to 381 in all of Digital's 
backplanes. A jumper is required on all 
Q22-Bus options to open (disconnect) the 
backup circuit from the bus in systems 
that use this line at the alternate 
voltage. 


Ground —— System signal ground and dc 
return. 


Spare —— Not assigned; 
not recommended. Preven 
modules are inserted upsi 


customer usage 
ts damage when 
de down. 


+5 VV Battery Power -- Secondary +5 V 
power connection. Battery power can be 
used with certain devices. 


DC Power OK ~~ A power supply-generated 
signal that is asserted when the 
available de yereede is sufficient to 
sustain reliable system operation, 


Power OK — Asserted by the power supply 
70 ms after BDCOK is negated when ac 
power drops below the value required to 
sustain power (approximately 75% of 
nominal). When negated during processor 
operation, a power~fail trap sequence is 
initiated. 


Special Spare in the Q22-Bus —— Not 
assigned. Bussed n 22-bit cable and 


i 
backolane assemblies; available for user 
interconnection. 


CAUTION: 
These pins may be used by manufacturing 
as test points in some options. 


In the Q22-Bus, these bussed address 
lines are address lines €21:18>; 
currently not used during data time. 


In the Q22-Bus, these bussed address 
lines are address lines €21:18>; 


aie GOON EINHORN 


Q22~Bus Specification 


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Table A-4 Bus Pin Identifiers (Cont) 


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Bus Pin Mnemonic (s) Description 


BH1 SSPARE8 Special Spare -- Not assigned or bussed 
in Digital's cable and backplane 
assemblies; available for user 
interconnection. 


BJ1 GND Ground —— System signal ground and de 
return. 


BK1 MSPAREB Maintenance Spare — Normally connected 
BLI MS PAREB together on the backplane at each option 
location (not a bussed connection). 


BM1 GND Ground —— System signal ground and de 
return. 


BN1 BSACK L This signal is asserted by a DMA device 
in response to the processor's BDMGO L 
Signal, indicating that the DMA device 
is bus master. 


BPI BIRO7 L Interrupt request priority level 7. 


BRI BEVNT L. External Event Interrupt Request — When 
asserted, the processor responds by 
entering a service routine via vector 
address 1008. A typical use of this 
signal is as A line-time clock 
interrupt. 


BS1 Ties +12 Vdc battery backup power (not bussed 
to AS1 in all of Digital's backplanes). 


871 GND Ground —— System signal ground and de 
return. 


B01 PS PARE 2 Power Spare 2 — Not assigned a 
function; not recommended for use. If a 
module is using -12 V (on pin AB2), and 
if the module is accidentally inserted 
upside down in the backplane, ~12 Vdc 
appears on pin BUI. 


BVI +5 +5 V Power -- Normal +5 Vde system 
power. 


AA2 +5 +5 V Power ~-- Normal +5 Vde system 
power. 


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Q022-Bus Specification 


RNAI 


AB2 


AC2 


AE2 


AF2 


AH2 


A-4 


BDOUT L 


BRPLY L 


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—12 V Power ~-- -12 Vde pover for 
(optional) devices requiring this 
voltage. 


NOTE: 

Each Q22~Bus module that requires 
negative voltages contains an inverter 
circuit that generates the required 
voltage(s). Therefore, -12 V power is 
not required with Digital's options. 


Ground —— System signal ground and de 
return. 


+12 V Power -- +12 Vde system power. 


Data Output —— When asserted, BDOUT 
implies that valid data is available on 
BDAL<0:15> L and that an output 
transfer, with respect to the bus master 
device, is taking place. BDOUT L is 
deskewed with respect to data on the 
bus. The slave device responding to the 
BDOUT L signal must assert BRPLY L to 
complete the transfer. 


Reply — BRPLY L is asserted in response 
to BDIN L or BDOUT L and during IAK 
transactions. It is generated by a slave 
device to indicate that it has placed 
its data on the BDAL bus or that it has 
accepted output data from the bus. 


t — BDIN IL. is used for two 


Data Input 
dus operations: 


types of 


When asserted during BSYNC L time, BDIN 
L implies an input transfer with respect 
to the current bus master, and requires 
a response (BRPLY L). BDIN L is asserted 
when the master device is ready to 
accept data from a slave device. 


When asserted without BSYNC L, it 
indicates that an interrupt operation is 
occurring. The master device must deskew 
input data from BRPLY L. 


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Q22-Bus Specification 


r r ß . 


Table A-4 Bus Pin Identifiers (Cont) 
Bus Pin Mnemonic (s) Description 
AJ2 BSYNC L Synchronize -- BSYNC L is asserted by 
the bus master device to indicate that 
it has placed an address on BDAL<0:17> 
L. The transfer is in process until 
BSYNC L is negated. 


AK2 BWTBT L Write/Byte -- BWTBT L is used in two 
ways to control a bus cycle: 


It is asserted at the leading edge of 
BSYNC L to indicate that an output 
sequence (DATO or DATOB), rather than an 
input sequence, is to follow. 


It is asserted during BDOUT L, ina 
DATOB bus cycle, for byte addressing. 


AL2 BIRQO4 L. Interrupt Request Priority Level 4 -- A 
level 4 device asserts this signal when 
its interrupt enable and interrupt 
request flips-flops are set. If the PS 
word bit 7 is 0, the processor responds 
by acknowledging the request by 
asserting BDIN L and BIAKO L. 


AM2 BIAKI I. Interrupt Acknowledge — In accordance 

AN2 BIAKO L with interrupt protocol, the processor 
asserts BIAKO L to acknowledge receipt 
of an interrupt. The bus transmits this 
to BIAKI L of the device electrically 
closest to the processor. This device 
accepts the interrupt acknowledge under 
two conditions: 1.) the device requested 
the bus by asserting BIRQXL, and 2.) the 
device has the highest-priority 
interrupt request on the bus at that 
time. 


If these conditions are not met, the 
device asserts BIAKO L to the next 
device on the bus. This process 
continues in a daisy~chain fashion until 
the device with the highest-interrupt 
priority receives the interrupt 
acknowledge signal. 


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A-43 


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Bus Pin Identifiers (Cont) 


weden nen mech, 


Description 

AP2 BBS7 L Bank 7 Select -- The bus master asserts 
this signal to reference the I/O page 
(including that portion of the I/O page 
reserved for nonexistent memory). The 
address in BDAL<0:12> L when BBS7 L is 
asserted is the address within the 1/0 
page. 


ne BDMGI L. Direct Memory Access Grant — The bus 

$2 BDMGO L arbitrator asserts this signal to grant 
bus mastership to a requesting device, 
according to bus mastership protocol. 
The signal is passed in a daisy-chain 
from the arbitrator (as BDMGO L) through 
the bus to BDMGI L of the next priority 
device (the device electrically closest 
on the bus). This device accepts the 
grant only if it requested to be bus 
master (by a BDMR L). If not, the device 
passes the grant (asserts BDMGO L) to 
the next device on the bus. This process 
continues until the requesting device 
acknowledges the grant. 


CAUTION: 
DMA device transfers must not interfere 
with the memory refresh cycle. 


AT2 BINIT L Initialize -- This signal is used for 
system reset. All devices on the bus are 
to return to a known, initial state; 
that is, registers are reset to zero, 
and logic is reset to state 0. 
Exceptions should be completely 
documented in programming and 
engineering specifications for the 
device. 


AU2 BDALO L Data/Address lines -- These two lines 

AV2 BDALI L are part of the 16—1ine data/ address bus 
over which address and data information 
are communicated. Address information is 
first placed on the bus by the bus 
master device. The same device then 
either receives input data from, or 
outputs data to, the addressed slave 
device or memory over the same bus 
lines. 


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idea i i ie EN 


Bus Pin 


BAZ 


12 


BDAL2 
BDAL3 
BDAL4 
BDAL5 
BDAL6 
BDAL7 
BDAL8 
BDAL9 
BDAL10 
BDALI1 
BDAL12 
BDAL13 
BDAL14 


Pre oF pee oe 


BDALI15 


SSeS NERC ENRON NTI EAC 


Table A-4 


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Mnenonic (8) 


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Q22~Bus Specification 


naa 


Bus Pin Identifiers (Cont) 


RSID HREOC OSORIO 


Description 


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+5 V Power -- Normal +5 Vdc system 
power. 


“12 V Power (voltage normally not 
supplied) “we ~12 Vde power for 
(optional) devices requiring this 
voltage. 


Ground — System signal ground and de 
return. 


+12 V Power ~~ +12 V system power. 


Data/Address Lines — These 14 lines 
part of the 16-line data/address bus. 


APPENDIX B 
LK201 KEYBOARD SPECIFICATION 


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8. 1 GENERAL DESCRIPTION 

The LK201 keyboard has 105 concave-surfaced keys that are divided 
into four groups: typing keys, numeric keypad for data entry, 
screen/cursor control keys for editing, and special programmable 
command/function keys supported by an enclosed printed circuit 
board. Four LEDS indicate when a specific function is in 
operation. A 1.9 m (6 ft) coiled cable connects the keyboard to a 
dedicated 4-pin MICRO-DIN connector on the monitor's rear panel. 
Figure B—1 shows the LK201 keyboard. 


The keyboard is the user interface to the system. It detects 
keystrokes, encodes them, and transmits the information to the 
central processor. The keyboard also receives information from the 
central processor. 


Communication between the keyboard and the central processor in 
the BA23 or BA123 enclosure is full-duplex, serial asynchronous, 
at a speed of 4800 baud. The communication lines conform to EIA 
Standard RS-423, which applies to unbalanced voltage interfaces. 


B. 2 PHYSICAL DESCRIPTION 
The keyboard used with the MicroVAX workstation has 105 keys 
arranged in the following four groups. (See Figure B-1.) 


Main keypad (57 keys) 

Numeric keypad (18 keys) 

Special function keypad (20 keys) 
Editing keypad (10 keys) 


@ ¢@ 6 6 


The keycaps can be installed manually, but require a special tool 
for removal. 


The keyboard circuitry is contained in a low-profile cabinet with 
a nominal height of 30 mm (1.2 in) from table top to home row. The 
keyboard case is made of two plastic shells that can be separated 
with a screwdriver. Nons a plastic strips along the bottom 
prevent the keyboard from sliding on a table top. Two feet can be 
manually inserted into holes to raise the back edge of the 
keyboard. 


LK201 Keyboard Specification 


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KEYPAD 


EDITING 
KEYPAD 


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re B—1 


LK201 Keyboard 


B-2 


LK201 Keyboard Specification 


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A plastic window along the top edge above the 
keys can be lifted to insert a keyboard label st 
thin paper strip, fits into the indented s 
according to the application program. 


1 function 


spe ia 
ip. The 
ace and varies 


r 
P 


Four LEDs are located beneath the plastic window: hold screen, 
lock, compose, and wait. 


A coiled cable (PN BCCO1), with a 4-pin modular connector on each 
end, connects the keyboard to the video monitor. The keyboard 
transmits four types of signals to the monitor that pass unchanged 
via the video cable to the system enclosure as shown in Figure 
B-2. The four signals are 


+12 V power to keyboard 

Ground to keyboard 

Serial Out (transmit line from keyboard) 
Serial In (receive line to keyboard). 


e 


The cable can be placed into a channel in the bottom case, and the 
modular-type telephone connector fits into the jack, J4. The cable 
can be inserted into the channel at either side of the keyboard. 


KEYBOARD 
CIRCUIT 
BOARD 


| SERIAL IN 


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Figure B-2 Keyboard Cable Connections 


Keyboard 


F 


Specification 


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LKZ 01 


B. 3 BLOCK DIAGR. 
Figure B-3 is a 

circuitry. All 
matrix“ are on 
the connections 
the 8051 mic 


DESCRIPTION 
Simplified block 
diagram 


troprocessor. 


in the 8051 8-bit 
three major keyboard operation 


The firmware 
following 
the detect 


1. Scans keyboard te 
4 


2. Transmits the results of 
1 0 


central processor. 
3. Receives information from the 
B, 3 „ Scanning 
The keyboard switches are connected 
18 X 8 line matrix. This provides a 
each key. 


he 18-line 
reading the 

keystroke a4 
code that is 


m 4 1 sais, 
axils 


0 te 


firmware s 
seep released 
‘ifies the de 
formation into 


cans ( 
key by 
‘tected 
an 8-bit 


oO 
d 
mn = 8 


B. 3.2 
TWO 


udio pEeneene cer 
control the audio transdt 
5 its ey from the 
he transducer (beep 

eep represents the 


5 of 
. i Ce its os 
circuit 
controls 
a short 


5 
er 


* 
5 ). 
: keyclick. 


be 


controlled 

18 each 
commands rr 

turns the indicator: 


A separate circuit, 
microprocessor, contro 
Firmware, responding to 
central processor, 


by a 
of the 


Keyboard Firmware Functions 

is paragraph describes the keyboard 
unctions are divided into two 
anged by instructions from the 
that can. 


system 


. 
a ad cal . N 
ae é 


B. 3. 3.1 Functions 
Instructions The 
instructions the 


e län, 


from 


following 


functi 
system's 31 


central 


Power-up test 
Keycodes 
© Special 


codes 


bannen tenen 


diagram 
blocks except the 

the printed circuit board. 
between the keyboard switches 


V 
at 
the keyboard 
system's 


at the 
fixed~posi 


and 
8-line 
9 5 


8051 
A long beep 


eceived 
S on 


5 
We 


Not Changed by the Syste 
ons 
processor. 


of the keyboard 
block marked "keyboard 
This EOE represents 
and the signals from 


controls the 


the same time. 


changes in the keyboard 


scan to the system's 


central processor. 


intersections of 
ition 


an 
identifier for 


detects a 


depressed or 
axis. The r 
t 


‘firmware then 
hi S$ positional 


que to that key. 


and Indicators 
isducer 


a 


and the indicators. One 
microprocessor and 
the bell, 


tu 


8051 
The 
system's 


e 
om the 
or of 


The 
cannot be 
processor, and 


firmware functions. 
28: those that 
central 


s Central Processor 
cannot be changed by 


init 


LK201 Keyboard 


RDN 


Specification 


— a SY it 


© N. a 


iagram 


2 


. 


KEYBOARD | 
LK201 Keyboard Circuitry, 


go. OC be oy 


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Simplified Block D 


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NN 


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LK201 Keyboard Specification 


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Power~Up Test 

Upon power-up, the firmware 5 ms a self-test ir 
ms. The test results are transmitted to the sys 
processor in four bytes 


1 less than 70 
stem's central 


The keyboard indicators are lit heen the self-test. The 
indicators blink once during the self-test routine. The indicators 
go off if the test is passed, but remain lit if the test fails. 


The system module can also request self-test at any time. 


5 | 
The keycodes represent fixed positions in the key switch matrix. 
The key associated with a * matrix position is always 


represented by the same keycode. 


Special Codes 


Thirteen special codes are transmitted by the keyboard. Four codes 
transmit the Paste of ihe power-up self-test. The other nine 
codes are status indicators or command acknowledgements. 


2 . Ch 
Instruction — The system's central sue 
instructions to change some keyboard transmis and es sea acteri stics 
and to control the keyboard indicators and beeper. 


anged by the 5 


. completion of a successful pover-up self-test, the firmware 

ets certain functi ions to predetermined conditions. These are 
5 to as "default" conditions. The conditions can be 
changed, but they sate ba come up to the default condition after a 


Successful power-up self~test. 


B.3.3.3 Firmware Functions That Can Be Changed — Certain 
Firmware functions can be changed by commands (instructions) hom 
the system's central processor. These commands are categori: 
stransmission® commands and peripheral“ commands. Transmis 05 
commands include a mode set command and an auto- repeat rate set 


command. Peri ipheral commands include a variety of commands. 


3. 4 DETAILED KEYBOARD CIRCUIT DESCRIPTION 
The following section describes the keyboard circuitry shown in 
Figure B-3. 


B. 4.1 Keyboard Matrix Scanning 
The key locations are arranged in an 18 X 8 line matrix. Each key 
Switch is connected across a matrix intersection. This gives a 
fixed position for each key connected in the matrix. This matrix 


pc 
accommodates all 105 keys in the LK201 keyboard. 


Figure B~-4 is a simplified block diagram of the matrix scanning 
circuit. Bight lines 10 5 port of the 8051 microprocessor go to 


1 Of 
the binary-coded decimal (BCD) inputs of two 74L8145 
BCD-to- decimal decoders. Ten outputs from one decoder and eight 
outputs from the other decoder provide the drive lines for the 
matrix. These 18 lines are called KB DRIVE 0-17. 


LK201 Keyboard Specification 


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[ 8051 | [ove 
F 7418145 
Saleen | DECODERS 


‘ 


(8 BCD ke 
INPUTS 961 
AND 18 | 18 LINES 
| DECIMAL | KB DRIVE 0-17 
| OUTPUTS) | 


BLINES s 
KB DATA Q—7 


TYPICAL SWITCH 
CONNECTION AT 
ae MATRIX 

e INTERSECTION 


MP 9908 


Figure B-4 Matrix Scanning Circuit, 
Simplified Block Diagram 


The other axis of the matrix consists of eight lines tied to +5 V 
through pull-up resistors. These lines go to port 0 of the 8051 
microprocessor and are called KB DATA 0-7. 


The 8051 microprocessor scans the 18 drive lines. Key closures are 
detected by reading the eight data lines. The complete matrix is 
scanned every 8.33 ms. When a_ key closure is detected, it is 
scanned again to verify that it is a key closure and not 
electrical noise. Once the key closure is verified, the 8051 
microprocessor firmware translates the position information into a 
keycode, and transmits it to the system's central processor. 
Transmission is handled by the universal asynchronous 
receiver/transmitter (UART) in the 8051 microprocessor. 


8—7 


LK201 Keyboard Specification 


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iON 


neo 


A "sneak path“ or “ghost key" indication can occur when three of 
the four corners of a matrix rectangle are closed, as shown in 
Figure B-5. The key positions in the matrix are arranged to avoid 
Sneak paths. However, if a sneak path does occur, the firmware 
prevents the keycode for the key (that caused the sneak path) to 
be transmitted until one of the involved keys is released. This 
prevents transmission of ghost keys entirely. 


Table B-1l shows the keyboard matrix on the LK201-AA (U. S. A.) 
keyboard. Keycap designations are shown for reference only and can 
be compared to Figure B~-6. 


| COND TIC 


INS ARE: SWITCHES B2, B3, AND C3 CLOSED, 
H C2 OPEN; LINE 215 BEING DRIVE N, AND LINE 
NG READ. 


8 R 


2. INTERSECTION C. 
SH 55 


21S BEING LOOKED AT. H SHOULD NOT 
OW A KEY CLOS E 


ISB ) 
URE BECAUSE SWITCH C2 IS OPEN. 


8 


3. HOWEVER, ASNEAK PATH IS PRESENT FROM LINE 2 
THROUGH SWI ITCHES B2, B, AND C3 TO LINE C. 
A GHOST KEY IS READ AT INTERSECTION C2. 
MIR Ooo 
Figure B-5 Example of Ghost Key Generation 


B-§ 


LK201 Keyboard Specification 


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Table B-1 Keyboard Matrix (LK201~AA) 


KB Data 
7 6 5 4 3 2 1 0 


MAD NADAS MAM MAMAN RATAN 


ee P eR ESOS ROEHTAS deute sR 


17 Reserved F19 Reserved F20 PF4 N — N, Enter 


16 F18 PF3 Reserved N9 V N6 N3 N 


15 F17 PF2 Reserved NS NS -> N2 NO 
(Note 2) 


14 PFI Next Remove 9 N7 N4 Nl NO 
| 
E20 18 E18 C17 20 C20 B20 A20 


13 Insert —— DO Prev { * Reserved Reserved 
Here — Screen [ g 
E17 E11 616 D1? Dil cll 


12 Find + Help Select Return <~ 


j 
] 
E16 E12 G15 D16 D12 913 816 C12 
11 Addtnl X Reserved) P (Note 3) : ? 
Options (delete) 0 : 
614 E13 E10 D10 C10 B10 


10 Reserved F12 Reserved F1l3 ( 0 L 8 
(BS) (LF) 9 
612 G13 E09 509 C09 809 


u 
go 


J 


9 Reserved Fll Reserved Reserved * 1 K j 
8 ; 
611 E08 DOs C08 808 


8 Reserved Main Reserved Exit N U J M 
Screen 7 
608 609 E07 DO7 C07 807 


c ILLES ASS AT TTT TT TEE EE NS ie MaRS ES 


B-9 


LK201 Keyboard 


NEN 


‘iia 


NOTES: 


1. 


7 


Reserved 


Reserved 


6 


Table B-1] 


6 


Cancel 
607 


Reserved 


Break 


603 


Lock 


C00 


Specification 


in 


Reserved 


Reserved 


Reserved 


a 


Reserved 


Reserved 


Compose 


A99 


SPER ASR LESS SE 


E00 


Reserved 


nene 


NO of the numeric keypad can be divided into two keys. 


NEE NESDIS ACRES SSE ESSE SPSS ESHER 


Note that NO--N9, N——, N, and N. refer to the numeric keypad. 


keyboard Matrix (LK201-AA) (Cont) 


SPACE 


A01— 
09 


Normally only the NO keyswitch is implemented as a double- Size key. 


3. The Return key occupies two positions that are decoded as the 


J 
Return { 


13) key. 


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LK201 Keyboard Specification 


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B „ 2 Audio Transducer Control Circuit 

Figure B-7 shows the audio transducer, or beeper, control circuit. 
The beeper is driven by a transistor whose base is connected to a 
2 kHz square wave from a 556 timer IC. This signal is biased by a 
network of four type 74LS05 open collector inverters. The 8051 
microprocessor controls all four inverters via the firmware. The 
on/off inverter connects directly to the transistor base. When the 
8051 microprocessor puts a high on the on/off inverter input, its 
output goes low and removes the 2 kHz square wave from the 
transistor base. This cuts off the transistor and disables the 
beeper. 


To turn on the beeper, the 8051 microprocessor puts a low on the 
on/off inverter input. Its output goes high and allows the 2 kHz 
Signal to reach the transistor base. This turns on the beeper. The 
firmware generates a keyclick (on for 2 ms) or a bell tone (on for 
125 ms). The 8051 microprocessor sets up the three level control 
inverters by putting one of eight binary combinations on the 
inverter inputs. All highs give the softest sound, all lows give 
the loudest sound. 


BEEPER 


74LS05 


2 CA 


F wl 
MR-1O000 


Figure B-7 Audio Transducer (Beeper) Control Circuit 


_ LK201 Keyboard Specification 


The firmware controls the keyclick and the bell tone 
independently. The bell tone is sounded only upon request from the 
system*’s control processor. The keyclick is sounded (unless 
disabled) under the following conditions. 


1. When a key is pressed. 
2. When a metronome code is sent. 


3. When a command to sound the keyclick is received from the 
system's control processor. 


B.4.3 Indicator (LED) Control Circuit 

Figure B-8 shows the LED indicator control circuit. The control 
signal for each LED goes from port 2 of the 8051 microprocessor to 
the input of a type 74LS05 open collector inverter. The inverter 
output goes to the LED cathode; its anode is connected to +5 V. A 
Separate +5 V source relieves the LED's load on the main +5 V 
supply. 


A low signal from the 8051 microprocessor drives the inverter 
output high, which cuts off the LED. A high signal from the 8051 
drives the inverter output low. This provides a path to ground 
From the +5 V through the LED. The LED then turns on. 


74LS05 
INVERTERS LEDS 


+5 V SUPPLY 
1120 


~ HIGH SIGNAL FROM 8051 PROVIDES 
PATH THROUGH LAST STAGE OF 
OPEN COLLECTOR INVERTER TO TURN 
ON LED. 


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Figure B-8 Indicator (LED) Control Circuit 


LK201 Keyboard Specification 


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B. 4. 4 Keyboard Communication 


B. 4. 4. 1 Keyboard Transmit Mode — The keyboard codes and a few 
other special codes are transmitted via a serial line output in 
port 3 of the 8051 microprocessor. The transmitted signal goes 
from the 8051 microprocessor to a driver, through the keyboard 
cable, monitor, and video cable to the system's central processor. 
A UART within the 8051 controls the transmission. 


Transmitted charact 
character is 10 bits 
always a logical 0 

encoded data. The last 
1 (mark). Figure B-9 shows 


nform to a specifi format. Each 
„ The first bit is the START bit. It is 
ace). The next eight bits represent the 
is the STOP bit. It is always a logical 
the character format. 


— | os mah J TL | oe eee 
bag “ago bea, f mg gy 


MARK (1) — ror Toro saa et cad — 


f i | i 
SPACE (0) LJ — 4. — 3 a 1 = 


BART OOO? 


Figure B-9 Keyboard Transmit and Receive Character Format 


si 


B. 4. 4. 2 Keyboard Receive Mode ~~ The firmware contains features 
that can be enabled by commands from the system's central 
processor. There are two categories of features: one sets keyboard 
transmission characteristics, the other controls the keyboard 
peripherals. A peripheral command covers indicator control, bell 
and keyclick volume, keyboard ID code, and reinstate keyboard. The 
commands come from the system's central processor, through the 
video cable, monitor, and keyboard cable to the receiver, and into 
the 8051 microprocessor via port 3. They go to the UART in the 
8051. 


Received characters conform to the same 10-bit format used for 
transmitted characters. The eight data bits are arranged in a 


specified protocol 5 on the command type. 


B-14 


_Lke01 Keyboard Spec) fication 


B. 4.5 Reset Signal for the 8051 Microprocessor 
Whenever the system is turned on, the 8051 microprocessor in the 
keyboard must be reset. This allows the 8051 to start operating. 


The reset signal generator is active only during power-up. The 
input is +5 V. The output is connected to the reset input of the 
8051. When power is turned on, the +5 voltage starts to rise from 
zero. The reset signal circuit output follows it, and drops off 
when a steady state of +5 V is reached. This circuit holds the 
8051 reset input high (+3.5 V to +5 V) long enough to enable the 
reset action in the 8051. This action occurs only during power-up. 


B. 4. 6 Hardware Keyboard Identification (ID) 

At power-up, the keyboard performs a self-test and sends the 
results to the system's central processor. One piece of 
information to be sent is the keyboard hardware ID, which is read 
from hardwired jumpers. 


There are six jumpers. Each jumper line goes from an input in port 
3 of the 8051 microprocessor to ground. All jumpers are installed 
so the keyboard hardware ID is zero. 


B.4.7 Voltage Supplies 
The only voltage sent to the keyboard is +12 V. However, +5 V and 
~10 V are also needed. These voltages are derived from the +12 V. 


A +5 V supply handles most of the requirements for this voltage. 
The four keyboard LEDs have their own +5 V supply. A -10 V supply 
provides voltage for the driver in the serial out line. 


B. 5 KEYBOARD PROGRAMMING 

This section describes the functions the keyboard performs under 
System central processor control. It also describes keyboard 
programming machine language. High-level user programming is not 
described here. 


B 1 Keyboard Layout and Key Identification 

Each keyboard key has a unique location. Each location is scanned, 
and when closure or release is detected, the location is verified. 
This is then decoded to an 8-bit keycode. Figure B-6 shows the 
keyswitch locations. Table B-2 lists the 14 functional divisions 
of the keyboard. Table B-3 lists the divisions, keycaps, and 
keycodes. 


B-15 


LK201 Keyboard Specification 


me 


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Division 


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1 


2 


B-16 


Table B-2 


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Description 

je graphic keys, epacebar 
Numeric keypad 

Delete character (E12) 
Return (C13) Tab (DOO) 

Lock (COO) Compose (A99) 
Shift (B99 and Bll), Ctrl (C99) 
Horizontal cursors (B16 and B18) 
Vertical cursors (B17 and C17) 


Six keys directly above the cursor 
keys (D16-D18 and E16-E18) 


Function keys (G99-G03) 
Function keys (605-609) 
Function keys (611-614) 


‘ie 


Function keys (G15-G16) 


Function keys (G20-G23) 


dae webe, 


Keyboard Functional Divis ions 


dee 


0001 


0010 
0011 
0100 
0101 
0110 
0111 
1000 


1001 


1010 


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Representation 


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LK201 Keyboard Specification 


Table B-3 Keycode Translation Table 


e e f ep ORONO TROIS 


Keycode** Keycode 
Division Position Keycap* (decimal) (hexadecimal) 


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FUNCTION KEYS 


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10 G99 Hold Screen 086 56 
600 Print Screen 087 97 
601 Set-Up 088 58 
602 F 4 089 59 
603 Break 090 5A 
Reserved 091-098 5B-62 


ed 


11 Reserved 099 63 
605 Interrupt 100 64 
606 Resume 101 65 
607 Cancel 102 66 
608 Main Screen 103 67 
609 Exit 104 68 
Reserved 105-110 69-6E 


12 111 6F 
Reserved 112 70 
Gll Fll (ESC) 113 71 
612 F12 (BS) 114 72 
613 F13 (LF) 115 73 
614 Addtnl Options 116 74 
Reserved 117-122 75-7A 


13 Reserved 123 7B 
G15 Help 124 7C¢ 
G16 Do 125 7D 


14 Reserved 126-127 7E-7F 
G20 F17 128 80 
621 F18 129 81 
622 F19 130 82 
G23 F 20 1 83 
Reserved 132-135 84-87 


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9 Reserved 136- 137 88-89 

E16 Find 138 8A 
E17 Insert Here 139 8B 
E18 Remove 140 BC 
D16 Select 141 8D 
D17 Prev Screen 142 8E 
18 Next Screen 143 8F 

Reserved 144 90 


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8-47 


LK201 Keyboard Specification 


Table B-3 


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Division Position _Keycap* 


aucune, 


NUMERIC KEYPAD 


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2 


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5 NS CLD ERA a NES FERN RAR OSHA 


Reserved 
0 
Reserved 


8 


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SS teueren ene 


ii 


OOH unebenen 


Fee 
(decimal) 


ii psn HEA RHONA 


iii num aga UN 


777. e aR SAD ee eRe 


Keycode Translation Table (Cont) 


damen DFR Meaba gOS PRONG OSA ASN CR OUP 


ee 
(hexadecimal) 


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Ce ebene enen ene eee demande eee eee ba dae sess ng assure enk dae eee bee wenden spe beam une ddulbehbbe ben, 


Reserved 
Left 
Right 


7 
B16 
B18 


817 
C17 


Down 
Up 
Reserved 


AON SREB NAL SR 


SHIFT, 1 TRE, A99, 


6 Reserved 
Shift 
Ctrl 


399,811 
C99 


C00 
A99 


Lock 
Compose 
Reserved 


Wi 


en 


3-18 


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and 3 


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＋＋＋＋ꝓPP 


LK201 Keyboard Specification 


Table B-3 Keycode Translation Table (Cont) 


＋＋＋＋＋＋＋＋Hꝓ——-— oD GAR ROONO RUNNERS HNO OHAIE ALO RMON 


Keycode** Keycode 
Division Position Keycap* (decimal) (hexadecimal) 


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SPECIAL CODES 
All Ups 179 
Metronome 180 
Output Error 181 
Input Error 182 
KBD LOCKED 183 
Acknowledge 
TEST MODE 184 B8 
Acknowledge 
PREFIX to keys 185 B9 
Down 
MODE CHANGE 186 BA 
Acknowledge 
Reserved 187 BB 


DELETE 


e p ESS GN eh Ue eS AGN J GS ORLA LBB ORDO ROSSINI INULIN 


3 E13 Delete x 188 BC 


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RETURN and TAB 


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4 C13 Return 189 BD 
DOO Tab 


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48 GRAPHICS KEYS and SPACEBAR 


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2 E00 ~ 191 BF 
E01 14 
DO] 0 . 
Col A 194 C2 
B01 2 ae 
Reserved 196 (4 
E02 @ 197 5 
902 * 198 C6 
C02 8 199 8 
802 X 200 C8 
BOO 50 201 9 
Reserved 202 CA 
E03 #3 203 CB 
DO3 E 204 CC 
C03 D 205 CD 
B03 C 206 CE 
Reserved 207 CF 


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LK201 Keyboard Specification 


nennen 


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Keycode** Keycode 
Division Position Keycap* (decimal) (hexadecimal) 


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804 


$4 208 DO 
DO4 R 209 Dl 
C04 F 210 D2 
V 211 D3 
Space 212 D4 
Reserved 213 D5 
E05 $5 214 D6 
DO5 15 215 D7 
C05 G 216 D8 


305 B on Ne DY 


Reserved 218 DA 
E06 “6 219 DB 
06 Y 220 DC 
C06 H 33 DD 
B06 N 222 DE 


1 Reserved 223 DF 
8 7 224 EO 
U 225 El 
J 226 E2 
B07 N 227 E3 
Reserved 228 E4 
*8 229 5 
I 230 E6 
C08 K 231 E7 
B08 N 232 E8 
Reserved 233 E9 
E09 (9 234 EA 
909 0 235 EB 
C09 L 236 EC 
309 0 237 ED 
Ne 238 EE 
E10 0 239 EF 
10 P 240 FO 
Reserved 241 Fil 
2 242 F2 
B10 2 7. 243 F3 
Reserved 244 F4 
E12 + = 245 FS 
D12 } ] 246 F6 
C12 N 247 F7 
Reserved 248 F8 


e AON O TRAKONNIO TED NOSSO NOMINATION RIBS 


B-20 


LK201 Keyboard Specification 


Table B—3 Keycode Translation Table (Cont) 


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Keycode** Keycode 
Division Position Keycap* (decimal) (hexadecimal) 


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Ell ees 249 F9 

911 1 1 250 FR 

(11 2 4 251 FB 
Reserved 252-255 FC-FF 


1 


SHURE 


MBM MIAO AMOR SNM STROSS IASI ueber eee mee DIE: 


* The legends under Keycap are taken from the keycap legends of 
the LK20 1-AA (U tp 8 ite A 5 ‘te 


** Keycodes 000 through 064 are reserved. Keycodes 065 through 085 
are unused. 


B.5.2 Modes 

This section describes the functions of the keycode transmission 
modes. The mode set command allows any 1 of the 14 keyboard 
divisions to be set to any 1 of the following 3 modes. (Division 
defaults are described in subsequent paragraphs.) 


1. Down-Only Mode The keyboard transmits a keycode when the 
key is pressed. 


2. Auto-Repeat Down The keyboard transmits a keycode when the 
key is first pressed. If the key is held 
down past the specified timeout period 
(usually 300 to 500 ms), a fixed metronome 
code is sent at the specified rate until 
the key is released. 


3. Down/Up The keyboard transmits a keycode when the 
key is pressed and an up code when the key 
is released. If any other down/up keys are 
pressed, the up code is a repeat of the 
down code. If no other down/up keys are 
pressed, the keyboard sends an ALL UPS 
code. 


B.5.2.1 Special Considerations Regarding Auto-Repeat — The 
auto-repeat rate set command allows the following changes in 
auto~repeat mode: 


1. The auto-repeat rate buffer association can be changed for 
the selected keyboard division. 


2. The timeout and interval values can be changed in any one 
of the four auto-repeat rate buffers. 


LK201 Keyboard Specification 


ee 


B-22 


5 CPC 


If multiple auto- repeating keys are held down, metronome 
codes are still generated. The metronome codes apply to 
the keycode transmitted most recently. If the last key 
pressed down is released, and another key is still down, 
the keycode of the key still down is retransmitted. 


Example: The A key is held down. 
This produces the following transmission. 
A metronome metronome 


Now the B key is pressed. This produces the following 
transmission. 


A metronome metronome B metronome metronome 


Now the B key is released. This produces the following 
Oo 


A metronome metronome B metronome metronome A metronome 


ee e, oo 


While metronome codes are being generated for an 
auto-repeating key, a nonauto-repeating keycode or special 
code may be transmitted. The keyboard transmits this 
special code instead of the next metronome code, and then 
returns to the auto-repeated code. The keycode to be 
auto~repeated is always the last byte transmitted. 


4 


Example: The A key is held down. 
This produces the following transmission. 
A metronome metronome 


Now the shift key is pressed. This produces the following 
transmission. 


A metronome metronome shift A metronome 


Now the shift key is released. This produces the following 
transmission. 


A metronome metronome shift A metronome ALL UPS A 
metronome met 


If an auto-repeating key is not to auto-repeat (for 
example, Ctrl C), the system module must issue a temporary 
inhibit auto-repeat command. This halts the transmission 
of any metronome codes or keyclicks for that key only. 
Metronome codes continue when another key is pressed. The 
command must be issued after the keycode for the 


a 


auto~repeating key is received. 


LK201 Keyboard Specification 


5. Auto~repeat can be enabled and disabled independently of 
the division settings by using the enable/disable 
auto-repeat commands. These commands apply to all keys on 
the keyboard. When auto~repeat is disabled, the keyboard 
continues to auto-repeat characters internally. However, 
it does not transmit metronome codes or keyclicks. When 
duto- repeat 18 enabled, the keyboard transmits the 
metronome codes from the point where they were before 
auto- repeat vas disabled. This may be within either the 
timeout or interval period, depending on the time elapsed 
Since the key was pressed. 


6. If the keyboard receives a request to change a division 
mode to auto-repeat while a key is being pressed, the 
keyboard makes the change immediately. After the specified 
timeout period, the keyboard transmits metronome codes for 
the pressed key. In place of the first metronome code, the 
keyboard transmits the keycode of the auto-repeating key. 


All auto-repeating division modes can be changed to down-only with 
one command. This and other auto-repeat commands are grouped with 
the peripheral commands. 


B. Special Considerations Regarding Down/Up Mode — If two 
down/up keys are released simultaneously (within the same scan), 
and there are no other down/up keys down on the keyboard, only one 
ALL UPS code is generated. 


Bs. 5s203 Auto-Repeat Rates -- Four buffers in the keyboard, 
numbered 0 through 3, store auto-repeat rates. Each buffer stores 
two values, which can be changed by the system module: 


1. Timeout value 
2. Interval value. 


Timeout is the amount of time the keyboard vaits before starting 
to auto-repeat a character. The timeout value is the amount of 
time between the detection of a down key and the transmission of 
the first metronome code. (Defaults range from 300 to 500 ms.) The 
rate of auto-repeating a character is called the "interval." The 
interval value is the number of metronome codes per second 
(defaults to 30). 


Each division is associated with one of the four buffers. Rates 
are taken from the associated buffer each time the auto~-repeat 
timers are loaded. This buffer-to-division association can be 
changed by the system module or left to default. 


B. 5.3 Keyboard Peripherals 

This section describes the peripherals available on the keyboard. 
The keyclick, bell, and LEDs are all considered keyboard 
peripherals. 


LK201 Keyboard Specification 


aendern elle merke 


B Audio —— The keyclick is a 2 ms beep; the bell is a 125 
ms beep. The bell is sounded only upon request from the system 
module. The keyclick (if not disabled by the system module) is 
sounded when: 


1. A key is pressed 
2. A metronome code is sent 
3. The system module receives a sound keyclick command. 


Tf either the Bll or B99 key (the left or right shift key on the 
LK201) or the C99 key (the Ctrl key on the LK201) is pressed, the 
keyclick is not generated. However, if a command is sent from the 
System module to enable the keyclick on the C99 key, the keyclick 
is generated. Figure B-6 shows the positions of these keys. 


The keyclick or bell (or both) may be disabled not to sound. If 
the system module requests sound (see Paragraph B.5.5.3), the 
keyclick or the bell does not sound. 


Both the keyclick and bell may be set independently to one of the 
following eight volume levels: 


000 ~ highest 
001 
010 - default 


lll — lowest 


B. 5. 3.2 Indicators (LEDs) — The system module normally transmits 
indicator control commands. However, the following are exceptions. 


pd 
* 


Upon power-up, the keyboard turns all LEDs off. 


0 


After receiving the inhibit transmission command, the 
keyboard turns on the lock LED. The LED is turned off 
after the keyboard receives a resume transmission command. 


B. 5. 4 Keyboard-to-System Module Protocol 
The following paragraphs describe the keyboard-to-system module 
protocol. 


B.5.4.1 Keycode Transmission -- The keyboard transmits single- 
byte keycodes that reflect the keyboard matrix status. The 8-bit 
codes above 64 (decimal) are used for keycodes. Every key is 
identified by a unique keycode. There are no special codes for 
shifted or control keys. 


Refer to Figure B-6 and Tables B-1 and B-2 for the complete 
keycode matrix translation table. 


B-24 


_LK201 Keyboard Specification 


B.5.4.2 Special Code Transmission — There are 13 special codes: 
9 codes with values above 64 (decimal) and 4 codes below. Table 
B-4 lists the nine special codes above the 64 (decimal) keycode 
value range. Table B-5 lists the four special codes below the 64 
(decimal) value range. 


Table B-4 


pinion OE RECO SHA ONROSFSIHIES 


Special Codes Above 64 (Decimal) 


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Keycode 
Special Codes (Decimal) 
All Ups 179 B3 
Metronome Code 180 84 
Output Error 181 BS 
Input Error 182 B6 
KBD Locked ACK 183 B7 
Test Mode ACK 184 BS 
Prefix to Keys Down 185 B9 
Mode Change ACK 186 BA 
Reserved 127 7F 


i ear e SKE RENONNRSHRNS EE OEUNDHOMHONEH=PORTEERTO — . e D —T OARS SANT 


(Hexadecimal) 


. 
aoe ERRONEOUS SLASHES een denen NEDSS DIBA G EN AMECE SIENNA IEE IODIDE 


All Ups — Indicates to the system module that a down/up mode key 
was just released and no other down/up keys are being pressed. 


Metronome Code — Indicates to the system module that an interval 
has passed, a keyclick has been generated, and the last key 
received by the system module is still being pressed. 


Output Error — Indicates an output buffer overflow to the system 
module. The overflow occurred after receiving a keyboard inhibit 
command from the system module and some keystrokes may be lost. 


Input Error Code —— Indicates to the system module that the 
keyboard received a meaningless command, too many, or too few 
parameters. 


Keyboard Locked Acknowledge -- Indicates to the system module that 
the keyboard received an inhibit transmission command. 


Test Mode Acknowledge -~ Indicates that the keyboard has entered 
test mode. This is a special mode used during the production test. 
If the system module receives this acknowledge, it sends 80 
(hexadecimal). This terminates the test mode and Jumps to 
power-up. 


Prefix to Keys Down — Indicates that the next byte is a keycode 
for a key already down in a division that has been changed to 
down/up. 


Mode Change Acknowledge -- Indicates that the keyboard has 
received and processed a mode change command. 


Reserved -- Keycode 7F is reserved for internal use. 


LK201 Keyboard Specification 


Table B—5 Special Codes Below 64 (Decimal) 


Keycode 
Special Codes (Decimal) (Hexadecimal) 


Keyboard ID -- Firmware 01 01 
Keyboard ID — Hardware 00 00 
Key Down on Power-Up Error Code 61 3D 
Power-Up Self-test Error Code 62 3E 


is Ensen enen Sane ENEMAS oo me eee uud A eSATA SSPE RS DSN DRE HU OO SE 


Keyboard ID -- This is a 2-byte identification code, transmitted 
after the power-up self-test (power-up transmission). It is also 
sent on request from the system module. 


Key Down on Power-Up Error Code —— Indicates that a key was 
pressed on power-up. 


Power-Up Self-Test Error Code — Indicates to the system module 
that the ROM or RAM self-test of the system module failed. 


B. 5. 4.3 Power -Up Transmission —— Upon power-up, the keyboard 
performs a self-test in less than 70 ms. It transmits the 
self-test results to the system module in 4 bytes. 


Byte 1: KBID (firmware) —— This is the keyboard identification 
(ID) that is stored in the firmware. 


Byte 2: KBID (hardware) — This is the keyboard ID that is read 
from hardware jumpers. 


Byte 3: ERROR —— Two error codes indicate either failure of the 
ROM or RAM self-test within the processor (3E 
hexadecimal), or key~down on power-up (3D hexadecimal). 
No error is indicated by 00. 


Byte 4: KEYCODE — This byte contains the first keycode detected 
if there was a key down on power-up. No error is 
indicated by 00. 


If the ROM self-test (CHECKSUM) fails and the error is fatal, the 
keyboard is unable to transmit. Nonfatal errors permit the 
keyboard to continue operation. 


LK201 Keyboard Specification 


If the keyboard finds a key down on the first scan, it continues 
to look for an ALL UP condition. The keyboard sends the corrected 
4-byte power-up sequence when the pressed key is released. This 
avoids a fatal error condition if a key is pressed by mistake 
while powering up. 


The keyboard LEDs are lit during the power-up self-test. If the 
self-test is passed, the keyboard turns the LEDs off. If a bell is 
selected on power-up, the system module can transmit a sound bell 
command to the keyboard. However, this should not be done until 
the system module receives the last byte of the 4-byte sequence. 
The request for self-test tests the serial line and system module 
connection. The power-up self-test takes 70 ms or less. 


The system module can request a jump to power-up at any time. This 
causes the LEDS on the keyboard to blink on and off (for the 
power-up self-test). 


B.5.5 System Module~to-Keyboard Protocol 

The system module controls both the peripherals associated with 
the keyboard and the keyboard transmit characteristics. Figure 
B—10 shows the protocol for the transmission of commands and 
parameters from the system module to the keyboard. 


COMMAND 


RAPT ONS 


Figure B-10 system Module-to-Keyboard Protocol 


LK201 Keyboard Specification 


ce 


Command Types 


Transmission Commands Peripheral Commands 


Mode Set Flow Control 

Auto- Repeat Rate Set Indicator 
Audio 
Keyboard ID 
Reinitiate Keyboard 
Some Auto- Repeat Control 
Jump to Test Mode 
Reinstate Defaults 


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Oeil Commands — Table B-6 lists the two kinds of commands: 
those that control keyboard transmission characteristics, and 
those that control keyboard peripherals. The low bit of the 
command is the TYPE flag. It is clear if the command is a 
transmission command; it is set if the command is a peripheral 
command. 


The high-order bit of every command is the PARAMS flag. If there 
are any parameters to follow, this flag is clear. If there are no 
parameters, this flag is set. 


B. 5.5.2 Parameters — The high-order bit of every parameter is 
the PARAMS flag. It is clear if there are parameters to follow. It 
is set on the last parameter. The remaining seven bits of the 
parameter are for data. 


B. Peripheral Commands — Two commands can turn the data 
flow from the keyboard off and on: 


1. Inhibit Keyboard Transmission -- This command shuts off, 
or locks, the keyboard and turns on the lock LED. After 
receiving the inhibit command, the keyboard sends a 
special command to the system's central processor. If the 
central processor receives this code without requesting 
it, this indicates that noise on the line was interpreted 
as the inhibit command. The central processor then 
responds immediately with the resume keyboard transmission 
command. 


2. Resume Keyboard Transmission -- This command turns on, or 
unlocks, the keyboard and turns off the lock LED. If any 
keystrokes are lost, the keyboard responds with an error 
code. 


_ LK201 Keyboard Specification 


Each keyboard LED can be turned on and off. The following are the 
eight commands that control the keyclick and bell sounds. 


The 


= = 


«„ M a „ * 


fol 


Disable Keyclick 

Enable Keyclick and Set Volume 
Disable Ctrl Keyclick 

Enable Ctrl Keyclick 

Sound Keyclick 

Disable Bell 

Enable Bell and Set Volume 
Sound Bell 


lowing four commands are related to the control of 


auto~repeat mode. 


1. 


4. 


Temporary Auto-Repeat Inhibit — Auto- repeat is stopped 
for a specific key only. It resumes automatically when 
another key is pressed. 


Enable Auto-Repeat Across the Board -- Starts transmission 
of metronome codes without affecting auto-repeat timing or 
keyboard division. 


Disable Auto-Repeat Across the Board -- Stops transmission 
of metronome codes without affecting auto-repeat timing or 
keyboard division. 


Change All Auto-Repeat to Down-Only -- Changes all 
keyboard auto-repeating divisions to down-only mode. 


The following are three other miscellaneous commands. 


To 
Bits 
Bits 


1. 


send 


6- 


2 


Request Keyboard ID — The keyboard sends the 2-byte ID 
(firmware and hardware). The keyboard does not jump to the 
power-up sequence. 


Reinitiate Keyboard -- The keyboard jumps to the power-up 
sequence. Transmission to the keyboard should be held 
until the host processor receives the last byte of the 
power~up self-test. 


Reinstate Defaults -~ Sets the following functions back to 
the default settings after a successful completion of the 
power-up self-test. 


Division mode settings 

Auto-repeat interval and timeout rates 
Auto-repeat buffer selections 

Audio volume 

Ctrl key keyclick 


a peripheral command, set the TYPE flag (low-order bit). 
3 contain a command representation from the table below. 
and 1 specify on (01), off (00), or sound (11). Bit 7 


should be set if there are no parameters to follow. 


B-29 


LK201 Keyboard Specification 


VVV 


Table B-7 lists the peripheral commands (in hexadecimal) and Table 


B-8 indicates the representation for each command function. 
The jump to power-up command is FD (hexadecimal). 


The following are some of the peripheral commands. 


1. Flow Control -- The system module can lock the keyboard 
with the inhibit keyboard transmission command. When the 
keyboard is unlocked, it responds with an error code if 


any keystrokes were missed. 


Table B-7 Peripheral Commands in pesados smal 


e HERS OND EOI RONDA NIEDN RSDP APOGEE SEDER ENO RUN HUH AROS ONSEN ARON NHRD 


Function Hexadecimal Parameters 


F MELANOMA SEDI DL LENO NLEASES TRALEE AAO DAE A LAL NSIS SLES SSR SENSEI 


3 ne 


buen len oben . . e AES p p p p . SESE BELSON ONE PIO RO 


Res ume r Transmission 8B None 
Inhibit . Transmission 89 None 


souvent oni eRNRTDUIONOID;UENP HEIDI ABSA NERO HANUMAN 


r t PE SER SB CDA See OS eae aI OSDIR ARPANSA OURO NN: 


INDICATORS ~ 


Light LEDs 13 Bit pattern 
aon ae EDS 11 Bit B 


ee bbb der enn, bucebouLeredatblr u dkbgoden bennett keln teeleentbeeanee amal 


AUDIO 


psn 


ANSEHEN 


nts ennai @n son insects I Ne eG NS ORHADAFANN NOLO 


Disable Keyclick 99 None 
Enable Keyclick, Set Volume 1B Volume 
Disable Ctrl Keyclick 89 None 
Enable Ctrl Keyclick BB None 
Sound Keyclick 9F None 
Disable Bell Al None 
Enable Bell, Set Volume 23 Volume 
Sound Bell A7 None 


e r OEP MOND OR RBIS Na OAR O AOS NNERNPSUSANNOLRTORNERIAER RONSON 


AUTO- 1 


aterm yo ssa ee SS ROSS SSO RS SUNT i NS ORDERS EON DOONAN ARID ERODED ETSAROANNNIEINERURNNAA SDPO. 


Temporary Auto-Repeat Inhibit C1 None 
Enable Auto- Repeat Across Keyboard E3 None 
Disable Auto~Repeat Across Keyboard El None 
nang: All Auto- n to Down- Rae D9 None 


<i ce rss = AOU HSA SIERRAS i Ok A ENERO OES PE A oS SAC EURO SN 


OTHER 


e t r te UU es OSORNO eon ALR RONAN EMSC DARGA ARISEN 


Request Keyboard ID AB None 
Jump to Power-Up FD None 
Jump to Test Mode CB None 
Reinstate Defaults D3 None 


ssc ee LE i ERNE EGER Sec GSTS SEU PSUR USSSA SOS ERS NSS ESE CASS DAN eR Ra RS ANAND 


B~-30 


LK201 Keyboard Specification 


eee i ee ee eee se 


ebnen emed 


Table B-8 Command Function Representation 


Command 

Flow Control 

Indicator (LEDs) 

Keyclick 

Bell 

Keyboard ID 

Keyclick for Ctrl Key 

Temporarily Inhibit Auto~Repeat 

Jump to Test Mode 

Change All Auto-Repeat Characters 
to Down-Only 

Enable/Disable Auto~Repeat 1100 


a 


Representation 


2. Indicators (LEDs) —— Figure B-11 shows the LED parameter. 
Figure B-—12 shows the LED layout on the LK201 keyboard 
without the label strip installed. 


3. Audio — Figure B-13 shows the audio volume parameter. 


F- OOO 


Figure B-—11 Indicator (LED) Parameter 


MAF) OOS 


312 Indicator (LED) Layout 


eee 


Figure B-13 Audio Volume Parameter 


sonst woc oe — . p . ST TAA STS 


ee wu emeunkume, 


LK201 Keyboard Specification 


eee ONRIROMONETNUKONRKOnEMEHIMNOONATONNONAORNADNENNRIRENREANRONI 


The 


sys 


The following are additional 


4 t 


volume 


} IBN: 


i 
cli 
em oor 


th 


4 ie R e 


ID 


ule 


levels 


lowest 


ick 
or 


Temporary 
key 
another key is 


is 


2. Disable/Enable 5 
transmission 
Auto- repeat 


Change t 
settings for all 


quest 


or 
pell is d 
reque 


All 


Keyboard II 
Keyboard does not 


ane een 


for the audio are as follows. 


the be both) 


11 (or 
8 Ge 


co 
isabled, 
Les 


does 
sts 


peripheral 


4 5 ‘is zune 


Inhibit 
Auto~repeat automat 


Auto~Repeat 
only. 


5 mo 1 


ome codes 


Vision 


o 
ra 
3 
oo 

8 re 5 
. 
0 

7 3 


to 
auto~repeating 


Auto-Repeat 


jump to power-up. 


sii pt 


can be disabled. When 
not sound, 


settings. 


Down-Only —— 


ID — Keyboard sends 


ee 


the 


even if the 


commands, 


ops auto-repeat f 
cally continues 


or 
when 


Across Keyboard -- Stops/starts 
without 


affectinc 


Changes division 
to down-only. 


a 2-byte keyboard 


i 
The system 
to the 
sequence 


Keyboard jumps to its power-up 
module should not try to transmit 
keyboard until the last byte of the 
is received. 


Test Mode — Special test mode for manufacturing 


back to 
of the 


the following 
“er a successful 


ee mode settings 

~repeat 5 and timeout 
5 buffer selections 
lio volume 

key keyclick 


rates 


LK201 Keyboard Specification 


Ce nehmen, 


B.5.5.4 Mode Set Commands -- The following describe the mode set 
commands. 


1. Division mode settings — Refer to Paragraph B.5.2. 


2. Each division on the keyboard has a unique 4-bit 
representation. Table B-2 describes these representations. 


3. Each mode has a unique 2-bit code as indicated in Table 
B-9 ® 


To set the key transmission mode on a particular keyboard 
division, the system module must send the PARAMS flag, then the 
keyboard division representation with the mode code, and then 
the TYPE flag (cleared). 


Example: Set main array to down/up. Refer to Figure B-14. 


The PARAMS flag is set to 1 if there are no parameters. The PARAMS 


flag is clear if there are parameters. 


Table B-9 


. c STILE SNR T ANITA NII 


lode Representation 


oases aes MMPS SLI LAETITIA 


Modes Representation 


. e ESSAI III eee ednet wm 


Down-only 00 
Auto~repeat down 0 
Down/up 1] 


. . AAAI SOLARA STRANDS . e PIANIST 


a ye yk 
DIVISION MODE fe 


MR-TOOO7 


PARAMETER 


Figure B-14 Setting Key Transmission Mode 


LK201 Keyboard Specification 


neat knee el 


NPM 0 . e HANAN INCH NSTER CEASE HRN Aa RRR ORAS TR HSASHSIIO HON Hae ORG oan omenensansmbNnpe 


Auto-repeat rate buffer association -- If the auto-repeat mode is 
Selected, the system module can transmit a parameter to change the 
buffer association of the selected division 


Example: Set main array to auto-repeat, 
] 4 : 1 
to buffer 3. Refer to Figure B-15, 


Auto- “repeat rate b 
Ur auto~-repeat 
nodule may change t 


re 

FFs 

Se 

re 
an 

Pes 
* 
2 

Fe 

sue 

if 

i 

4 
is 
= 

{> 
~~ SS 
0 5 
= 8 
888 

re 
or 
8 8 
. 

Le 

85 
=e 

i 

8 
ee 
0 
“dl 
F% bede 
= 

a | 

© 

ee 


8 8 


In the command byte, bi 
are 1111 (to indicate tha 
1 should be the buff 
Clear. There should be tw 


PARAMS flag) should be reat bi 
is ze a rate set command 
Um 
ara 


~*~ 
aod 
ow 
= 
gage 
one 
Sek 


Co 
be (0 to 3), bit 0 (TYPE 3) i: 
me eee carrying the rate set data. 
Example: Change rates in buffer 3. Refer to Figure B-—16. 


he Store in the 


The first parameter specifies the timeout to t 
2] 0 > the interval. 


elected buffer. The second 


PARAMETEF DIVISION MODE TYPE 
g 4 — se es ue! FV — ian 3 7 — 


07 06 05 04 03 02 01 00 


FFF ieee e eee 
0 0 0 | 0 
4 a 

=n cme VF ine 
| . i J 


0 0 0 0 0 1 1 


ew J 0 Lee ae eee ee ea Tee Seen e 


Figure B-15 Setting Auto~Repeat Rate Buffer Association 


— os om maden deko wem; int muae o wheels eR e rene Ge 


* 6. 1 i 1 ene ay, cd Hie * 


05 04 03 02 01 00 


ieee eee eee e 


1 | 0 


AONE u nn * ig 


AAA TESS LE HS LINERS ASTI AS IBIS ESN SNES OSES SOS SHOES HOUTEN ERECT RE A GS AO ROSA O 


PARAMETER 2 (INTERVAL) 
i ne | 


MP-10009 


Figure B-16 Setting Auto~Repeat Rate Buffer Values 


re 
te 
i 
ee 
He, 


LK201 Keyboard Specification 


r ai ina Sad NU NOS iii iia iii tne NN NMDA 


aC 


co. 


For example, to set the auto~repeat rate in buffer 1, the system 
module firmware transmits 00000011, followed by 2 bytes of numeric 
parameters. 


The auto-repeat timeout is the transmitted number times 5 ms. To 
specify a rate of 5 ms delay, the first parameter received is 
00000001. The maximum allowable time is 630 ms (01111110). The 
system module must not send 635 (01111111). 


NOTE 
le (01111111) is reserved for 


The cod 
internal keyboard use. 00 is an illegal 
value. 


Auto- repeat timeout is implemented as a multiple of 8.33 ms, the 
keyboard's internal scan rate. Timeout rates can vary + 4.15 ms. 


The auto-repeat interval is the number of metronome codes per 
second. In order to specify a speed of 16 Hz, the second parameter 
received is 10010000. Note that the high-order bit is set because 
it is the last parameter. The highest value that may be sent is 
124 (11111100). 


The lowest rate that can be implemented by the keyboard is 12 Hz 
Values as low as 1 can be transmitted, but are translated to 1 
HZ. 


ae 
ay 
2 


NOTE 
The system module must not send 125, or 
11111101. This code is the power-up 
command. 


B. 5. 6 Special Considerations | 
The following paragraphs describe the special codes and their 
considerations. 


B.5.6.1 Error Handling — There are four error codes. The first 
two are sent at power-up if the self-test fails. The other two are 
the input error code and the output error code. 


The output error B5 hexadecimal) is sent after the keyboard 
receives a resume transmission command, if the output buffer 
overflowed while the keyboard was locked. 


The input error (B6 hexadecimal) is sent when the keyboard detects 
noise (an unidentified command or parameter) on the line. B6 is 
also sent if the keyboard detects a delay of more than 100 ms 
while expecting a parameter. 


B-35 


LK201 Keyboard Specification 


Pe 


iene HNN 5 noe 


B.5.6.2 Keyboard Locked Condition -- When the keyboard receives 

an inhibit transmission command, it lights the lock LED Ane 
transmits one more byte - a special code indicating the keyboard 
is locked (keyboard locked acknowledge). If the system module 
receives this code without a request, noise on the line was 
interpreted as an inhibit transmission command. The system module 
should immediately send the resume transmission command to unlock 
the keyboard. 


The output first-in/first-out (FIFO) buffer in RAM is four bytes. 
When the keyboard is locked, the ee attempts to store 
characters received from the keyboard. The keyboard stops scanning 
its matrix. When the keyboard is unlocked by the system module, it 
transmits all four bytes in the output buffer. If any keystrokes 
were missed due to buffer overflow, the keyboard transmits an 
error code as the fifth byte (output error). Keys that were not 
transmitted and are being held down when the keyboard is unlocked 
are processed as new keys. Upon unlocking the keyboard, an error 


code indicates a possible loss of keystrokes to the system module. 
The keyboard stops scanning its matrix when its buffer is full. 
However, it processes all incoming commands. 


B. d. Reserved Code ~~ The number 7F (hexadecimal) is reserved 
for the internal keyboard input and output buffers handling 


routines. 


B. 5. 6. 4 8 ~~ The keyboard jumps to a test mode by command 
t transmit 

es d 

t 


during Sts. 1) i a special code to the system 
module to 1 the test mode. If the system module receives 


this code, it should . the byte 80 (hexadecimal) to continue. 
This causes a jump to power-up. 


„ Future Expansion — Some keycodes are reserved for future 
use aS special codes or keycodes. 


B. 5.7 Default Conditions 

Certain keyboard divisions have specific default modes. Some 
divisions default to the auto-repeat mode; therefore, they have an 
associated buffer that contains the default values for timeout and 
interval. Table B-10 lists the default modes and Table B-11 lists 
the default rates in the four keyboard division auto-repeat rate 
buffers. 


The volume level for the keyclick and bell has an 8~-Step range. 
The default volume level for the keyclick and bell is the third 
loudest. Both keyclick and bell volumes are 2 (decimal) (010 
5 by default. The key in position C99 of the keyboard (the 
Ctrl key on the LK201) does not generate a click unless enabled by 
the system module. The keys in position B99 and Bll (shift keys on 
the LK201) never generate a keyclick. 


For the LK201 keyboard, the Ctrl key defaults to the no-keyclick 


B-36 


Table B-10 


Keyboard Division 


_LK201 Keyboard Specification 


_ Keyboard Division Default Modes 


_ nisi esti a UGS ECS PO HSS GSO ER RGIS SGU PENTOSE ORICA EN 


sii ESR OEE Ra ERODE OOOO DE UR OS 


Mode AR Buffer 


eee needed belege iar, so iS SSR SRS CU SR RERUN 


Main array 

Keypad 

Delete 

Cursor keys 
Return and Tab 
Lock and Compose 
Shift and Control 


Six basic. editing Keys 


olbenk wuerden, 


Default 


veto dehebbe Losers 


Table B- 11 


eule 


Buffer 
Number 


uam DANONE FO DIINO mehl eee umarmen NER RU ROE ARUN 


B. 6 SPECIFICATIONS 
FUNCTIONAL 


Electronics 


Cord 


Keypad 

Home row key height 
Keys 

Main keypad 

Numeric keypad 


Special function keypad 


Editing keypad 


vo , was LMM LAA LASSE ESL IAAL ALAS OASIS AMSTRAD SINAN ONT 


Auto~repeat 
Auto-repeat 
Auto~repeat 
Auto~repeat 
Down-only 
Down-only 
Down/up 
Down/up 


seein rz iso ESAS RP RRO ON e p e ORONO RIDAT aE HOINOOTO IN. 


ee OS 


Rates in _Auto-Repeat | Buffers 
Timeout Internal 

(ms) (Hz) 

500 30 

300 30 

500 40 

300 40 


e IASON IAD 


ee ener eee wanted edel, 


8-bit microprocessor, 4 
ROM, 256 
transducer 


Kbytes of 
bytes of RAM, 4 LEDS, 


1.9 m (6 ft), 
telephone~type 
plugs into 
BCCOI) 


coiled, 4-pin 
modular connectors, 
display monitor (PN 
Sculptured key array 

3 cm (1.2 in) above desk top 

105 matte, texture~finished keys 

57 keys 

18 keys 


20 keys; Firmware- and 


software-driven 


10 keys 


a 
a0 4. 


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2 


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enter - toe 


an 


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LK201 Keyboard Specific 


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LK2Z01-AK 


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LKZ OI-AC 
LK201-AI 


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CHARACTER 


Table 


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PHYSICAL 


B. 7 
The 
Bach 


LK201 Keyboard 


ß iN 


Specification 


ii ARR 


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5 150 i 
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ns % 
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1 


Se neunen baer 


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i 
Fe ee merken 


DEC SUPPLE 

GRAPHI 
SET 
(GR) | 


si a sn mae FRIIS SGN 


| ASCII 
GRAPHIC CHARACTER 
| | SET 
c | (GL) 


——— — EC MULTINATIONAL CHARACTER SET — 


a RS esp nO EEN ANSI NNN GENER 


queen uten ame 


nee nere eb 


abend 


a 


MACOVS2 


Figure B-17 Digital's Multinational Character Set 


The MicroVAX workstation processes 7-bit character codes as though 
they were 8-bit character codes with the eighth bit not set. Each 
character set consists of displayable or graphic characters, and 
nondisplayable or control characters. 


In 7-bit-coded character sets, control characters are contained in 
columns 0 and 1, and in position 7/15, while graphic characters 
are contained in the remaining positions of columns 2 through 7. 


In 8-bit-coded character sets, control characters are contained in 
columns 0, 1, 8, and 9, and in positions 7/15 and 15/15, while 
graphic characters are contained in the remaining positions of 
columns 2 through 7, and 10 through 15. 


B-39 


LK201 Keyboard Specification 


endeten FCC 


kor 


ie 


Special Graphics Character Set 


In all character sets, the control characters in columns 0 and 1, 
and position 7/15, are designated as belonging to the control 
character group Co. The graphic characters in the remaining 
positions of columns 2 through 7 are designated as belonging to 
the graphics left character group GL. 


The control characters in columns 8 and 9, and position 15/15, are 
designated as belonging to the control character group Cl. The 

graphic characters in the remaining positions of columns 10 
through 15 are designated as belonging to the graphics right 
character group GR. 


Figure B-19 shows how the character sets are designated and used 
in the MicroVAX workstation. 


LK201 Keyboard Specification 


— KNOTT MM AMA pd . ARAM S AIT 


CHARACTER SET LIBRARY 


US UK SPECIAL GRAPHICS DEC MULTINATIONAL, 


E 


CH A AC T 2 RS 8 


CHARACTER GENERATOR ROM MAPPING 


oO 1 2 3 4 w 6 7 8 9 10 11 12 13 


| REVERS Se-.| DEC 
| QUESTION | MULTINATIONAL 
| MARKS | GR 


MEATS 


in 


igure B-19 Character Set Designations 


Re 
pete 


Fj 


0 mn aa, a, Sl, ale, be, la . ale, e, . . 
CVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVhhTUUUThhyhcf& t! d e e p . i Le Oe 


SET 


aa 
tal 
2 
2 
4 
— 
= 
2 


og = 


One 


1. V 605 * 


ap 


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ing 


act 


8 


5 
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Sa 


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bee 


os 


chara 


1 
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ra 


0 
0 


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ter. 


aracter. 


ss 
Ny 


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ch 


6 


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( 


Car 


15 
nal 


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fully active 


of the 


twelfth 


value 


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12 


c 


denen 


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3 3 tin Soe ae 
HSRC eehte eee 


been teen eee 


va ene ehen ume 
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G2 


parameter sett 


meal 


under 


0 
= 


i i 
| 
i 
i 


a Re CR ERE 


ö : 
ee endeten 


my OO e gy, ety, ge ty ite 
ben, he a oo ey CM et e 
a. e, . ie, dae ee H 
. 
i 
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4 ‘ 


MPB-TOTIS 


LK201 Keyboard Spec ification 


ase lag ERS Ue RDU ENR OS a ES a ISS Ei NR Un gana mies pA NNN 


B. 9 DISPLAYING CHARACTERS 
All character codes are processed by the MicroVAX workstation 
firmware in the following order. 


1. If no SCS sequences are detected, all character codes are 
assumed to belong to the default character set. 


2. If an SCS sequence is detected, the character code is 
translated so that, when it is input to the character 
generator ROM, it produces the proper character display. 


NOTE 

A translation between the character code 
received and the character code expected 
by the character generator ROM is 
necessary because, as shown in Figure 
B-21, the ROM mapping for graphic 
characters does not always agree with 
the character set mapping in Figures 
B-17 and B-18. 


1 character codes with the eighth bit set are processed 


. 1 
as be elonging to Digital's multinational GR character set. 


. 


Figure B-22 shows the data paths in various modes. When character 
codes are input to the workstation application programs in console 
mode, the application software is responsible for transmitting the 
actual codes for each key pressed. If the escape key is pressed, 
the applications software must send the workstation firmware the 
character code for the escape key (27 decimal, 33 octal, or 18 
hexadecimal). The same applies to host processor software, when 
the workstation is in line mode. In local mode, keyboard outputs 
are transmitted directly to the translation process firmware. 


LK201 Keyboard Specification 


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2 


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‘aa NNR RNIN 
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i | . 5 : 9 0 
i | q 5 5 18 0 i 
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a { ; SLAIN @ 5 4 
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i ; | 5 7 
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1 : 2 ee colt a 5 ö 


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3 
Pero nale eau pueblo | — 
| 1 
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0 : f ‘ q 


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alen 


i po OP ae | 4 " 0 0 
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SPECI, ee 
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GRAPHICS NOT USED | GR | 
| | 
Sie l , eae pe i ei a al / 

OTE: REVERSE QUESTION MARKS (9) ARE POSITIONS 

RESERVED FOR FUTURE STANDARDIZATIO 

101 


Figure B-21 Character Generator ROM Displayable Charac 


B~44 


LK201 Keyboard Specification 


ROUT TMT CMM OMT MMM MMM MMA MMM NM MMAR AAMT MMM ANT ANAND 


i ines ean: 


CONSOLE | 
| MODE 


nana 


WORKSTATION | 
APPLICATION | 
| SOFTWARE 


LK201 7 | 
KEYBOARD IN 


77 WORKSTATIC 
mo Te TL Le 5 ae 
JERMINAL LC TRANSLATION 


| PROCESS 


a 


HOST 
PROCESSOR 


Keyboard Output Processing 


Figure B-22 


B-45 


APPENDIX C 
MOUSE SPECIFICATION 


aos ito eigen TORE COE i Sa ER BUI aU SO i BRAT ES a iia UE ER ENUF O nT OOOAN 


C. 1 GENERAL DESCRIPTION 

This Appendix provides information on Digital's serial mouse, 
shown in Figure C-1. A mouse is a hand-held pointing device used 
to move a cursor on a video display screen. As the mouse is moved 
about on a tabletop, the cursor makes corresponding movements on 
the screen. Once the cursor is positioned, one of the mouse 
buttons is pressed to make the desired selection. 


Using an ergonomically designed pointing device like a mouse can 
make software easier to learn and use. Pointing is often faster, 
easier, and more accurate than with keyboard typing. Some 
advantages of using a mouse as a pointing device are 


Very fast positioning 

High accuracy 

Nonfatiguing 

Items on the screen are not obscured 
Stays where it was last placed 

Small, light-weight, and inexpensive. 


© @¢€ @ &@ @ 


Digital's serial mouse uses optomechanical technology to detect 
movement, with a resolution of 200 counts/in. A dedicated 
microprocessor inside the mouse converts quadrature X-Y pulses to 
relative X-Y coordinates, which are then transmitted as serial 
data to the host computer. A rubber-coated ball on the underside 
of the mouse provides excellent tracking on most desktop surfaces. 


TO 
MONITOR 
CONNECTOR 


Figure C-1 Three-Button Mouse 


Mouse Specification 


FF ENR RES ODI SONU ii i Ss is ß Oe aU NN GS RRNA BGS UR HSU i Ga a UK RE ell lt eRe 


C. 2 INSTALLATION 


C. 2.1 System Hook-up 

The mouse is shipped fully assembled and ready to operate. To 
connect the mouse, plug its cable into the mouse/ tablet input jack 
of the computer or terminal on which it will be used. The 
mouse/tablet input jack is normally located on the rear panel of a 
video monitor. 


C. 2.2 Installing/Removing the Mouse Ball 

The rubber-coated ball on the underside of the mouse can be 
removed for cleaning or replacement without special tools. To 
Clean the ball, use water and, if necessary, a mild soap. Do not 
use organic solvents such as toluene; they damage the ball's 
rubber coating. 


Clean the ball when the cursor fails to track the mouse smoothly. 
In an average office environment, cleaning the ball every six 
months should be sufficient. 

To replace the mouse ball, turn the mouse upside down to locate 
the ball housing cover, Remove the cover by turning it 
counterclockwise, as shown in Figure C-2. To reassemble nsert 
the ball into its housing, replace the cover, and secure it by 
turning the cover in a clockwise direction. 


ise Ball Removal 


we wy 
C=? 


Mouse Specification 


d r r Nia iiiN eit 


C. 3 USING THE MOUSE 

The mouse is normally used in contact with a desktop, to the right 
or left of the keyboard. To operate the mouse, take hold of it and 
allow your index finger to rest lightly on its buttons. Its cable 
should lead away from you. Move the mouse on the desktop to verify 
that the cursor responds correctly: it should go left when the 
mouse is moved left; right when the mouse is moved right; up when 
the mouse is moved away from you; and down when the mouse is moved 
toward you. 


By experimenting, each user will find the most comfortable method 
of holding and moving the mouse. The mouse buttons may be either 
pressed from the front or down from the top. Most users find it 
easiest to make small movements of the wrist. Note also that the 
mouse can be picked up and repositioned at any time. 


The buttons on the mouse are commonly referred to as left (L), 
middle (u), and right (R), as shown in Figure C-1. The functions 
of the mouse buttons depend on the software used. (Refer to 
applicable software documentation.) 


C. 4 


MOUSE SPECIFICATIONS 
PHYSICAL 


bize 


8 
hi 


8 om (3.5 in) diameter, 4.0 cm (1.6 in) 
th 
0 


Weight 170 g (6 oz) including cable 


Switches Three tactile-type switches, actuating 
force approximately 85 g (3 oz) 


Cable 1.5 m (5 ft), round 0.375 cm (0.15 in) 
diameter, 6-conductor #26 AWG stranded, 
shielded high-flexibility design 

Connector 7~pin micro-DIN type (male) 


Temperature Operating: +10°C to +40°C 
(+50°F to +104°F) 


Nonoperating: -40°C to +66°C 
(-40°F to +150.8°F) 


ELECTRICAL 


Power +45 Vdc +/- 5% at less than 150 mA 
~8 V to -13 V at less than 20 mA 


Interface RS-232 voltage-level-compatible, output 
from the mouse capable of driving a load 
of 3 kilohms to ground (mark less than 6 
V, space = 4.6 V min.) 


FCC/EMI Class B certified 


Mouse Specification 


PERFORMANCE 
Resolution 
Tracking Speed 


Accuracy 


Acceleration 


ctor 


Table C-1 


i ie ie ESRD SRG IO ODS HR EHR RCT TCT aC SFT ai HR np IS ARUN GU NU SSRN 


+/~ 3% 0 — 25 cm/s (0 ~ 10 ins 

158 25 ~ 50 em/s (10 — 20 | 

30% 50 — 75 cm/s (20 - 
ti 


31 ram 
(power~up def a 


Increment 
Prompt ult) 

odd 
” bytes 
elative 


Serial 
parity), 
indicating 


‘te 


displacement 


asynchronous (8 
report consists of 3 
button state and re 


tal stream mode, 
11 


oignal/Power Cable 
Wiring pin assi 


gnments and functions are listed in 


are numbered as shown in 


pins 


Pin ‘Number Function 

1 GND (signal and power return) 

2 TXD (serial out from mouse) 

3 RXD (serial in to mouse) 

4 “12 V 

5 +5 V 

6 Not used 

7 Device present (shorted to pin 1) 
Shell Protective > ground 


Mouse Specification 


ai cS get ct Sti eC ig i r oii i iio ial iii Naa ODI 


HE RS 


MOUSE CABLE CONNECTOR 
END VIEW 


‘€ 
E. ' 


+ CONNECTOR KEY 


NEN G6 54 


Figure C-3 Mouse Cable Connector Pin Numbering 


„ Spurious Outputs 

The mouse is designed to avoid reporting movement when it is not 
tracking on a surface. Lifting the mouse from a horizontal surface 
will not report movement of more than 20 counts of resolution. 


Noise problems are suppressed where the output varies by one count 
when the mouse is not being moved. 


Ceo ELECTRICAL INTERFACE 


C.5.1 Interface Signal Levels 
The mouse transmits and receives RS~-232-compatible signals. 


Transmit: Mark < ~6 V, Space > 4.6 V 
Receive: Mark ~15 V to 0.8 V, space 2.8 V to +15 V 


Minimum de load resistance is 3000 ohms to ground. 


6 Power and Voltage Considerations 

To operate, the mouse requires +5 V +/- 5% at 150 mA. On systems 
where a long extension cable is used between the mouse and its 
power supply, it may be necessary to regulate a higher voltage 
(5.2 V) at the system to overcome the voltage drop of the cable. 
Digital's local service representative should be consulted to 
determine the adequacy of the supplied voltage when adding a mouse 
extension cable. 

There is no fuse inside the mouse housing due to its small size 
and low voltage requirements. If developing hardware to power the 
mouse, a fuse or other current-limiting method is recommended as a 
safety precaution. 


The rise time of the +5 V supply should be less than 100 ms to 
ensure that power-up reset occurs. 


0 2 i ficat ! 

. 

Mouse Specification 

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C. 6 


MOUSE OPERATION 


age soem | Serial Interface Operation 
The mouse communicates with its . via an asynchronous, serial 
interface at 4800 baud (+/- 2%). ch character consists of one 
Start bit, eight data bits, one 0 bit (odd), and one stop 
bit. The mouse ignores incoming parity and the most significant 
of each byte (bit 7) on receive. 


The mouse supports on 
sent to the mouse whi- 
the data being t 8 
1 


y half- duplex communication. If a byte is 
le it is transmitting, the mouse will abort 

ransmitted (force a break) and process the new 
command immediately (except during self-test). If a byte is 
received between the characters of a multibyte report, the mouse 
is still considered to be transmitting and will abort the current 
report. 


C. 6.2 Report Format 

Data is transferred in 9-bit bytes (8 
Though the mouse transmits odd parity, it ix 
receive, The mouse transmits a 3-byte posit 
Figure C-4, 


data, plus odd parity). 
gnores parity errors on 
ion report, as shown in 


ive the movement 


The xX and values in the mouse position report 91 2 
the X or 1 values 


in units of 8 tion since the last report. If 
overflow, the max imum movement is reported. 


MISPLACEN 
ACE 


MIRA 


Figure C-4 Three-Byte Position Report Format 


Mouse Specification 


<i aii aii i So iSO SRG GROG tH ei iE i tT 


Ceca Operating Modes 
The mouse has two operating modes that determine when, and how 
often the mouse transmits a position report: 


1. Incremental Stream Mode 
2. Prompt Mode (power-up default). 


In incremental stream mode, the mouse generates reports at 55 
Hz intervals any time there is movement, or a change in button 
position since the last report. If the mouse is motionless and no 
buttons have changed, no report is generated. The report rate 
under continuous movement or button change is 55 reports/s. 


In prompt mode, the mouse generates a report only in response to a 
request mouse position command. The mouse responds to over 95 
position requests/s. 


C.6.4 Summary of Mouse Commands 
All mouse commands are printable ASCII characters and are 
summarized in Table C-2. The mouse ignores invalid commands. 


Table C-2 Mouse Co 


"ia Rg ESR Sao a OSS bueno 


mnand Summary 


in eS a Bai te aap gi needed uebi neee 


ASCII Hex Function 


ee r e 


VVT 


R 52 Select incremental stream mode 
D 44 Select prompt mode 


P 50 Request mouse position —— The mouse 
responds with a position report. The P 
command also switches the mouse to prompt 
mode. 


wy 
ui 
*. 


Self-test and identify -- The mouse 
responds with its self-test report (see 
Paragraph C.6.5). Self-test leaves the 
mouse in the reset or power-up state. 
When a self-test command is issued, it is 
invalid to send any data to the mouse 
until the last byte of the self-test 
report is received. The mouse ignores any 
data received during self-test. 


ZX SA XX Reserved functions for testing or quality 
control that are completed within one 
second. The previous mouse state is not 
disturbed. 


RDS ERMM MARA DMA ASSASSINS A EINE NANG EHID MMSE N LLM LLAMA LLL SLM MSN LOSARTAN NDR 


Mouse Specification 


eee mn 


e r ROO NURESGMESoiHaniainiii ci 


Ce Oe Power-Up Self-Test and Identification 

Upon command from the computer or mouse power-up, the mouse 
automatica ally checks its internal logic and circuits, and 
transmits a self-test report consisting of a 2-byte identification 
code and a 2-byte code describing the health of the electronics 
and firmware. 


The 4—byte self-test report shown in Figure C-5 is transmitted at 
power-up. 


8 
2 
2 
ee 
See 
oO 
a. 
oy 
rey) 
Some 
o 
2 


The bytes shown in Figure C~5 are descr 


dicates the start 


Byte 1, Firmware ID: Bit 7 through bit 5 (101) in 
RO is the revision 


) 
of a self-test report. R3 
number. 


oe 
a 
8. 


Byte 2, Hardvare ID: A single- byte code for manufacturing and 
device identification. M2-M0 is Digital's 
manufacturi ing location ID. Bi 5 3 through bit 

is the device code; 001 icates mouse 
71 


gure C-6 shows the ID nes format. 


Manufacturing location ID assig 
reserved for Digital's future defi 


Indicates mouse data 
Indicates tablet data 


Byte 3, Error Code Error code ASCII ">" (3E hex) indicates a RAM 

or Zero: or ROM checksum error. If there is no 
checksum error, ASCII "=" (3D hex) indicates 
a button error. Codes of 20 (hex) or greater 
are considered to be fatal hardware problems, 
codes less than 20 (hex) are nonfatal. 


Byte 4, Button code The code will be the same as the low three 

or Zero: bits of of the first byte of the mouse 
position report, indicating which, if any, 
buttons are down or have failed. 


Example: 04 (hex) would mean a left button 
error. 


Mouse Specification 


ß gc Cie en GH SAO NO SA OS UO OC 


07 O06 05 04 03 02 01 00 BIT NUMBER 


BYTE 1 


7 = FRAME SYNCHRONIZATION 
3~RO = REVISION NUMBER 
M2-MO = MANUFACTURER LOCATION ID 
E6-EO = ERROR CODE (ZERO = OK) 
LM.R = BUTTON CODE (ZERO = OK) 


ME ODGG 


Figure C+5 Four~Byte Self-Test Report Format 


MANUFACTURER 


MRO OQDG? 


Figure C-6 ID Code Format 


The switches in the mouse have two contacts, and thus, four 
possible states: 


Button up 

Button down 

Both contacts open (switch missing) 
Both contacts closed (short circuit). 


= = 


we iad AG P< 
. 


. 


The left and right switches report a button error for any state 
other than button up. The middle switch reports an error for 
button down, or both contacts closed. 


The mouse ignores any data received during self-test until the 
last byte of the self-test report is transmitted. 


Mouse Specification 


e oi i i ni oie ie ae UN li a RR GRO RROD 


C. 6. 6 Report Synchronization 

Bit 7 of the first byte of a mult ibyte report is 1, and can be 
used for software synchronization. Bit 7 of the succeeding bytes 
of a multibyte report are always Os. 


The following starting bit sequences are defined (bit 7, bit 6, 
and bit 5 of the first byte of a multibyte report). 

100 — 3-byte relative posit 
loi — 4—byte self-test repo 
110 — 5-byte abs solute posit 
ll - Reserved for Digital' 


ia’ 


ion report (mouse) 
rt (mouse or tablet) 
lien report (tablet) 
s future definition 


C. 6.7 Response Tine 

The mouse completes all valid commands, except self-test and 
Digital's reserved 5 within 50 ms. It processes a 

self-test command within 500 ms. At power-up, the mouse completes 

its self-test within 1 0 From stable power. 


C. 7 PROGRAMMING CONSIDERATIONS 

Digital's serial mouse does not support the XON/XOFF flow control 
protocol because there is no data buffering inside the mouse. This 
results in a more effective link between mouse and cursor. 


* 


The serial mouse uses half de communication. Hal f-duplex does 

not interfere with norma! 01 operation because there is no 

reason to send a command to ie. mouse while it is ] 
8 i lways read befor 

a 


t 
When polling, the previous 3-byte report is a 
0 at nds to the mouse 
1 8 


eet 
= * 
LZ 
ee 
fe 
2 
5 


a 
requesting another report. The only oth 
cause it to reset or change operating mode 


er Comme 
nd 


ae 


The mouse powers up in prompt mode to avoid sending position 
reports to the host before it is ready to receive them. 18 

mouse's self-test report is transmitted at power-up to noti 
host of its presence. 


Caled Initialization 

Although 5 serial mouse defaults to prompt mode at 
power-up, host oftware should select the protocol and operating 
mode explicitly Gon compatibility with other mouse devices. A 
complete power-up sequence typically includes the following steps. 


1. Initialize the host's rial port for the mouse for 4800 
baud (8 data, odd parity, 1 stop bit). 


PS 
aS 


. Read the power-up self-test report to confirm the mouse's 
identification and function. If the self-test was 
successful, go to step 4. 


NOTE 
The self-test report may indicate the 
pointing device is a digitizing tablet. 
(See Appendix D.) 


sisi tu gaa SURE NON AUCTS GO AHA 


Mouse Specification 


ii Si OREN pS IRINA 


aU 


3. If the self-test report is not received in 1 second: 


Check that the mouse is correctly attached and send ASCII 
T (54 hex) to invoke self-test. If the mouse responds, 
check identification and function. If there is no 
response, assume a defective or alien mouse. 


4. Send ASCII S (53 hex) to select the report format. 
(Currently, there is only one format.) 


„ gend ASCII R (52 hex) to select incremental stream mode, 
or ASCII D (44 hex) to select prompt mode (power-up 
default). 


C.17.2 Incremental Stream Mode vs. Prompt Mode 
The mouse has two operating modes that determine when, and how 
often the mouse transmits a position report. 


In incremental stream mode, the mouse tests for movement or button 
action 55 times/s, and sends a report only when a significant 
event occurs. This mode allows the host to track the cursor 
smoothly, with a minimum of data overhead. 


An effective way to use incremental stream mode is to set the 
alarm level on the universal asynchronous receiver transmitter 
(UART) to interrupt only when its first-in/first-out (FIFO) buffer 
is full. On each vertical interrupt, the host polls the UART for 
available data. If data is waiting, the host reads the report and 
updates the cursor position. Otherwise, no action is necessary. 
The host rarely receives UART interrupts. 


The mouse can also be polled to allow the host to control when the 
mouse position is updated. Since the buttons are not latched (only 
debounced), the host must poll frequently enough to detect any 
button action. 


The intended use of polling is to synchronize mouse updates with 
video refresh in order to minimize interrupt overhead. On each 
vertical interrupt, the host reads the previous 3-byte report from 
the mouse UART, and then sends the command to poll the mouse. If 
the UART is buffered (as many are), allowing it to hold three 
bytes, the host never needs to respond to mouse interrupts. 


To move the cursor absolutely smoothly under worst-case 
conditions, it is necessary to update the cursor position every 
frame time. For normal 60 Hz refresh, the 55 Hz sampling rate is 
sufficient to provide good tracking. For the smoothest possible 
tracking, or higher frame rates, polling at the frame refresh rate 
is recommended. 


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Mouse Spec 


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APPENDIX 


DIGITIZING TABLET oPECIFICATION 


5 
ee 
2 
rf 
_ 
2 


This Appendix t ides the specifications that define the 
characteristics of a digitizing tablet system interfacing wi 
VAXstation IT/GPX workstation. The digitizing tablet 
consists of a 27.5 cm (11 in) square digitizing tablet, a 
2ucK, a 2-button stylus, and a 5-foot power/signal cable, 
in Figure D-l. 


dade ey 


1 it 


a ‘te i ie 


Figure D-1 Digit 


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Digitizing Tablet Specification 


eens pi get abe NE Goal GR ca RENN i NN SU OC RE aE RU 


ion 


D. 3.2 Electrical Signals 
The tablet transmits and receives RS-232-C-compatible signals as 
follows. 


t: Space = +5 V to +12 V, mark = -4 V to -12 V 

: poe = +3 V to +12 V, mark = -3 V to -12 V 

Output from the tablet is capable of driving a load of 3000 ohms 
to ground. 


D303 Tablet Position Report 

The tablet transmits a 5-byte position report format as shown in 
Figure D-3. 

In explanation of Figure D-3: 

Bit 7 = Start of frame synchronization 

Puck: 

Bl = Button 
B2 = Button 


B3 = Button 
B4 = Button 


& © & Ge 
8 
oS 
ick 
, me 
et aa ee ee 
a 
= 
o 
= 
— 


Be 22 2e . 


1 = Barrel button: 
2 = Tip button: 
R = Proximity: 


= up, 1 = down 
= up, 1 = down 
ee | proximity, 
= out of proximity 


2088 
85 


O is LSB, binary format. 


= X coordinate bits; 
ts; YO is LSB, binary format. 


ee 
VYO-Y¥Y1l1 = Y coordinate bit 


oes 
"eee 


Figure D-3 Tablet Position Report Binary Format 


Digitizing Tablet Specification 


F e 


D. 4 TABLET OPERATION AND COMMANDS 


D. 4.1 Report Rate 

The tablet report rate is software-selectable by host command. 
Report rates are 55, 72, and 120 reports/s. In order to transmit 
120 reports/s, the baud rate must be increased to 9600 bits/s. The 
default or power-up report rate is 55 reports/s. Report rate is 
selected by sending the following ASCII characters. 

f 55 reports/s 

£ 72 reports/s 

of 120 reports/s 


D. 4. 2 Baud Rate Command 

The default baud rate of the tablet is 4800 bits/s. The baud rate 
is changed to 9600 bits/s by sending the ASCII character B (42 
to the tablet. Upon receiving this command, the tablet 
letes any report in progress, change baud rate, and switches 
equest point mode. 


7 
cr 


*k to the default baud rate by sending a 
character times) or by Ee anes ting a 
h these commands invoke the self-test 


Ea 


ons to the default conditions. 


st of the 


te a 
“urn all funct 


aa re 


D. 4. Request Point 5 
R 11 select when a coordinate 


Request point mode a the host to s 

pair is to be sent. This mode is selected by sending the ASCII 

character D (44 hex). A coordinate pair is requested by sending 

the ASCII character P (50° ae to the tablet. The P command also 

witches the tablet to rec point mode. If the request is made 

hile the s not in proximity with the tablet, the 
itted without the 
tion of power-up or 


Le 


oi 1S or puck is 

last valid coordinate pair is transm 

ope as pkey mity flag being set. Upon comple 
3 st, the tablet is placed in this mode. 


u) 
. 
e 
4 8 


Increnental Stream Mode 
incremental e mode, the tabl 
ylus moved more than 
while the puck is in motio 
depression or release, I 
SCII character R (52 


et generates a report when the 
0.0125 cm (0.005 in). Reports 
n. A 5 is also generated 

al stream is selected 
8 ‘the tablet. 


aa 
fe 
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a 
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— 
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ae 
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aus 
End: 
Reg 
wer 


4.5 Sself~Test 

n command from the host Out ipon t et power-up, the 
et automatically eee les A logic ae 1its, and 

S$ a 2-byte identification code, plus a 2-byte code 

ng the health of the l and firm 

A 4-byte self-test report is transmitted at power-up, as shown in 
Figure D-4. Each report contains the absolute K and Y¥ positions of 
the puck or stylus from the N of the tablet. The origin of 
the tablet is the bottom left corn of the active area. The first 
byte of the report indicates whi ch “button i 36 


Digitizing Tablet Specification 


ia 


— 
= 
3 
a 
ao 


ee 

BIT 7 = FRAME SYNCHRONIZATION 
R3-RO = REVISION NUMBER 
M2-M0 = MAN i FAC TU RING LOCATION ID 
B4-B1 = BU" 


N- 1712 


Figure D-4 Four -Byte Self-Test Report Format 


The four bytes are explained below. 

Byte 1, Firmware ID: AO (hex) for initial release. 

Byte 2, Hardware ID: A _ single-byte 8 for manufacturing and 
device identification, as formatted i 


erage Dros 


Manufacturing location ID code 


assignments 
are reserved for Digital's future 


definition. 


Device ID code assignments: 
0010 — Indicates mouse data 
0100 — Indicates tablet data 


MANUFACTURER 


e 


Figure Db—5 ID Code Format 


hardware problems, 


fatal 


be 


to 


55 


40h 


1 


4 


‘ 
4 
4 


hi 
co 


« 
. 


0 


i 
for 


jy 


scifie 


CS ae 
me e 
Ba 
LSM SALMA SASSI eee unebenen e een SSNS SEE eeuc eben eee 


iz ing Tablet 


se) 


a os 


t 
are down, 

8 

p 

1. 

h 

QO 
software 

k 
urrent 


command, 


for 


4 
est 


x 8 ee rs is a 8 
. e ae 3 “2 3 age 2 peed = 
td < . 


eck sum error 
e 


M che 
r did! 
8 
0 
1 
t 


i 
completes 
a 


ata 
self- 


2 ‘ — * O = 

: = „ 8 ee 

cS = — = Me eed "OD : © 

si & e i 2 . # ex. get 

oc) Oo 2 oO Om 4 oconm~ © © 7 — 
l A — 


tablet 
e 
ommands 


De ** or ey 
the 
e 

‘hes 
Pa 


i 
“ter 
. 


ti 
following state. 


„ ee 


i 
the 
t 
aft 


n 
the 


‘ommands 


1 
f 
ts 
the 
d 
15 
ar C 
2 
Or a 
(the bytes of the report are 
i 


gq Tablet 


commands, 


dered 


2 — 
177 ao up 4 
2 ibe i i 43 45 ort oo Oo 6 2 — me 1 92 
W 4 W >H O Ll et * — 2 8 Cc si « © — 
ei * — — — 2 — 92 it n 6 . nO 2 O et 2 W 3 
2 x N de „ I # @Q oc 3 8. amt UO ort @ x ceo © 
„ OCG M ‚—W ONDA & 2 0 i wt Do dere > © wt Ee 
„5 =< 2 20: 2.2855 “wo 8 i ba Qe QE aH O — NOE 2 
Qu W e — — — ot 8 ® ut O coo G Nos oo 8 O W 
2 W . ~~ 2 How ww kh oO * oot Ow 
O20 Hc Oo ei © fe & @ Ue @ i ot O oow = 8 ~ W © 1 
OF OF MOO ee Bt ke cet 0 . 2 0 ou — WS © — 
ud ond <= ef iy * W 45 ad @ > W er 
HO W „ o G6 GC we 2 2 . 
7 = ge is) 2 ee Gi u pee = 
2 aa 
— 


Command 


48 
im 

1 

me 
rate 


reports ar 
gnores 


j 
i 
3 
8 
Recovery from Invalid ¢ 
i 


tablet 
) 
i 
} 


Summary of Digiti 


Default 
Lon 
= 
E 
a 
Report Sync 


commands 
(m 


4 
1 
Report 


host 

a BRE 
. 
* 
ne 


“ee ee =) 


The 
Ve 

Ne 
Upon 

ab. 

N 

U 

5 

lL 
The 


Digitizing Tablet Specification 


r r . RNnniTNssinIn Sis nit sienna sin iv itt eng ECR 


Summary of Tablet Commands 


. DELIA SADNESS ELLA LETS LALLA SE SELLS ABS ILEANA ABELL DRL LIAS ELLE ADELE ALE ALAS EDA. 


. Hex Function 


e 


BREAK saves seis test 

B 42 Change baud rate to 9600 

D 44 Request point mode command 

K 48 Set sampling rate to 55 

5 40 Set sampling rate to 72 

M 4D Set sampling rate to 120 

P 50 position request command 

R 52 Incremental stream 

T 54 Invoke self-test 

Z x SA XX Digital's reserved functions for tes 
or quality control, completed withir 

The previous tablet State is not 


D. 5 PERFO! NCE SPECIFICATIONS 

Da et Resolution 

The resolution of the tablet is 0.0125 cm (0.005 in) or 200 
counts/in in any direction. 


Ded ad Accuracy 
The tablet does not produce outputs in error by more than / 5 
counts of the position report's LSB 


D.5.3 Spurious Outputs 

The tablet avoids reporting movements of 1 LSB or when reporting 
has been disabled. Picking the puck or stylus straight up from the 
tablet surface does not report movement of more than 10 counts of 
resolution. When the puck or the stylus is not in the proximity of 
the tablet, positional reports to the host are suppressed. 


D. 5. 4 Response Tine 

The tablet processes all valid commands (except self-test and 
vendor- reserved commands) within 100 ms. Within 500 ms, the tablet 
must respond to a self-test command. The tablet completes its 
power-up self-test within 1 s after stable power. 


D.5.5 Initia 
tia 


A sample ini ion for the tablet is as follows. 


920 
cr 


ie 


1. Initialize the host's serial port for the mouse/tablet t 
4800 baud data format (8 data, odd parity, 1 stop bit). 

2. Request that the tablet do a self-test and identification 
sequence by sending ASCII T (54 hex) to the tablet. 


If the tablet driver switches the baud rate to 9600 baud 
the break character should also be used (break followed by 
an ASCII T). This prevents the tablet's staying at the 
higher baud rate if the system is reset. Care must be 
taken when switching to the higher baud rate. 


elf-test was 


‘iB 
ss 


a 
Rp en. 
L hes 
ehe, en, 


ith any error report. 
not 


of th D 
SSS eas GSE ENON ANBAR REND 


oe Ne ginny pn oO BIRR USO 


ificat 
report was 


ig 


Spec 


vt 


1. 
e 


2 


et 


Tabl. 
sel f-t 


ae 1 
11 


izing 


a 


4 © 


a 


gi 


Di 


es eS aped 2 @ = es 


eS. é 5 eee 2 i 
3 2 cart 2 8 Se 
2 re) © 6O x 8 
Ae R& 2 Zz es : see : 
wo o Oo S S e 2 . 
ul £ 8 2 5 & 5 e ‘i 
a — 82 5 re OOO N = — 
3 AS gE Pes 3 


1 
set- up 
8 
0 +400C 
6 
Sing, 
% 


aS al 5 
2 ui he 


-LFICATIONS 


~4 

ni 

1 
minimey 


ee 4 b 
alien. 
a 
al 


2 
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0 
15 
Lem 
i 
% 


I 
Default 


IOnsSe 


SPE 


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I 
9 


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0 


ng 


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heck 
defective or 


RANGE 
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(packaged) 


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| 
operat: 


Nonoperating 


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Operat 


TEMPERATURE 


HUMIDITY 


i 
Q 


II 


Address processor chip 
A custom LSI chip (microsequencer) that generates the CRT timing 
nals and bitmap memory addresses required for screen refresh, 
lling, and raster operations. The address processor chip also 
ies microinstructions a 
(datapath). 


] 1 
suppl nd data used by the video processor 
chip 


Application program 
A pro chee designed to meet a user's specific need, such as the 
monitoring of a manufacturing process. 


ASCII 
American Standard Code for Information Interchange. 


Asynchronous multiplexer 

A device that controls and alternates the transmission of si 
so that more than one signal can be transmitted over a sg 
communication line. The data being transmitted contains 
necessary synchronizing information in the form of start and stop 
ignals. 


Backplane 
The connector block into which all the MicroVAX workstation's 
printed circuit boards are inserted. 


Backup 

The continuing process of making copies of a disk drive's store 
data for purposes oe recovery in case the main record is lost. 
Backups are made on RX50 diskettes or TK50 magnetic t 
cartridges, which are then safely stored. 


eed at which signals are ser 12115 transmitted along a 
cation path. One baud equals one bi t/s. 


Binary 

The number system that uses only 2 digits: 0 an 
are usually represented in MicroVAX workstat 
voltage levels. 


ee oe 
deed 


Bit 
A binary digit; the smallest unit of information in a binary 
system of notation, designated as a 0 or a 1. 


Glossary~1l 


Glossary 


gate re oe ORO ag EO HET EN Ue SN eg OES Sa OO a UU COR RT ONE RNG AN ATER EOE UVV 


Bitmap 
Memory used to store an image as an array 
each pixel. Bitmaps | sical 
multivalued pixels. 


Bootable medium 

A fixed disk, diskette, or magnetic tape cartridge that contains 
software, such as an operating system, which the bootstrap progran 
can load into the MicroVAX workstation's system memory and begi1 


® 


memory execution. 


M 
n 


Bootstrap program 

A program started upon power-up of the MicroVAX workstation. The 
program loads into memory software contained on a fixed disk, 
diskette, or magnetic tape cartridge. The workstation then halts 
execution of the bootstrap program and starts execution of the 
software in memory. The software usually loads an operating system 
or other software into memory to enable operation of the MicroVAX 
workstation. 

Bug 

An error in the design or implementation of hardware or software 
system components. 

Bus 

A flat, flexible cable that consists of many transmission lines or 
wires and that interconnects computer system components to provide 
communication paths for addresses, data, and control information. 


Byte 
A group of 8 binary digits (bits). A byte is 
of a MicroVAX workstation word (that is 
words, or 1 longword). 


one-quarter the size 
2 bits, 4 bytes, or 2 


Central processing unit (CPU) 
The part of a MicroVAX workstation s 
‘ 


r system that controls the 
interpretation and execution of instructi 


ee 
0 h 
hy em 
ball a d a 


Clipping rectangle 

A rectangular mask applied to tt raster 5 a 
rasterop. Pixels outside the N of the clipping rectangle 
are unmodified. 


Color map register. 

Color map | 

A random-access memory that translates a pixel value into a color 
Or ee. 


Command 
An order entered on the MicroVAX workstation keyboard by a user. 


Communication line 
A cable path along which electrical signals are transmitted. 


Glossary~-2 


iain inane ei aii iia t t SRG SGU GRU . t EG RU GRAN NGO 


Computer system 

A combination of, for example, MicroVAX workstation hardware, 
software, and external devices which performs specific operations 
or tasks. 


Console terminal 
The MicroVAX workstation terminal used for installing software and 
running diagnostic programs. 


Controller 

A MicroVAX workstation component, usually a printed circuit board, 
that regulates the operation of one or more peripheral devices. 
Controllers are often called “interface units." 


Control panel 

The part of the desktop, floorstand, or rack~-mounted BA23 or BA123 
nclosure that contains the control switches and indicators for 

monitoring the operation of the MicroVAX workstation. 


CPU 
Central processing unit. 


Cursor 

An arbitrary 2-color shape with an arbitrary serie a blinking or 
non-blinking block or underscore displayed to indicate the screen 
or data entry position. 


DAC 

Digital~to-analog converter. 

Data 

A formalized representation of facts, concepts, or instructions, 
Suitable to human or mechanical communication, Retest rates or 


processing. 


Data transmission | | 
The movement of data in the form of electrical signals along a 
communication line. 


Debug 
To detect, locate, and correct errors (bugs) in a system's 
hardware or software. 


Device 

The general name for any entity connected to the MicroVAX 
workstation that is capable of receiving, storing, or transmitting 
da ta ® 


Diagnostic program | 
A program or several programs that detect and identify abnormal 
MicroVAX workstation hardware operation. 


Directed-beam refresh © 
See "Graphics CRT display." 


Glossary~3 


Glossary 


FF r n Rg TG ra GOAN a t d NG DN aR LM 


Direct-view storage tubes 
See 5 cs CRT display." 


Disk 

A flat, circu! 
magnetically st 
an RD53 fixed di 


ar . with a coating | 
ae, in concentric circles 
sk, and RX50 disk(ette). 


on which data is 
8 or example, 


pte, Lee 
rr 
rt 
Fee 
pe kd 
1 
~ 
7 


r 


Disk drive 
A device that contains a fixed disk or one o 
drive contains mechanical components that spi 
move the pickup heads for reading and vritinc 


Dis 1 
A flexible disk packaged in a Square paper envelope. 


Display coordinates 

The address of a pixel in Cartes 
upper left corner of the eet 
increas ses downward. 


2 “a 


9 . 


inates referenced to the 
creases to the right, Y 


al universal asynchronous receiver/transmitter. 


Elacteonic Industries Association. 


Error message 
A message displayed by the MicroVAX workstat 
detection of (a) hardware, software, or data fault 


5 


ion to indicate 
(s). 


Fast mode 

The writing mode in which data is written into the destine 

raster in 16-bit increments. Fast mode can be used when one edge 

of the raster is aligned with the X-axis. 

FCN registers 

Logic 1 
r 


iction registers in ne video processor chip that can be 
coded to perform logical oper 


tions on displayable data. 


ey 
a 
rr 
55 
5 
e 


FIFO 
First-in/first-out (buffer control). 

File 

A collection of related information treated as a single item by 
MicroVAX workstation. 


Formatted data 
Data arranged in a 
predetermined st 
organization is ai 2 


particular pa attern to conform to a 


ructure or nei F protocol. Its 
tated by the system software. 


Glossary~-4 


FRU 

Field-replaceable unit, an individual component or assembly of a 
system. An FRU can be replaced while the system is operational. 
The VCBO2 video subsystem's FRUS are the VCB02 base module, the 
first VCBO2 4-plane memory upgrade module, the second VCB02 
4-plane memory upgrade module, the keyboard, and the mouse or 
optional tablet. 


Graphics CRT display 
One of three basic forms of graphics CRT displays: raster scan, 
directed-beam refresh, or direct-view storage tubes. 


The raster scan form is used in commercial television. It operates 
by varying the intensity of a beam that periodically scans left to 
right and top to bottom along the fixed number of a screen's scan 
lines. 


In directed-beam refresh displays, the beam moves from point to 
point on the screen to produce the desired image, rather than 
scanning periodically. The image is maintained by being completely 
redrawn at the periodic refresh rate. 


Direct-view storage tube devices use the same method as 
directed-beam displays to draw an image. Since the image is stored 
in the phosphor of the screen, periodic refresh is not necessary. 
This type of display features a “write through" capability, which 
writes a beam-refreshed image of lesser intensity over the 
permanent image on the screen. 


ie 
0 


Full color is available only on the raster scan display devices. 


Hard-copy terminal 
A terminal that displays information on paper, rather than on a 
video monitor. 


Hardware | | 
The physical (mechanical and electrical) components assembled in a 
MicroVAX workstation. 


Head 
The part of a fixed disk drive, diskette drive, or tape drive that 
reads, records, and erases data. 


Hole 
A pixel within the boundaries of a destination raster that is not 
mapped by the normal raster operation algorithm. 


Hole-f111 
A modification of the raster operation algorithm used to fill 
holes in the destination raster. 


I/D interconnect 

The instruction/data bus that connects the address processor chip 
to one or more video processor chips and associated display 
hardware; used to transfer instructions and data. 


Glossary-5 


Glossary 


a i 


Input device 
A system assembly used to transfer data into the MicroVAx 
workstation; (for example, a keyboard). 


Inputy/ output (I/O) device 
A system assembly that accepts data for transmission to (input) or 
from (output) a MicroVAX workstation; for example, a terminal. 


Interactive | 
The method of communicating with a MicroVAX workstation system in 
which a command is entered at the keyboard, the system executes 


the command, and indicates its accomplishment of the command with 
a displayed screen prompt. 


Interface 

A hardware device or software instruction that allows the 
components of a MicroVAX . to communicate with one 
another. 


170 
See "Input/output device.“ 


Kbyte | | 
Abbreviated form of ki lobyte;“ 1,024 bytes. 


= 


Light~emitting diodes used as 


LEDs 
i 
vital 895 nts of a printed 


indicators on the control panel and 
circuit board. 


Linear pattern | | 
A repeating, 2~dimens onal, rectangular pattern whose origin and 
alignment correspond to an arbitrary vector in the bitmap. 


LK201 
One of Digital's LK200-series keyboards. 


Load 
To move software 
physically place 
drive. 


rom a peripheral device into system memory; to 
disk into a disk drive, or tape into a tape 


3 


Local processor 
The processor that controls the VcBOZ video subsystem. 


Locator 

An absolute point on the display represented as 
coordinate in the high 16 bits, and the Y coordinate in 
bits. 


1th the X 
the low 16 


Glossary 


CMM MMO NAAN ER IND: 


Magnetic tape 

A long plastic strip coated with magnetic oxide, used for storing 
data; for example, the tape contained in a TK50 magnetic tape 
cartridge. 


Mbyte 
Abbreviated form of "megabyte;" 1,048,576 bytes. 


Memory 
The area where a MicroVAX workstation stores data and finds the 
instructions to perform commanded tasks. 


Memory coordinates 

The address of a pixel in Cartesian coordinates referenced to the 
start of bitmap memory. X increases to the right; Y increases 
downward. 


Menu 
A displayed list of options, typically commands a user can enter. 


OCRS 

Operand control registers in the video processor chip that can be 
coded to control the transfer of displayable data between 
functional registers in the video processor chip and the bitmap or 
I/D interconnect. 


On~line 
Pertaining to equipment, devices, and events that are in direct 
communication with the MicroVAX workstation system. 


Operating system 
A collection programs that control the operation of the MicroVAX 
workstation and perform such tasks as: 


Data and program memory assignments 
Processing requests 

Scheduling tasks 

Controlling input/output operations. 


& @ @ ¢ 


Output device 
A device that extracts data from the MicroVAX workstation; for 
example, a printer. 


Peripheral device 
Any device that provides the CPU with added memory storage or 
communication capability; for example, a disk(ette) drive, video 
terminal, printer. 


Pixel 

A picture element, the smallest addressable component of a 
displayable image. Associated with each pixel is a value, and a 
bitmap address in a 2-dimensional Cartesian coordinate system. 


Glossary 


‘cient an 


i 
pits in the xX direction tha 
, the field is one bit wid 
half, or one- quarter, resol 


represent a pi 
The width is 
i 


At highest 
1 5 Four 
utions, respecti 


resoltr 
bits at 


al eee oe 

8 
. 

1 
nik 
2 
= 
SS 


Pixmap 
An N-plane (pixel) rectangle, where Nis the number of planes 
provided by a displ 


Power up F 
A series of ordered events that functions to properly energize a 
system, 


Printer 
A peripher ral device that provides paper copies of information 
stored in a MicroVAX workstation. 


Program | 
The complete sequence of instructions necessary for a MicroVAX 
workstation to 553 a task. 


PROM 
Programmable read~only memory. 


Prompt 
A symbol or word(s) the MicroVAX workstation displays to indicate 
a task is completed or that a command should be entered to perform 


One. 


Puck 
A 4 - button 


Se 


nput device used with an optional digitizing tablet. 


gr 


Raster 
The set of pixels within a parallelogram. 


Rasterop 
A rast 
transfor 
raster of any size or or 


er operatior 
mS a rectangular source of pixels 
yrientation. 


on on the contents of bitmap memory that 
into a destination 


Raster scan | 
See "Graphics CRT display." 


Read-only memory (Re 
A memory that does not allow modification of its contents. 


Reboot 

To restart a MicroVAX workstation system. Pres 
button on the control panel reboots the works tat i 
halt enable/disable switch at the rear of the en 
up (enable) position. 


8 8.0 


Record 
A set of related data that a program can treat as a unit. A "file" 
consists of a number of records. 


Glossary 


ens iT ap Ra i as sen igi ui Ga Gia i ao ANON I NaN CN OR 


ROM 
Read-only memory. 


Run 
A single, continuous execution of a program. 


Slow mode 
The writing mode in which data is written into the bitmap 
pixel at a time. Slow mode is used for Z-axis operations anc 

the destination raster does not have one edge aligned wit 


8 8 
ee 
© 
3 


h the 


Software 
Programs executed by a MicroVAX workstation system to perform 
chosen or required functions. 


Software package 
A set of related programs that together perform a Specific task. 


Storage medium 
Any device capable of recording information; for example, a 
diskette. 


store 
To enter data into a storage device, such as a disk drive, or into 


The bit plane that is created by reducing the X resolution of a 
bitmap by a factor of one-quarter or one-half. In this case, 


resolution is sacrificed to obtain added color or intensit 
Le eye 18 ‘ie 


7 
* 


system 
A combination of, for example, MicroVAX workstation hardwa 


. 
software, and external devices that performs specific proc 5 
operations. 


0 
4 
00 


System management 
Tasks performed by the operating system that control the overall 
operation of the MicroVAX workstation. 


Terminal 

Generally, an input/output ens 1 allows a user to 
communicate with the MicroVAX works ion system. Terminals are 
either video or hard-copy devices. 


linear pattern whose origin coincides with the screen ori: 
9se edges are parallel to the X- and Y-axis. Concept 
le pattern covers the entire bitmap address space. 


cr ~~ 
~~ 
ae 
a 
— e 
— 
e 
. 


VVV 


VCB02 video subsystem 

A 4- or 8-plane video subsystem contained on 2 or 3 quad-height 
modules, respectively. It provides 1024 (horizontal) by 864 
(vertical) pixel resolution on a 19-inch monochrome or color 
monitor when installed ina _Microvax workstation (BA23 or BA123 
enclosure). The 4-plane subsystem displays a total of 16 olor or 
Shades of gray, whereas the 8-plane subsystem displays a total of 
256. 


Video terminal 
A terminal that displays information on the screen of a cathode 
ray tube (CRT). 


Video processor chip 

The component gets path) of the VCB02 video subsystem that 
operates on displayable data as instructed by the address 
processor chip. 


Winchester disk 
A hard disk permanently sealed in a drive unit to prevent 
contaminants from affecting the read/write head. 


Word 

The largest number of bits (3 
accommodate in any one opera 
also process longwords (two words 


2) that a MicroVAX works rae on can 
tion. The MicroVAX workstation can 
s, or 64 bits). 


Workstation 
A single-user system that offers high-performance, high-resolution 
graphics, and can function in a network environment. 


Write-protect 
To protect a disk, disket te, or other storage medium against the 
addition, revision, or dele tion of its information. 


Write-protect notch 
The small notch in the side of an RX50 diskette envelope, covered 
with an adhesive label or tab to write~protect the diskette. 


Me 


Glossary~-10 


sess i SS ih S/S UAB NACo NODS OPIN GAN DO A aT RR SSRIS OS SAPS GEIS SOMN 


Additional memory, 2-9 Bus width, effect of 
Address counter, 3-58 address output, 3-104 
Address disable pin, 3-96 performance, 3-16 
Address indexing, 4-11 register, 3-71,84 
Address ial dade algorithm, 4-10 restrictions 
Address processor tides, 3539 
commands, 4-50 video processor, 3-82 
description, 4-49 
Address processor chip, 3-27, Cables, 2-8 
4-16 Cancel command, 3~40,56,63,79, 
commands, 3-74 82 
data flow, 4-19 status bit, 3-58,82 
pins, 3-94 Chip architecture 
Q22-Bus interface, 4-19 video processor, 4-19 
registers, 3-57 video processor/address 
Address translation, 4-13 processor, 4-16 
Alignment error, 4-47 Chip select registers 
Arbitrator, 4-18 external register numbers, 
3-102 


BA1L23 enclosure, 1—1, 2-2,6 C —6 


1 Clip XK max, 3 

configuration, 2-5 lip X min, 3- 
BA23 enclosure, 1-1, 2-4 Clip 1 max, 3 
ie 4s 3 

1 


2 
: 


components, 2-4 C1 
configuration, 2-5 | 
BA23/BA123 enclosure 
configurations, 2-2 registers, 3-66 
Background color, 3-87 with scrollin ng, 3-23 
effect of, 3~-37,86,87 Clipping rectangle, 4—7 
loading of, 3-26,76,90 Clipping region, 4-10 
with PTBs, 3-81 Color map loading, 3-6 
Backplane slot assignments, 2-3 Command, 3-27,62,63,74 
Bitmap data operations, 4-16 use of, 3-52 
Bitmap memory organiz zation, 4-3 Communication devices, 2-9 
Bitmap/processor Connections 


mapping, 4-46 common intermodule, 2-14 
: 16 


Bresenham's algorithm, 3-32, Console emulation, 3-11 
4—27 Control store RAM, 4-22 
Brush, 3-47 Coordinate systems, 4-50 
BIP 9 2°20 732 Coordinate systems/mapping, 4-8 
command, 3-62,74,78 Coordinates 
with scrolling, 3-79 device, 3-57 
X-mode, 3-79 memory, 3-57 
Z- mode, 3-81 world, 3-57 


0 


2— 

transfers, 4-42 unique intermodule, 2- 
1 
2 


Index 


SNES EAE NEE HEE BIRR EEO SIRS HONE NR SH RE EO HO SIR IS HOO GNESI i Li EGS SE OD ED SDE hl SG il MRO RNR ee 


DEQNA, 2-8 

Destination operand, 4-12,29 

Destination Xx origin, 3-29, 52, 
67 


Destination Y origin, 3-29, 52, 


Diagnostic support, 3-12 
Diagnostics 

fault detection, 5—1 
processor test, 5-10 
p memory addresses, 1 
map memory test, 5—11 
Ain sequence, 5-20 

p set initialization test, 


6 


142 


CMR blue pixel value test, 


1 
CMR green pixel value test, 
1 


1 
console bus resety/ reset 
defaults, 5—21 
co 


console I 
console 1/0 support, 5-1 
console page configuration, 
5-5 
console prog 
DMA test, 5- 
down scroll 
DUART test, ~16 
enable ROM/console reset 
routine, 5-23 
error numbers, 5-7 
execution cine, 5-2 
Functional description, 5-6 
get character 
hardware R "623 
hardware i 


ram, 5-2 
14 

test, 514 
5 

co 


operational 
requirements, 5~4 

Keyboard put character 
routine, 5-27 

keycode translate character, 
528 

LED definitions, 5-8 

LEDs, 5-6 

manual input devices test, 
5~18 


Index- 2 


9 ion, 5-1 

power-up defaults, 5-24 

power-up self- test, 5-1,6 

put character poll routine, 
5-21 

put character routine, 5-19 

register access, 5-9 

reset ROM/console bus 
routine, 5~21 

restrictions, 5-3 

right scroll test, 5-13 

ROM code, 5-3 

row/column parameters, 5-29 

scan line pixel values, 5-15 

software operational 
requireme nts, 5-4 

software service routine, 
597 

template RAM test, 5-9 

update enable chip select 
test, 5-10 

eno font table, 5-28 

VCBO 2 I/O space CSR address, 
5-28 

VCBO2 memory space CSR base 
5-29 

video si 


i level test, 5—15 
video sy! 


ronization pulse 
5-14 
lisecond routine, 


7 4 
＋ 
3 


Dis splay lis 
3~118 
DMA controller 
interface, 3-16,19,57,58 
restriction, 3-24 
use of, 3~-26,39,79 
DMVII, 2-9 
Doubling, 4-39 
Drag region, 4-8 
52011, 2-9 


t data and commands, 


Edge vectors, 4 
before fill, 4-39 
diverging, 

ERROR 1, 3-32,69 

ERROR 2, 3-32,69 

Ethernet controller (DEQNA), 

2—8 


destination DX, 3-28,34,68 


Fast destination DY, 3-28,34,68 
Fast scale, 3-33,34,49,68 
Fast source 1 DX, 3-67 
effect of, 3-32,33,49 
use of, 3-52,55 
Field replaceable units (FRUS) , 


5-2 
Fill, 3-87 
loading of, 3-26,76,77,90 
Foreground color, 3-87 
effect of, 3-37,86,87 
loading of, 3- 26, 76, 90 
with PTBS, 3-81 


Graphics, 3-46 
curves, 3-27, 47 


flood, 3 
objects, 
points, 

polygons, 


~40,55 
3-56 

3-46 

3-50 


vectors (shaded), 3-48 
Hardware 
buses, 3-15 
address, 3-15,16,103 
data, 3-15,16,103 
t/D, 3-15,16 


private data, 3-15 
video, 3-15,107 
chip select 
logic, 3- 
use of, 
color map, 


15,22,75,81,102 
3-76,79, 80, 31, 90 
3-107 


interconnect (I/D), 3-26,82, 
99,100 
timing, 3-16 
address bus, 3-16,72 
clocks, 3-99,101 


computation cycle, 3-18 

data bus, 3-16 

I/D bus, 3-16,99 

major cycle, 3— 16,73, 74, 
103,106 

minor cycle, 

synchronization, 
101 

video bus, 

write enable logic, 


3-16,103,106 


3~15,73,82 
3-106 


Hardware cursor, 3-5 
Hardware support, 4-1 


Hole fill, 4-28 


Index 


fenen SNA RTS RES 


1/D bus, 3-16 
command, 3-64,74,75 


data . 362,64, 76 
FIFO, 3-39, 75, 79582 
status, 3- 58 
with address counter, 

58 

data source, 3-36,80,86,88 

external device, 3-75,76,102 

NOP cycle, 3-75,90 

I/D DATA, 3-60,62,77,82,89 

I/D sneerccnnecc, 3— 25 4—1 

chip select decoding, 3- 

protocol, 4-17, 26 

I/D scroll command, 
82 


3~19, 


3~64,74,77, 


t/D scroll data, 3-58 ,64,77,90 
1/O devices, 3-6 

I/O connections, 2-16 

I/O page CSR, 3-10 
Index/offset registers, 4-15 
Interconnect (I/D), 3-15 


Interrupt, 3-22,25 
pin, 3-18,76 
Interrupt enable, 3-58 


KA630 ROM, 5-1 

KA630-AA CPU, 2-4 

Keyboard, 2-8 

Left scroll boundary, 3-77,87 

Light emitting diodes (LEDS) , 
5-6 

Linear pattern, 4-33 

LK201 keyboard, 2-8, 3-6 

Local memory space computation, 
4-44 

Logic unit, 4-22 

Logic unit function, 3-39,85 


selecting, 3-78,80,81 
Mask 1, 3-86 

control of, 3-86 

loading of, 3-38,88 
Mask 2, 3-86 

control of, 3-86 

loading of, 3-38,88 


Masking/clipping logic 22 


4— 
. 
Mass storage devices, 2—7 


Index-3 


Memory, 3-16 Operand indexing algorithm, 
configuration, 3~16,18,71, 4—10 
104,105 Operand routing functions, 4-21 


Planes, 3-26,41,56,105 Optional tape storage, 2-9 
RAM, 3-71,105 Orthogonal functions, 4-19 
refresh, 3-16,71,72,104 
row/column addresses, 3-71, Pause, 3~-24,59,65,77 
103—105 PBT, 3-26 
timing, 3~16,73,103 flood, 3-56 
word boundaries, 3-35, 39,41, with scrolling, 3-39 
79,87 X-mode, 3-39 
Memory base register, 3-10 Z~mode, 3-39 
Memory CSR, 3-10 I/D instructions, 3-37 


MicroVAX CPU index management, Pending X index, 3-24,66,77 
3-24 Pending index, 3-24,66,77 
MicroVAX workstation, 1-1 Performance, 3~18 


System configuration, 2-2 rasterop, 3-18, 40 
Mode, 3-45, 62 text, 3-18, 42, 43, 44 
use of, 35 49,50, 51 font storage, 3-41 


1 
Modulo arithmetic, 4-10 while scrolling, 3-21, 40 
Monitors, 2-8, 3-7 Physical configuration, 3-94 
VR260/VR290, 2-8 Pixels 
Mouse, 2-8, 3-6 non=square, 3-27,29,30 
commands, C-7 square, 3-3] 
operating modes, C~7 Plane address, 3-85 
operation, C-6 Polygon fill, 4-36 
programming considerations, Polygon £111 algorithm 
C-10 effects, 4-39 
self-test and ID, C-8 Polygon fill model, 4-38 
usage, C-3 Printers, 2-9 
MS630 oe expansion module, Processor/bitmap 
6 mapping, 4-46 
transfers, 4-46, 49, 53 
New X index, 3-24, 66,77 PTB, 3-26, 39 
New 1 index, 3-24, 66,77 command, 3-63, 75,79 
with scrolling, 3-79 
Object (raster), 4-10 X~mode, 3-79 
Off-screen Z2~mode, 3-81,85 
definition, 3-72 I/D ins tructions, 3-90 


shared use 


3 
5 3720 PTP (Z- mode), 3-85 
use of, 3-20 


ifigurations, A-32 


ui 
— 
7 
re 
m2 
Q 
— 
ee 
. 
N 
55 


dae had If 8 mE dbs 8 Bus, A~] 
PBTs, 3-39 block mode DMA, A~-17 
PTBs, 3— 79 bi 
Source two, 3-34, 50, 56 bus pin identifiers, A-36 
zoom, 3~27 control functions, A~-27 
Off-screen memory, 4-9 BDCOK H, A-28 
of f-screenyvis sible memory, 4-4 BPOK H, A-28 
Old X index, 3-24,66,77 halt, 27 
Old Y index, 3-24,66,77 initializ ration, A~27 


1S cycle protocol, A-6 


On-screen, 3-56 ,57 memory refresh, A~27 
definition, 3-18,72 power status, A-27 


power-up/down protocol, 
A~28 


Index-4 


vis nian ia einai ig ECHO 


data transfer operations, A~5 
DMA, A-15 
DMA protocol, A-15 
interrupts, A-21 
signal assignments, A-3 
specifications, A-29 
DATBO bus cycle, A-18 
DATI bus cycle, A-7 
DATIO or DATIOB bus cycle, 
A-13 
DATO or DATOB bus cycle, A~12 
device addressing, A-6 
DMA guidelines, A~20 
interrupts 
device priority, A-21 
4-level configurations, 
A-25 
protocol, A-21 
master/slave relationship, 
A~2 
memory space, 3-8 
multiple-backplane system 
configuration rules, A~35 
single-backplane system 
configuration rules, A-34 
specifications 
bus drivers, A-29 
bus interconnecting wiring, 
A-31 
bus receivers, A-30 
bus termination, A-30 
load definition, A-29 
120-ohm bus, A-29 
power supply loading, A~36 


Raster (object), 4-10 
Raster operational model, 4~35 
Raster scanning algorithm, 4-27 
Rasterop, 3-18,27,46, 4-5 
address FIFO, 3-28,40 
arithmetic 
Bresenham's algorithm, 
3-30,32 
error computation, 3-32,69 
major axis, 3-30 
minor axis, 3-30 
range, 3~28,35 
scaling, 3-32 
shift constants, 3-37 
command, 3-27,63,78 
loading of, 3-76,78 
use of, 3-52 
complement mode, 3-28,30,31, 
33 


Index 


data flow, 4-19,20 
data path, 3-34, 36 
barrel shifter, 3-37,80, 82, 
89,92 
colors, 337,85, 86 
loading of, 3-26, 45 
use of, 3-56 
CSRs, 3-31,38,88 
selecting, 3-78,79 
logic unit, 3-37,85 
selecting, 3-78,79,81 
use of, 3-45 
mask register, 3- 
control of, 3-83 
use of, 3-45,56 
source register, 3-37,81, 
82,85,86 
loading, 3-26 
definition, 3-27 
destination, 3~-26,27,29,37, 
63 
enable, 3-78 
fast vector, 3-34, 68 
definition, 3-29 
use of, 3-46, 49 
holes and duplications, 
3-30,46,63 
origin, 3-52,67 
registers, 3-67 
rotation, 3-39 
effect of, 3-34 
use of, 3~27,44,46 
slow vector, 3-68 
definition, 3-29 
use of, 3-47,50,52 
fast mode, 3-34,37,40,46 
fill mode, 3-50,62 
A and B sides, 3-51,69 
baseline, 3-55,63 
complement mode, 3-52,54 
crossing vectors, 3-51,54 
error registers, 3-32 
origin, 3-52 
polygon subdivision, 3-51 
x or Y fill axis, 3-33,50 
§1,52,55,63 
mode, 3~22,28,50,62 
pen up/down, 3-45,50,63 
use of, 3-49 
operand flow, 4-6 
operands, 4-28 
process, 4-27 
protocol, 4-52 
register values, 3~24,56 


ae 
8 5 


Lae 


Index-5 


a 


Ce 


Index 


4 
3-21, 
3 
6 
. 

3 


Memory , 


1 
, SC Teen 
5 
t 
3 
l 


color, 


Lei 


Se 


e 
. 
and, 
e 
3 
C 
reserved 


l 

e 

f 

n 

2 

Ss 

region, 

O 

i 

eed 


scroll Xx max, 
5 x 
* 
1 


#4 5 . 2 
FR FE e% a Se Se, SS FX FR oh OR wo 
ers 5 2 5 ae re Pe! 
ae ee a0 ei a Wa We Vs We Wa Wa ada 


3 
2,4 
3-4 

2 
2 
8 


i 
1 
. 
1 
16 
4 
3219 
cco. 
. 
. 
und 


50, 
| 4 
1 
„ 
8 


pattern, 


ter 
9 
enable, 


8 

i 

8 

3 

r 

n 

9 
Resolution mode, 


i 
— W he © — a 8 > Ga D = ON O 4) | cet A = rm O tu O 
V 6 ei O gH Ort Yet wi OY W ei N U) — 2 ted — | — OD MM 
Beet POQVN DY Y Dea on FH W © YH Wi O, O. UP © 2 * 3 UO 
OSO DVO OC OF & — 3 4 Or 2 
vt OH hy CM eet & OO — DW 2 he bee 0 — W . 
en on OM ul =o SO ke —_ WW i 2 . — — 
Oo 0 6 : D : 


00 
at 
8 
sal 


e 

re 
i 

hs 


use 
t 
t 
© 
n 
Region, 
0 
Register 
185 
1 


30 


ae 
i 


4-12,29 
4 iit 


oe 


& 


origin, 


5767 


ary 8 


ts. 


operand, 


a Sig sah 


if 


7 


Cy 
sa 
0 


ppin 
1 
a 


HE e, te a ae 
Source 
ie 


a tbe 


= 


am 


4-13 


gc 
ny 


j ig 
4 e 8 


i 


4~14 


4-30 


mbling effect, 
3~84,106 


4-7 


system, 
Oo~-memory mapping 


ess, 
mayne 
St) y 


Mi 


a 


area, 
nstant (video 


nate 


i 


refresh 


SC ke 


- .. 


Process 


Tags 


0% 


coord 


aling proc 
C 


Scroll 


CS ee 
de bee 


Source 2 
Source 2 x 
Source 2 * 
Source/dest 

4~43 
Source edge vector, 

e 3-58 
Status bits, 3- 


operand, 4- 
origin, "3-35,69 
Phy 335,69 


1 
Aen. 
address e 3— 59,63, 65, 


78 
clippi ng, 3219,60 
I/ D receive ready, 3-60 
1/D scroll ready, 3-61,77 
I/D transmit ready, 3~€ 50,76, 


82 
initialization complete, 
paus 3e, 3-24,59,65 


rasterop complete, 
scroll service, 3-22, = 59 
se of, 3-59, 64, 755 79 
vertical blanking, 3-61 
Subsystem timing generation, 
3-4 
. settings, 
Sync phase, 3-74 
Synchronization and blanking, 
3-5 
System § 
system 


5 


214 


specifications, 2-10 
support, 3-7 


Tablet, 2-9, 3 
commands, D-7 
connector pins, 
default state 
modes, D-4 
operation, D-4 
power rating, D-2 
resolution, D-7 
1 time, 

self-test, D-4 
specifications, D-8 
support, C-12 

Test n 


D-7 


3-57,61 


e 3239, 45 
fonts, 3-41, 43 


normal, 3-42 

rotated and scaled, 

var ilable- pitch, 3-43 
Tiling, 4-35 

disabled, 4-12 
Timing generator 

inputs/outputs, 3-4 

TK50, 2-7 


3-44 


and 


chip registers 


commands, 3-57 


VCBO02 address map, 3-7 
VCBO2 DMA gate array, 3-1( 


2 
VCBO2 video subsystem, 
address processor 
1-12 
base module, 1—1, 3-2 
block diagram, 4-2 
chip set interface, 1— 
data manipulation, 1 
FRUS, 5-2 
installation, 2-11 
multiplane support, 1-9 
operational elements, 1 
performance, 1-11 


1 


10 


Index 


07 


1-1, 2-6 
registers, 


1 


—7 


power requirements, 2-10 


4-plane, 1-1, 2-1 
8-plane, 1-1, 2-1 
4~plane module, 1~1,4,5 
principal features, 1— 
private memory, 1—11 


programmable modes, 1-10 


a ase 4—1 
asterops, 1-10 


„ ee applications, 


1-15 
video interfaces, 2 
video processor reg 
1-14 
viewport 
VCB02~B 
2-11 
VCBO02-B module aon 2-6 


8 
iste 


support, 1-9 
cable interconnect 


VCB02-C cable inte connect 


-12 
VCBO2-C module set, 2-7 
Video memory structure, 3 
Video output logic, 3-5 
Video processor 
control registers, 
description, 4-56 
external operand, 4-21 
FIFO, 4-19 
operand fetch, 4-21 
operand processing, 4-2 
2 


4-24 


rs, 


-12 


Video processor chip, 3-26,82, 


4-16 
commands, 


active cycle, 3+75,78,93 
register access, 3~88,90 
functions, 3-36 
pins, 3-98 
registers, 3-82 
loading, 3-76 ,77,85,86 


Index 


Video upgrade path, 3-5 Z-axis, 3-26 
Viewport, 3-19, 4~9,10 addressing mode, 4-56 
VR260, 2-8 definition, 3-26 
VR290, 2-8 I/D command, 3~26,76 
plane address, 3~26,81,90 
Windows, 4-10 register, 3-85 
restrictions, 3-81,85 
X limit, 3-71 processor/bitmap command, 
use of, 3-18,57 4-55 
X scan configuration, 3-71,72, Processor/bitmap transfers, 
73,104 4-53 
X scan count, 3-72 register load, 3-76,88, 4-57 
use of, 3-37,45,85,86 
Y limit, 3-72 Z~block, 3-76,81,85,90 
use of, 3-18,57,65 definition, 3~26 
Y offset, 3-65 Zoom, 3-27 
effect of, 3-30,33,34,41,56 
loading of, 3-22,77 
use of, 3-22,57,72 
scan count, 3-69,70 
¥ scroll constant, 3-65,77 


Index~8 


ͤ———äœ— ̃ —ũ— — — —ä—ͤ—ß . — 


EONS OIA OTIS 


+: 
+: 
+: 
85 
og 
3 
* 
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eee 


eee 


Digital Equipment Corporation ¢ Maynard, MA 01754 


